MASTER TIMING GENERATOR BOARD DESCRIPTION ----------------------------------------- CARD NAME: MASTER TIMING GENERATOR MTG BOARD DESCRIPTION: This board is used to generate the Timing and Synchronization Signals that are used by the First Level Trigger Framework and by the First Level Calorimeter Trigger. This board can also be used to supply general purpose Timing and Sync Signals to other systems in the experiment. This board has 32 independently programmable output signals. Each of these outputs can be programmed to use as its source either: the PROM memory, a bit in a programmable register, or an external signal. Each channel, under programmable control, can have its output enabled and disabled either by a bit in a programmable register or by an external control signal. The time base for incrementing the address to the PROM memory is either the accelerator RF clock, an onboard crystal oscillator, or a bit in a programmable register (the Register Clock Bit). The time base is selected under programmable control and can be enabled to switch automatically from the accelerator RF clock to the onboard crystal clock if the accelerator RF clock input signal should fail. The MTG board uses an input from the beam crossing pickup to reset the PROM address to zero at each beam crossing. If the beam crossing pickup signal is not available the the PROM address is reset to zero after reaching a terminal count that is set in a switch register. Under programmable control either source of a reset signal for the PROM address counter may be selected or one can enable an automatic switch over from beam crossing reset to switch register terminal count reset if the beam crossing signal should fail. The frequency of the time base for incrementing the PROM address counter is 26,552 MHz. This is one half of the accelerator RF frequency. The PROM address increments once every 37.662 nanoseconds. There are about 93 addresses in the 3.5 microseconds between beam crossings. Because the PROMS have 512 addresses they may be divided into two sections of 256 addresses each with each section large enough to cover the 3.5 microsecond period. The section to be used is picked with ROM Address Bit#9. This ROM Address Bit is controled by bit # 5 of the register at Function Address 38. Front panel connectors J3 and J4 provide the 32 External Enable inputs and the 32 External Bit inputs. Front panel connector J5 provides the 53.104 MHz Accelerator Clock input, the Beam Crossing Pulse input, a monitor output for the Prescaled Accelerator Clock as used by the ROM Address Counter, a monitor output for the on board 26.5 MHz oscillator, and a monitor output for the Synchronized Beam Crossing Clock. The connector near the center of the card, J6 is used for wire wrap strapping of certain options. Positions 15 thru 20 provide the Accelerator Clock with various amounts of prescale ( 1, 2 or 4 ). A selection is made from these and connected to positions 11 and 12, the input to the ROM Address Clock selector PAL. The normal wiring is to connect 16 to 12 and 15 to 11. Positions 1 thru 6 are used to select the method of resetting the Accelerator Clock Prescaler. Pin 6 is the raw Beam Crossing Pulse, and pin 5 is a synchronized Beam Crossing Pulse. Pin 2 is the Set input for the Accelerator Clock Prescaler and pin 1 is the Clear input for the Accelerator Clock Prescaler. The normal connection is pin 5 to pin 1. PROGRAMMING: There are two basic sections of the Master Timing Generator that must be programmed. The first is the ROM Address Counter and the second is the control logic for each of the 32 Timing and sync Signal outputs. The programming of the ROM Address Counter involves three different Function Address on the Master Timing Generator Card: FA37, FA38, and FA39. These three registers are all Read Write registers. Function Address 37 The Auxiliary Control Register ------------------- -------------------------------- Bit #1: 0 => Stop the ROM Address Counter. 1 => Enable the ROM Address Counter to increment. Bit #2: 0 => Enable the Terminal Count Switch Register Comparator to reset the ROM Address Counter. 1 => Disable the Terminal Count Switch Register Comparator from resetting the ROM Address Counter. Bit #3: 0 => Disable the Beam Crossing Input from resetting the ROM Address Counter. 1 => Enable the Beam Crossing Input to reset the Rom Address Counter. Bit #4: 0 => Disable the Beam Crossing Input from resetting the ROM Address Counter PreScaler. 1 => Enable the Beam Crossing Input to reset the ROM Address Counter PreScaler. Bit #5: 0 => Set ROM Address Bit #9 to a 0 1 => Set ROM Address Bit #9 to a 1 Bit #6: . . NOT USED . Bit #8: Function Address 38 The ROM Address Counter Clock Selector Register ------------------- ------------------------------------------------- Bit #1: Select Internal Oscillator Bit Bit #2: Select External Oscillator Bit Bit #3: Shift External Oscillator 180 Degrees Bit Bit #4: Register Clock Bit Bit #1 Bit #2 SELECT SELECT ROM ADDRESS COUNTER CLOCK INTERNAL EXTERNAL SOURCE -------- -------- ------------------------- 0 0 Select the Register Clock Bit (Function Address 38 Bit 4) as the ROM Address Counter Clock Source. 1 0 Select the onboard crystal oscillator as the ROM Address Counter Clock Source. 0 1 Select the external oscillator (the Accelerator RF) as the ROM Address Counter Clock Source. 1 1 Enable the automatic selection of the onboard or external oscillator as the ROM Address Counter Clock Source. If the External Oscillator is operating it will be selected. If the External Oscillator is not operating the the Onboard Oscillator will be selected. Bit #3: 0 => The External Oscillator is not shifted 180 degrees. 1 => The External Oscillator is shifted 180 degrees. Bit #4: 0 => If Bits #1 and #2 are both 0 (i.e. the Register Clock Bit has been selected as the ROM Address Counter Clock Source), then the ROM Address Counter Clock is in the 0 state. 1 => If Bits #1 and #2 are both 0 (i.e. the Register Clock Bit has been selected as the ROM Address Counter Clock Source), then the ROM Address Counter Clock is in the 1 state. Function Address 39 The ROM Address Counter Register ------------------- ---------------------------------- Bit #1 ROM Address Counter Bit #1 LSB . . . . . . Bit #8 ROM Address Counter Bit #8 MSB This register can be read at anytime and will give the current state of the ROM Address Counter. This register can be used to program the state of the ROM Address Counter in the following way: 1. Stop the ROM Address Counter by setting Bit #1 of Function Address 37 to a 0. This is the ROM Address Counter Enable bit. 2. Select the Register Clock Bit as the source for the ROM Address Counter Clock by setting Bits #1 and #2 of Function Address 38 to 0. 3. Set the Register Clock Bit (Bit #4 Function Address 38) to 0. 4. Load the ROM Address Counter Register with the desired value for the ROM Address Counter. 5. Set the Register Clock Bit to a 1. 6. Set the Register Clock Bit to a 0. The programming of the Control Logic for the 32 Timing and Synchronization Signal Outputs involves 32 different Function Address on the Master Timing Generator Card: Function Address 0 thru Function Address 31. These 32 registers are all Read Write registers (except Bit #6 of each register which is read only). Function Address 0 controls Timing and Synchronization Signal 1, ... , and Function Address 31 controls Timing and Synchronization Signal 32. Function Address 0 The Control Logic Register for Timing and Synch ------------------ Signal #1 ------------------------------------------------- Bit #1 Select Register Bit (Bit #5) as the source of the Timing & Sync Signal. Bit #2 Select the External Bit Input as the source of the Timing and Sync Signal. Bit #3 Select the ROM as the source of Timing and Sync Signal. Bit #4 Enable the Timing and Sync Signal Output. Note: the Timing and Sync Signal Output can also be enabled by the External Enable signal. Bit #5 Register Bit that can be used as the source of the Timing and Sync Signal. Bit #6 This is a read only bit that indicates the state of this Timing and Sync Signal output at the last time that this Function Address was loaded. i.e. 0 => the Timing and Sync Signal is Low and 1 => the Timing and Sync Signal is High. Bit1 Bit2 Bit3 Bit#4 Bit#5 Timing and Sync Signal Output ---- ---- ---- ----- ----- ---------------------- 0 0 0 0 x No source is selected, Timing and Sync Signal Output is Low. 1 0 0 0 0 Bit#5 is selected as source, Timing and Sync Signal Output is Low. 1 0 0 0 1 Bit#5 is selected as source, if the External Enable is High, then Timing and Sync Signal Output = High. 1 0 0 1 0 Bit#5 is selected as source, Enable Bit#4 is High, Timing and Synch Signal Output is Low. 1 0 0 1 1 Bit#5 is selected as source, Enable Bit#4 is High, Timing and Synch Signal Output is High. 0 1 0 0 x The External Bit is selected as the Source, if the External Bit AND the External Enable are both High, then the Timing and Sync Signal Output is High. 0 1 0 1 x The External Bit is selected as the source, Enable Bit#4 is High, if the External Bit is High, then the Timing and Sync Signal Output is High. 0 0 1 0 x The ROM is selected as the source of the Timing and Sync Signal. If the External Enable is High then the ROM signal will appear as the Timing and Sync Signal Output. 0 0 1 1 x This ROM is selected as the source of the Timing and Sync Signal. Enable Bit#4 is High, so the ROM signal appears as the Timing and sync Signal Output. MASTER TIMING GENERATOR BOARD CONNECTORS AND SWITCHES ----------------------------------------------------- REAR ------------------------------ | | J1 | | J2 | | | --------- ------- | | | | | | MTG | | CARD | | ---- | | |J6| | | ---- | | | | ------ ------ ---- | | | J3 | | J4 | |J5| | ------------------------------ FRONT CONNECTOR J1 THE TIMMING AND SYNCHRONIZATION SIGNAL OUTPUTS ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 NOT USED . . . . . . 66 NOT USED 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown Timing & Sync. Signal Bit#1 Non-inverted IN 1 NTS1 76 tan Timing & Sync. Signal Bit#1 inverted IN 2 ITS1 77 red Timing & Sync. Signal Bit#2 Non-inverted IN 3 NTS2 78 tan Timing & Sync. Signal Bit#2 inverted IN 4 ITS2 79 orange Timing & Sync. Signal Bit#3 Non-inverted IN 5 NTS3 80 tan Timing & Sync. Signal Bit#3 inverted IN 6 ITS3 81 yellow Timing & Sync. Signal Bit#4 Non-inverted IN 7 NTS4 82 tan Timing & Sync. Signal Bit#4 inverted IN 8 ITS4 83 green Timing & Sync. Signal Bit#5 Non-inverted IN 9 NTS5 84 tan Timing & Sync. Signal Bit#5 inverted IN 10 ITS5 85 blue Timing & Sync. Signal Bit#6 Non-inverted IN 11 NTS6 86 tan Timing & Sync. Signal Bit#6 inverted IN 12 ITS6 87 violet Timing & Sync. Signal Bit#7 Non-inverted IN 13 NTS7 88 tan Timing & Sync. Signal Bit#7 inverted IN 14 ITS7 89 grey Timing & Sync. Signal Bit#8 Non-inverted IN 15 NTS8 90 tan Timing & Sync. Signal Bit#8 inverted IN 16 ITS8 91 white Timing & Sync. Signal Bit#9 Non-inverted IN 17 NTS9 92 tan Timing & Sync. Signal Bit#9 inverted IN 18 ITS9 93 black Timing & Sync. Signal Bit#10 Non-inverted IN 19 NTS10 94 tan Timing & Sync. Signal Bit#10 inverted IN 20 ITS10 95 brown Timing & Sync. Signal Bit#11 Non-inverted IN 21 NTS11 96 tan Timing & Sync. Signal Bit#11 inverted IN 22 ITS11 97 red Timing & Sync. Signal Bit#12 Non-inverted IN 23 NTS12 98 tan Timing & Sync. Signal Bit#12 inverted IN 24 ITS12 99 orange Timing & Sync. Signal Bit#13 Non-inverted IN 25 NTS13 100 tan Timing & Sync. Signal Bit#13 inverted IN 26 ITS13 101 yellow Timing & Sync. Signal Bit#14 Non-inverted IN 27 NTS14 102 tan Timing & Sync. Signal Bit#14 inverted IN 28 ITS14 103 green Timing & Sync. Signal Bit#15 Non-inverted IN 29 NTS15 104 tan Timing & Sync. Signal Bit#15 inverted IN 30 ITS15 105 blue Timing & Sync. Signal Bit#16 Non-inverted IN 31 NTS16 106 tan Timing & Sync. Signal Bit#16 inverted IN 32 ITS16 107 violet Timing & Sync. Signal Bit#17 Non-inverted IN 33 NTS17 108 tan Timing & Sync. Signal Bit#17 inverted IN 34 ITS17 109 grey Timing & Sync. Signal Bit#18 Non-inverted IN 35 NTS18 110 tan Timing & Sync. Signal Bit#18 inverted IN 36 ITS18 111 white Timing & Sync. Signal Bit#19 Non-inverted IN 37 NTS19 112 tan Timing & Sync. Signal Bit#19 inverted IN 38 ITS19 113 black Timing & Sync. Signal Bit#20 Non-inverted IN 39 NTS20 114 tan Timing & Sync. Signal Bit#20 inverted IN 40 ITS20 115 brown Timing & Sync. Signal Bit#21 Non-inverted IN 41 NTS21 116 tan Timing & Sync. Signal Bit#21 inverted IN 42 ITS21 117 red Timing & Sync. Signal Bit#22 Non-inverted IN 43 NTS22 118 tan Timing & Sync. Signal Bit#22 inverted IN 44 ITS22 119 orange Timing & Sync. Signal Bit#23 Non-inverted IN 45 NTS23 120 tan Timing & Sync. Signal Bit#23 inverted IN 46 ITS23 121 yellow Timing & Sync. Signal Bit#24 Non-inverted IN 47 NTS24 122 tan Timing & Sync. Signal Bit#24 inverted IN 48 ITS24 123 green Timing & Sync. Signal Bit#25 Non-inverted IN 49 NTS25 124 tan Timing & Sync. Signal Bit#25 inverted IN 50 ITS25 125 blue Timing & Sync. Signal Bit#26 Non-inverted IN 51 NTS26 126 tan Timing & Sync. Signal Bit#26 inverted IN 52 ITS26 127 violet Timing & Sync. Signal Bit#27 Non-inverted IN 53 NTS27 128 tan Timing & Sync. Signal Bit#27 inverted IN 54 ITS27 129 grey Timing & Sync. Signal Bit#28 Non-inverted IN 55 NTS28 130 tan Timing & Sync. Signal Bit#28 inverted IN 56 ITS28 131 white Timing & Sync. Signal Bit#29 Non-inverted IN 57 NTS29 132 tan Timing & Sync. Signal Bit#29 inverted IN 58 ITS29 133 black Timing & Sync. Signal Bit#30 Non-inverted IN 59 NTS30 134 tan Timing & Sync. Signal Bit#30 inverted IN 60 ITS30 135 brown Timing & Sync. Signal Bit#31 Non-inverted IN 61 NTS31 136 tan Timing & Sync. Signal Bit#31 inverted IN 62 ITS31 137 red Timing & Sync. Signal Bit#32 Non-inverted IN 63 NTS32 138 tan Timing & Sync. Signal Bit#32 inverted IN 64 ITS32 139 Ground GND 140 Ground GND CONNECTOR J2 THE SPECIFIC BACKPLANE BUS CONNECTOR ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown Timing & Sync. Signal A Non-inverted IN 1 NTSA 76 tan Timing & Sync. Signal A Inverted IN 2 ITSA 77 red Timing & Sync. Signal B Non-inverted IN 3 NTSB 78 tan Timing & Sync. Signal B Inverted IN 4 ITSB 79 orange Timing & Sync. Signal C Non-inverted IN 5 NTSC 80 tan Timing & Sync. Signal C Inverted IN 6 ITSC 81 yellow Timing & Sync. Signal D Non-inverted IN 7 NTSD 82 tan Timing & Sync. Signal D Inverted IN 8 ITSD 83 green Timing & Sync. Signal E Non-inverted IN 9 NTSE 84 tan Timing & Sync. Signal E Inverted IN 10 ITSE 85 blue Timing & Sync. Signal F Non-inverted IN 11 NTSF 86 tan Timing & Sync. Signal F Inverted IN 12 ITSF 87 violet Timing & Sync. Signal G Non-inverted IN 13 NTSG 88 tan Timing & Sync. Signal G Inverted IN 14 ITSG 89 grey TTS-H LED's OFF Non-inverted IN 15 NTSH 90 tan TTS-H LED's OFF Inverted IN 16 ITSH 91 white Card Address Bit#1 Non-inverted IN 17 NAC1 92 tan Card Address Bit#1 Inverted IN 18 IAC1 93 black Card Address Bit#2 Non-inverted IN 19 NAC2 94 tan Card Address Bit#2 Inverted IN 20 IAC2 95 brown Card Address Bit#3 Non-inverted IN 21 NAC3 96 tan Card Address Bit#3 Inverted IN 22 IAC3 97 red Card Address Bit#4 Non-inverted IN 23 NAC4 98 tan Card Address Bit#4 Inverted IN 24 IAC4 99 orange Card Address Bit#5 Non-inverted IN 25 NAC5 100 tan Card Address Bit#5 Inverted IN 26 IAC5 101 yellow Card Address Bit#6 Non-inverted IN 27 NAC6 102 tan Card Address Bit#6 Inverted IN 28 IAC6 103 green Function Address Bit#1 Non-inverted IN 29 NAF1 104 tan Function Address Bit#1 Inverted IN 30 IAF1 105 blue Function Address Bit#2 Non-inverted IN 31 NAF2 106 tan Function Address Bit#2 Inverted IN 32 IAF2 107 violet Function Address Bit#3 Non-inverted IN 33 NAF3 108 tan Function Address Bit#3 Inverted IN 34 IAF3 109 grey Function Address Bit#4 Non-inverted IN 35 NAF4 110 tan Function Address Bit#4 Inverted IN 36 IAF4 111 white Function Address Bit#5 Non-inverted IN 37 NAF5 112 tan Function Address Bit#5 Inverted IN 38 IAF5 113 black Function Address Bit#6 Non-inverted IN 39 NAF6 114 tan Function Address Bit#6 Inverted IN 40 IAF6 115 brown Function Address Bit#7 Non-inverted IN 41 NAF7 116 tan Function Address Bit#7 Inverted IN 42 IAF7 117 red Function Address Bit#8 Non-inverted IN 43 NAF8 118 tan Function Address Bit#8 Inverted IN 44 IAF8 119 orange Strobe Non-inverted IN 45 NSTB 120 tan Strobe Inverted IN 46 ISTB 121 yellow Direction Non-inverted IN 47 NDIR 122 tan Direction Inverted IN 48 IDIR 123 green Bidirectional Data Bit#1 Non-inverted IN 49 NDB1 124 tan Bidirectional Data Bit#1 Inverted IN 50 IDB1 125 blue Bidirectional Data Bit#2 Non-inverted IN 51 NDB2 126 tan Bidirectional Data Bit#2 Inverted IN 52 IDB2 127 violet Bidirectional Data Bit#3 Non-inverted IN 53 NDB3 128 tan Bidirectional Data Bit#3 Inverted IN 54 IDB3 129 grey Bidirectional Data Bit#4 Non-inverted IN 55 NDB4 130 tan Bidirectional Data Bit#4 Inverted IN 56 IDB4 131 white Bidirectional Data Bit#5 Non-inverted IN 57 NDB5 132 tan Bidirectional Data Bit#5 Inverted IN 58 IDB5 133 black Bidirectional Data Bit#6 Non-inverted IN 59 NDB6 134 tan Bidirectional Data Bit#6 Inverted IN 60 IDB6 135 brown Bidirectional Data Bit#7 Non-inverted IN 61 NDB7 136 tan Bidirectional Data Bit#7 Inverted IN 62 IDB7 137 red Bidirectional Data Bit#8 Non-inverted IN 63 NDB8 138 tan Bidirectional Data Bit#8 Inverted IN 64 IDB8 139 Ground GND 140 Ground GND CONNECTOR J3 EXTERNAL ENABLE 1 - 16 AND EXTERNAL BIT 1 - 16 ------------- INPUT CONNECTOR ------------------------------------------------------------------------------ CONNECTOR J3 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 External Enable # 16 Non-Inverted NEXEN16 2 External Enable # 16 Inverted IEXEN16 3 External Bit # 16 Non-Inverted NEXBT16 4 External Bit # 16 Inverted IEXBT16 5 External Bit # 15 Non-Inverted NEXBT15 6 External Bit # 15 Inverted IEXBT15 7 External Enable # 15 Non-Inverted NEXEN15 8 External Enable # 15 Inverted IEXEN15 9 External Enable # 14 Non-Inverted NEXEN14 10 External Enable # 14 Inverted IEXEN14 11 External Bit # 14 Non-Inverted NEXBT14 12 External Bit # 14 Inverted IEXBT14 13 External Bit # 13 Non-Inverted NEXBT13 14 External Bit # 13 Inverted IEXBT13 15 External Enable # 13 Non-Inverted NEXEN13 16 External Enable # 13 Inverted IEXEN13 17 External Enable # 12 Non-Inverted NEXEN12 18 External Enable # 12 Inverted IEXEN12 19 External Bit # 12 Non-Inverted NEXBT12 20 External Bit # 12 Inverted IEXBT12 21 External Bit # 11 Non-Inverted NEXBT11 22 External Bit # 11 Inverted IEXBT11 23 External Enable # 11 Non-Inverted NEXEN11 24 External Enable # 11 Inverted IEXEN11 25 External Enable # 10 Non-Inverted NEXEN10 26 External Enable # 10 Inverted IEXEN10 27 External Bit # 10 Non-Inverted NEXBT10 28 External Bit # 10 Inverted IEXBT10 29 External Bit # 9 Non-Inverted NEXBT9 30 External Bit # 9 Inverted IEXBT9 31 External Enable # 9 Non-Inverted NEXEN9 32 External Enable # 9 Inverted IEXEN9 33 External Enable # 8 Non-Inverted NEXEN8 34 External Enable # 8 Inverted IEXEN8 35 External Bit # 8 Non-Inverted NEXBT8 36 External Bit # 8 Inverted IEXBT8 37 External Bit # 7 Non-Inverted NEXBT7 38 External Bit # 7 Inverted IEXBT7 39 External Enable # 7 Non-Inverted NEXEN7 40 External Enable # 7 Inverted IEXEN7 41 External Enable # 6 Non-Inverted NEXEN6 42 External Enable # 6 Inverted IEXEN6 43 External Bit # 6 Non-Inverted NEXBT6 44 External Bit # 6 Inverted IEXBT6 45 External Bit # 5 Non-Inverted NEXBT5 46 External Bit # 5 Inverted IEXBT5 47 External Enable # 5 Non-Inverted NEXEN5 48 External Enable # 5 Inverted IEXEN5 49 External Enable # 4 Non-Inverted NEXEN4 50 External Enable # 4 Inverted IEXEN4 51 External Bit # 4 Non-Inverted NEXBT4 52 External Bit # 4 Inverted IEXBT4 53 External Bit # 3 Non-Inverted NEXBT3 54 External Bit # 3 Inverted IEXBT3 55 External Enable # 3 Non-Inverted NEXEN3 56 External Enable # 3 Inverted IEXEN3 57 External Enable # 2 Non-Inverted NEXEN2 58 External Enable # 2 Inverted IEXEN2 59 External Bit # 2 Non-Inverted NEXBT2 60 External Bit # 2 Inverted IEXBT2 61 External Bit # 1 Non-Inverted NEXBT1 62 External Bit # 1 Inverted IEXBT1 63 External Enable # 1 Non-Inverted NEXEN1 64 External Enable # 1 Inverted IEXEN1 CONNECTOR J4 EXTERNAL ENABLE 17 - 32 AND EXTERNAL BIT 17 - 32 ------------- INPUT CONNECTOR ------------------------------------------------------------------------------ CONNECTOR J4 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 External Enable # 32 Non-Inverted NEXEN32 2 External Enable # 32 Inverted IEXEN32 3 External Bit # 32 Non-Inverted NEXBT32 4 External Bit # 32 Inverted IEXBT32 5 External Bit # 31 Non-Inverted NEXBT31 6 External Bit # 31 Inverted IEXBT31 7 External Enable # 31 Non-Inverted NEXEN31 8 External Enable # 31 Inverted IEXEN31 9 External Enable # 30 Non-Inverted NEXEN30 10 External Enable # 30 Inverted IEXEN30 11 External Bit # 30 Non-Inverted NEXBT30 12 External Bit # 30 Inverted IEXBT30 13 External Bit # 29 Non-Inverted NEXBT29 14 External Bit # 29 Inverted IEXBT29 15 External Enable # 29 Non-Inverted NEXEN29 16 External Enable # 29 Inverted IEXEN29 17 External Enable # 28 Non-Inverted NEXEN28 18 External Enable # 28 Inverted IEXEN28 19 External Bit # 28 Non-Inverted NEXBT28 20 External Bit # 28 Inverted IEXBT28 21 External Bit # 27 Non-Inverted NEXBT27 22 External Bit # 27 Inverted IEXBT27 23 External Enable # 27 Non-Inverted NEXEN27 24 External Enable # 27 Inverted IEXEN27 25 External Enable # 26 Non-Inverted NEXEN26 26 External Enable # 26 Inverted IEXEN26 27 External Bit # 26 Non-Inverted NEXBT26 28 External Bit # 26 Inverted IEXBT26 29 External Bit # 25 Non-Inverted NEXBT25 30 External Bit # 25 Inverted IEXBT25 31 External Enable # 25 Non-Inverted NEXEN25 32 External Enable # 25 Inverted IEXEN25 33 External Enable # 24 Non-Inverted NEXEN24 34 External Enable # 24 Inverted IEXEN24 35 External Bit # 24 Non-Inverted NEXBT24 36 External Bit # 24 Inverted IEXBT24 37 External Bit # 23 Non-Inverted NEXBT23 38 External Bit # 23 Inverted IEXBT23 39 External Enable # 23 Non-Inverted NEXEN23 40 External Enable # 23 Inverted IEXEN23 41 External Enable # 22 Non-Inverted NEXEN22 42 External Enable # 22 Inverted IEXEN22 43 External Bit # 22 Non-Inverted NEXBT22 44 External Bit # 22 Inverted IEXBT22 45 External Bit # 21 Non-Inverted NEXBT21 46 External Bit # 21 Inverted IEXBT21 47 External Enable # 21 Non-Inverted NEXEN21 48 External Enable # 21 Inverted IEXEN21 49 External Enable # 20 Non-Inverted NEXEN20 50 External Enable # 20 Inverted IEXEN20 51 External Bit # 20 Non-Inverted NEXBT20 52 External Bit # 20 Inverted IEXBT20 53 External Bit # 19 Non-Inverted NEXBT19 54 External Bit # 19 Inverted IEXBT19 55 External Enable # 19 Non-Inverted NEXEN19 56 External Enable # 19 Inverted IEXEN19 57 External Enable # 18 Non-Inverted NEXEN18 58 External Enable # 18 Inverted IEXEN18 59 External Bit # 18 Non-Inverted NEXBT18 60 External Bit # 18 Inverted IEXBT18 61 External Bit # 17 Non-Inverted NEXBT17 62 External Bit # 17 Inverted IEXBT17 63 External Enable # 17 Non-Inverted NEXEN17 64 External Enable # 17 Inverted IEXEN17 CONNECTOR J5 ACCELERATOR CLOCK INPUT, BEAM CROSSING PULSE INPUT, ------------- AND CLOCK MONITOR OUTPUTS ------------------------------------------------------------------------------ CONNECTOR J5 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 Accelerator Clock Input Non-Inverted NACCI 2 Accelerator Clock Input Inverted IACCI 3 Ground GND 4 Ground GND 5 Beam Crossing Pulse Input Non-Inverted NBCPI 6 Beam Crossing Pulse Input Inverted IBCPI 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 ROM Address Counter Clock Non-Inverted NRACC 12 ROM Address Counter Clock Inverted IRACC 13 On Board Oscillator Monitor Non-Inverted NOBOM 14 On Board Oscillator Monitor Inverted IOBOM 15 Prescaler Reset Monitor Non-Inverted NPRTM 16 Prescaler Reset Monitor Inverted IPRTM CONNECTOR J6 HARD WIRE CLOCK AND BEAM CROSSING SELECTORS -------------- ------------------------------------------------------------------------------ CONNECTOR J6 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 ROM Address Counter Prescaler Reset Input CLEAR RAPC 2 ROM Address Counter Prescaler Reset Input SET RAPS 3 Ground GND 4 Ground GND 5 Synchronized Beam Crossing Pulse For PRSC Reset SBCP 6 Raw Beam Crossing Pulse For Prescaler Reset RBCP 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Selected Accelerator Clock Input Inverted ISACC 12 Selected Accelerator Clock Input Non-Inverted NSACC 13 Ground GND 14 Ground GND 15 Accelerator Clock Divided By 2 Inverted IACD2 16 Accelerator Clock Divided By 2 Non-Inverted NACD2 17 Accelerator Clock Divided By 4 Inverted IACD4 18 Accelerator Clock Divided By 4 Non-Inverted NACD4 19 Accelerator Clock Inverted IACC 20 Accelerator Clock Non-Inverted NACC SWITCH U85 CARDS ADDRESS SELECTOR SWITCH This switch controls the Card Address at which this card will wake up. When a switch is closed the coresponding bit in the Card Address is a 0 and when a switch is open then the corresponding bit is a 1. ADDRESS SWITCH SECTION CARD ADDRESS BIT BIT VALUE ---------------- ------------------ ----------- 1 6 32 2 5 16 3 4 8 4 3 4 5 2 2 6 1 1 7 ALWAYS CLOSED 8 ALWAYS CLOSED SWITCH UXXX TERMINAL ROM ADDRESS COUNT SELECTOR SWITCH This switch controls the terminal count of the ROM address counter (the last count before a reset is forced). ROM ADDRESS SWITCH SECTION ROM ADDRESS BIT BIT VALUE ---------------- ----------------- ------------- 1 1 1 2 2 2 3 3 4 4 4 8 5 5 16 6 6 32 7 7 64 8 8 128 BOARD ORDERS HISTORY: 8 BOARDS ORDERED July 1986 ETCH REVISION HISTORY: REVISION A July 1986 ECO HISTORY: none POWER REQUIREMENTS: VCC +5.0 Volts at 49 Amps VEE -5.2 Volts at 72 Amps PARTS LIST: QUANTITY ITEM -------- ------ 1 74 LS 02 2 74 AS 04 1 74 LS 05 2 74 AS 08 1 74 AS 74 11 74 ALS 138 2 74 AS 163 1 74 LS 240 5 74 ALS 245 2 74 ALS 520 3 74 ALS 541 1 74 ALS 574 1 10 H 101 1 10 H 116 11 10 H 124 23 10 H 125 1 10 H 131 3 10 H 188 4 63RA481A 1 PAL16R4ACN 32 PAL16R6ACN 2 7902 13 LED 2 8 POSITION DIP SWITCH 1 OSCILLATOR MODULE 26.552 MHz 17 56 OHM 8 PIN SIP 3 330 OHM 8 PIN SIP 7 470 OHM 8 PIN SIP 8 110 OHM 16 PIN DIP 2 140 pin connectors right angle 2 64 pin connectors right angle 1 16 pin connector right angle 1 20 pin connector straight MODIFICATIONS TO REVISION A: ------------------------------ Cut the following traces: Component Side Trace connected to U43 pin 5 Component Side Trace connected to U47 pin 5 Component Side Trace connected to U51 pin 5 Component Side Trace connected to U55 pin 5 Solder Side Trace between U90 pin 4 and U91 pin 4 Solder Side Trace between U90 pin 4 and Plate Thru Component Side Vcc to Vee short above pin 9 of U102 Add the following wires: Component Side U90 pin 4 to U90 pin 8 U91 pin 4 to Plate Thru isolate from U90 in the last step above U43 pin 5 to U43 pin 8 U47 pin 5 to U47 pin 8 U51 pin 5 to U51 pin 8 U55 pin 5 to U55 pin 8 End of Modifications for Revision A as of 18-SEPT-1986. SETUP - MODIFICATIONS TO THE MTG'S FOR USE AT D-ZERO HALL --------------------------------------------------------- The wire wrap wiring on J6 must be correct for all of the above setup to operate correctly. J6 must be wrapped to directly connect the Accelerator Clock Input the the ROM Address Counter Selector PAL (the Accelerator Pre-Scaler is by passed). This is done by wrapping J6 pin 11 to pin 19 and J6 pin 12 to pin 20. Part of the ROM Address Counter Reset circuit on the MTG board must be changed for it to operate properly in the "slave" mode. This is most easly done by removing the 74AS74 at U108 and replacing it with a socket. In this way one may either insert a 74AS74 for normal operation, or insert a jumper between pins 6 and 11 for "slave" operation. USE OF THE CY7C245A-25 CYPRESS PROMS TO REPLACE THE MMI 63RA481A'S ------------------------------------------------------------------- PIN NUMBER 63RA481 CY7C245 MTG CONNECTION ------ ------- ------- -------------- 1 A7 A7 2 A6 A6 3 A5 A5 4 A4 A4 5 A3 A3 6 A2 A2 7 A1 A1 8 A0 A0 9 Q0 Q0 10 Q1 Q1 11 Q2 Q2 13 Q3 Q3 14 Q4 Q4 15 Q5 Q5 16 Q6 Q6 17 Q7 Q7 18 CLK CLK 19 /ES /E-/ES TIED LOW ON MTG 20 /CLR /INIT TIED HIGH ON MTG 21 /E A10 TIED LOW ON MTG 22 /PRS A9 TIED HIGH ON MTG 23 A8 A8 Thus all is "ok" to use the 245A's except line A9 is going to be High and thus the MTG data must start not at address 0 but at address 512 (200 hex). TIMING CONSIDERATIONS IN RESETING THE MTG ROM ADDRESS ----------------------------------------------------- ROM ADDRESS COUNTER CLOCK PATH 1. Received by a 10H116 2. Converted to TTL by a 10H124 3. Processed by a 16R4A (non-latched section) 4. Buffered by a 74AS04 5. Delivered to the ROM Address Counter CLK 74AS163 pin 2 and the Output Register Clock CY7C245A-25. ROM ADDRESS COUNTER RESET SIGNAL PATH 1. Received by a 10H116 2. Converted to TTL by a 10H124 3. Processed by a 74AS08 4. Delivered to the ROM Address Counter Clear 74AS163 pin 1. What we want is a ROM Address Counter Reset signal that goes LOW before the positive Clock edge that should take the output of the counter to zero. This reset signal must be LOW by at least a setup time before this clock edge and must be high again at least a setup time before the positive clock edge that takes the output of the Rom Address Counter from zero to one.