_________________________________________________________________ | | | MASTER TIMING GENERATOR | | | | Revision B | | BOARD DESCRIPTION | |_______________________________________________________________| 8-AUG-1990 Current Rev. 1-NOV-1995 BOARD DESCRIPTION: This board is used to generate the Timing and Synchronization Signals that are used by the First Level Trigger Framework and by the First Level Calorimeter Trigger. This board can also be used to supply general purpose Timing and Sync Signals to other systems in the experiment. This board has 32 independently programmable output signals. Each of these outputs can be programmed to use as its source either a PROM memory, a bit in a programmable register, or one of the two external input signals per channel. Each channel uses a PAL to make combinations of its input sources. Each channel, under programmable control, can have its output enabled or disabled either by a bit in a programmable register or by its external input signals. The timebase for incrementing the address to the PROM memory is either the ACCELERATOR RF CLOCK input on connector J6, an ON-BOARD CRYSTAL OSCILLATOR, or the MANUAL CLOCK bit in the PROM ADDRESS COUNTER CSR at Function Address 37. The time base is selected under programmable control also via the PROM ADDRESS COUNTER CSR. All of these three clock sources are gated by the PROM COUNTER CLOCK ENABLE signal on connector J6. The PROM COUNTER CLOCK ENABLE input defaults High (i.e. the counter clock is enabled) if no signal is connected to this input. The MTG allows a BEAM CROSSING PULSE input signal, also on connector J6, to set the PROM address to the value stored in the PROM ADDRESS COUNTER PRESET register at each beam crossing. The PROM address counter can also be preset to this value by enabling the terminal count reset via the PROM ADDRESS COUNTER CSR, whereupon the counter will reset to the address stored in the PROM ADDRESS COUNTER PRESET register when the PROM ADDRESS COUNTER value matches that in the PROM TERMINAL ADDRESS register. The PROM ADDRESS COUNTER PRESET register is found at function addresses 33 (LSB) and 34 (MSB). The PROM TERMINAL ADDRESS register is located at function addresses 35 (LSB) and 36 (MSB). Both of these register pairs are ten bits wide. All higher order bits (bits above the 10th) have no effect on MTG operation. The PROM address counter can also be reset to zero asynchronously using the MANUAL RESET bit in the PROM ADDRESS COUNTER CSR. The PROM ADDRESS COUNTER can be read asynchronously through function addresses 38 (LSB) and 39 (MSB). The frequency of the time base for incrementing the PROM address counter is 26,552 MHz. This is one half of the Fermilab accelerator RF frequency. The PROM address increments once every 37.662 nanoseconds. The RF system at Fermi operates at 53.104 MHz and there are 1113 RF buckets around the accelerator. There are 93 PROM addresses in the 3.5 microseconds between beam crossings. The full turn around the Fermilab accelerator requires 557 addresses (6 beam crossings). Because the PROM's have 2048 addresses they may be divided into two sections of 1024 addresses each with each section large enough to cover the 21 microsecond period. The section to be used is selected with the PROM BANK SELECT BIT located in the PROM ADDRESS COUNTER CSR at Function Address 37. Front panel connectors J4 and J5 accept the two external input signals for each of the 32 channels on the MTG card (a total of 32 External Enable inputs and the 32 External Bit inputs). Front panel connector J6 accepts the 26.552 MHz ACCELERATOR CLOCK input, the BEAM CROSSING PULSE input, a PROM COUNTER CLOCK ENABLE input, and provides monitor outputs for the PROM ADDRESS COUNTER CLOCK SIGNAL, the PROM ADDRESS COUNTER RESET SIGNAL (as selected by the PROM ADDRESS COUNTER CSR), and a monitor for the ONBOARD CRYSTAL OSCILLATOR. Note that the reset monitor will not reveal any reset activity initiated by software. ie; the monitor will not reflect the status of the asynchronous MANUAL RESET bit in the PROM ADDRESS COUNTER CSR. All of the bits in the PROM ADDRESS COUNTER CSR are displayed with LED's at the extreme right-hand edge of the card. PROGRAMMING: There are two basic sections of the Master Timing Generator that must be programmed. The first is the PROM ADDRESS COUNTER and the second is the control logic (Bit PAL) for each of the 32 Timing and Sync Signal outputs. The following table summarizes all of the progammable registers and their Function Addresses on the MTG Card. MTG REVISION B FUNCTION ADDRESSES ------------------------------------------------- FUNCTION ADDRESS CONTROL REGISTER ---------- ------------------------------------------------- 0 Control of Timing & Sync Channel #1 . . . . 31 Control of Timing & Sync Channel #32 33 PROM Address Counter Preset Register LSB 34 PROM Address Counter Preset Register MSB 35 PROM Address Counter Terminal Address Register LSB 36 PROM Address Counter Terminal Address Register MSB 37 PROM Address Counter Control Status Register 38 PROM Address LSB (read only) 39 PROM Address MSB (read only) PROGRAMMING of the PROM ADDRESS COUNTER The programming of the PROM Address Counter involves properly loading 5 different registers: the PROM Address Counter Preset Register (LSB and MSB), the PROM Address Counter Terminal Address Register (LSB and MSB), and the PROM Address Counter Control Status Register. All 8 bits in each of these registers is a read/write bit. Each of these registers will be described below. Function Address 33 PROM ADDRESS COUNTER PRESET REGISTER LSB ------------------- ------------------------------------------- Bit #1 PROM ADDRESS COUNTER PRESET Bit #1 . . . . Bit #8 PROM ADDRESS COUNTER PRESET Bit #8 Function Address 34 PROM ADDRESS COUNTER PRESET REGISTER MSB ------------------- ------------------------------------------- Bit #1 PROM ADDRESS COUNTER PRESET Bit #9 Bit #2 PROM ADDRESS COUNTER PRESET Bit #10 Bit #3 Not used by MTG . . . . Bit #8 Not used by MTG Function Address 35 PROM TERMINAL ADDRESS REGISTER LSB ------------------- ------------------------------------ Bit #1 PROM TERMINAL ADDRESS Bit #1 . . . . Bit #8 PROM TERMINAL ADDRESS Bit #8 Function Address 36 PROM TERMINAL ADDRESS REGISTER MSB ------------------- ------------------------------------ Bit #1 PROM TERMINAL ADDRESS Bit #9 Bit #2 PROM TERMINAL ADDRESS Bit #10 Bit #3 Not used by MTG . . . . Bit #8 Not used by MTG Function Address 37 PROM ADDRESS COUNTER CONTROL STATUS REGISTER ------------------- ---------------------------------------------- Bit #1: MANUAL ASYNCHRONOUS RESET BIT 0 => Do not force an asynchronous reset. 1 => Force an asynchronous reset of the PROM Address Counter. Bit #2: EXTERNAL RESET ENABLE 0 => Disable the Beam Crossing Input from resetting the PROM Address Counter. 1 => Enable the Beam Crossing Input to reset the PROM Address Counter. Bit #3: TERMINAL ADDRESS RESET ENABLE 0 => Disable the Terminal Address Comparator from resetting the PROM Address Counter. 1 => Enable the Terminal Address Comparator to reset the PROM Address Counter. Bit #4: PROM BANK SELECT BIT 0 => Set PROM Address Bit #11 to ZERO. This is BANK 1, the first 1024 PROM addresses. 1 => Set PROM Address Bit #11 to ONE. This is BANK 2, the second 1024 PROM addresses. Bit #5: PROM Address Counter Clock MUX control bit A See the table below Bit #6: PROM Address Counter Clock MUX control bit B See the table below Bit #7: Not Used Bit #8: MANUAL CLOCK BIT Increment the PROM Address Counter on ZERO->ONE transitions of this bit if the Manual Clock Bit is selected by PROM Address Counter Clock MUX. PROM ADDRESS COUNTER CLOCK MULTIPLEXOR CONTROL: Bit #6 Bit #5 Control bit B Control bit A Counter Clock Source ------------- ------------- -------------------- ZERO ZERO STOP the clock ZERO ONE ACCELERATOR CLOCK input ONE ZERO ON-BOARD CRYSTAL OSCILLATOR ONE ONE MANUAL CLOCK BIT (CSR Bit #8) The current value of the PROM Address Counter can be read via the PROM Address Counter Registers (LSB and MSB). These register can be read at anytime and will give the current state of the PROM Address Counter. This is a Read-Only register. When doing a C-BUS read cycle on this register one is reading the dynamic state of the PROM Address Counter (i.e. if the PROM Address Counter is incrementing then a bit in this register could be changing state as it is being read). Function Address 38 The PROM ADDRESS COUNTER Register LSB ------------------- --------------------------------------- Bit #1 PROM ADDRESS COUNTER Bit #1 . . . . Bit #8 PROM ADDRESS COUNTER Bit #8 Function Address 39 The PROM ADDRESS COUNTER Register MSB ------------------- --------------------------------------- Bit #1 PROM ADDRESS COUNTER Bit #9 Bit #2 PROM ADDRESS COUNTER Bit #10 Bit #3 PROM ADDRESS COUNTER Bit #11 Bit #4 Always returns a ZERO . . . . Bit #8 Always returns a ZERO TYPICAL PROGRAMMING OF THE PROM ADDRESS COUNTER WHEN USING THE CY7C245A PROMS WHICH WHERE PROGRAMMED STARTING AT ADDRESS 200 (I.E. FOR REV A MTG'S) --------------------------------------------------------------------------- FUNCTION TYPICAL DATA ADDRESS LOADED DECIMAL FUNCTION -------- -------------- --------------------------------------- 33 0 Load 200 hex into the PROM Address 34 2 Counter PreSet Register. 35 92 Load 25C hex into the PROM Address 36 2 Counter Terminal Count Register. 37 36 Select the on board crystal oscillator as the PROM Address Clock and Enable the Terminal Count Comparator to Reset the PROM Address Counter. PROGRAMMING of the MTG Channel Control Logic (Bit PAL) The programming of the Control Logic, a "Bit" PAL, for each of the 32 Timing and Synchronization Signal Outputs involves 32 different Function Addresses on the MTG Card: Function Address 0 through Function Address 31. Each Bit PAL has one byte of configuration data loaded into it to setup the MTG Card. The exact definition of the function of the bits in each byte in these 32 registers depends on what type of Bit PAL's are installed on the MTG. In the examples given in this description it is assumed that the Bit PAL type MTGBIT2 are being used. Even with other types of the Bit PAL's an attempt has been made to maintain the same definition of the bits in the programming byte for all types of Bit PAL's. In the MTGBIT2 type Bit PAL's all of the configuration byte bits are Read/Write (except Bit #6 which is read only). Only bits 1 through 6 are used. Bits 7 and 8 are not used and are undefined during a read operation. Function Address 0 controls Timing and Synchronization Signal 1, ... , and Function Address 31 controls Timing and Synchronization Signal 32. The following example applies to an MTGBIT2 type of Bit PAL used in the output logic of a Timing & Sync Signal from one of the 32 channels on an MTG Revision B card. DEFINITION OF THE BITS IN THE CONFIGURATION BYTE OF THE MTGBIT2 TYPE BIT PAL ---------------------------------------------------- BIT NUMBER FUNCTION OF THE BIT IN THE CONFIGURATION BYTE ---------- ------------------------------------------------------- Bit #1 Select Register Bit (Bit #5) as the source of the Timing & Sync Signal. Bit #2 Select the External Bit Input as the source of the Timing and Sync Signal. Bit #3 Select the PROM as the source of Timing and Sync Signal. Bit #4 Enable the Timing and Sync Signal Output. Note: the Timing and Sync Signal Output can also be enabled by the External Enable signal. Bit #5 Register Bit that can be used as the source of the Timing and Sync Signal. Bit #6 This is a read only bit that indicates the state of this Timing and Sync Signal output at the last time that this Function Address was loaded (written to). i.e. 0 => the Timing and Sync Signal is Low and 1 => the Timing and Sync Signal is High. CONFIGURATION EXAMPLES OF THE MTGBIT2 TYPE OF BIT PAL ------------------------------------------------------------- Bit Bit Bit Bit Bit # 5 # 4 # 3 # 2 # 1 Timing and Sync Signal Output --- --- --- --- --- ------------------------------------ x 0 0 0 0 No source is selected, Timing and Sync Signal Output is Low. 0 0 0 0 1 Bit#5 is selected as source, Timing and Sync Signal Output is Low. 1 0 0 0 1 Bit#5 is selected as source, if the External Enable is High, then Timing and Sync Signal Output = High. 0 1 0 0 1 Bit#5 is selected as source, Enable Bit#4 is High, Timing and Synch Signal Output is Low. 1 1 0 0 1 Bit#5 is selected as source, Enable Bit#4 is High, Timing and Synch Signal Output is High. x 0 0 1 0 The External Bit is selected as the Source, if the External Bit AND the External Enable are both High, then the Timing and Sync Signal Output is High. x 1 0 1 0 The External Bit is selected as the source, Enable Bit#4 is High, if the External Bit is High, then the Timing and Sync Signal Output is High. x 0 1 0 0 The PROM is selected as the source of the Timing and Sync Signal. If the External Enable is High then the PROM signal will appear as the Timing & Sync Signal Output. x 1 1 0 0 This PROM is selected as the source of the Timing and Sync Signal. Enable Bit#4 is High, so the PROM signal appears as the Timing and sync Signal Output. MAP OF THE PROM DATA BITS TO MTG CHANNEL NUMBER ------------------------------------------------------- MTG TIMING AND SYNC CHANNEL NUMBER --------------------------------------------------------------------- 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 --------------- --------------- --------------- --------------- PROM #1 BIT # PROM #2 BIT # PROM #3 BIT # PROM #4 BIT # MASTER TIMING GENERATOR BOARD CONNECTORS AND SWITCHES ----------------------------------------------------------- Rear of the Card ------------------------------ | |. J1 | |. J2 | | | --------- ------- | | | | | | MTG | | CARD | | | | | | | | | | ------ ------ ----- | | | J4.| | J5.| |J6.| | ------------------------------ Front of the Card CONNECTOR J1 THE TIMING AND SYNCHRONIZATION SIGNAL OUTPUTS ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 NOT USED . . . . . . 66 NOT USED 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown Timing & Sync. Signal Bit#1 Non-inverted IN 1 NTS1 76 tan Timing & Sync. Signal Bit#1 inverted IN 2 ITS1 77 red Timing & Sync. Signal Bit#2 Non-inverted IN 3 NTS2 78 tan Timing & Sync. Signal Bit#2 inverted IN 4 ITS2 79 orange Timing & Sync. Signal Bit#3 Non-inverted IN 5 NTS3 80 tan Timing & Sync. Signal Bit#3 inverted IN 6 ITS3 81 yellow Timing & Sync. Signal Bit#4 Non-inverted IN 7 NTS4 82 tan Timing & Sync. Signal Bit#4 inverted IN 8 ITS4 83 green Timing & Sync. Signal Bit#5 Non-inverted IN 9 NTS5 84 tan Timing & Sync. Signal Bit#5 inverted IN 10 ITS5 85 blue Timing & Sync. Signal Bit#6 Non-inverted IN 11 NTS6 86 tan Timing & Sync. Signal Bit#6 inverted IN 12 ITS6 87 violet Timing & Sync. Signal Bit#7 Non-inverted IN 13 NTS7 88 tan Timing & Sync. Signal Bit#7 inverted IN 14 ITS7 89 grey Timing & Sync. Signal Bit#8 Non-inverted IN 15 NTS8 90 tan Timing & Sync. Signal Bit#8 inverted IN 16 ITS8 91 white Timing & Sync. Signal Bit#9 Non-inverted IN 17 NTS9 92 tan Timing & Sync. Signal Bit#9 inverted IN 18 ITS9 93 black Timing & Sync. Signal Bit#10 Non-inverted IN 19 NTS10 94 tan Timing & Sync. Signal Bit#10 inverted IN 20 ITS10 95 brown Timing & Sync. Signal Bit#11 Non-inverted IN 21 NTS11 96 tan Timing & Sync. Signal Bit#11 inverted IN 22 ITS11 97 red Timing & Sync. Signal Bit#12 Non-inverted IN 23 NTS12 98 tan Timing & Sync. Signal Bit#12 inverted IN 24 ITS12 99 orange Timing & Sync. Signal Bit#13 Non-inverted IN 25 NTS13 100 tan Timing & Sync. Signal Bit#13 inverted IN 26 ITS13 101 yellow Timing & Sync. Signal Bit#14 Non-inverted IN 27 NTS14 102 tan Timing & Sync. Signal Bit#14 inverted IN 28 ITS14 103 green Timing & Sync. Signal Bit#15 Non-inverted IN 29 NTS15 104 tan Timing & Sync. Signal Bit#15 inverted IN 30 ITS15 105 blue Timing & Sync. Signal Bit#16 Non-inverted IN 31 NTS16 106 tan Timing & Sync. Signal Bit#16 inverted IN 32 ITS16 107 violet Timing & Sync. Signal Bit#17 Non-inverted IN 33 NTS17 108 tan Timing & Sync. Signal Bit#17 inverted IN 34 ITS17 109 grey Timing & Sync. Signal Bit#18 Non-inverted IN 35 NTS18 110 tan Timing & Sync. Signal Bit#18 inverted IN 36 ITS18 111 white Timing & Sync. Signal Bit#19 Non-inverted IN 37 NTS19 112 tan Timing & Sync. Signal Bit#19 inverted IN 38 ITS19 113 black Timing & Sync. Signal Bit#20 Non-inverted IN 39 NTS20 114 tan Timing & Sync. Signal Bit#20 inverted IN 40 ITS20 115 brown Timing & Sync. Signal Bit#21 Non-inverted IN 41 NTS21 116 tan Timing & Sync. Signal Bit#21 inverted IN 42 ITS21 117 red Timing & Sync. Signal Bit#22 Non-inverted IN 43 NTS22 118 tan Timing & Sync. Signal Bit#22 inverted IN 44 ITS22 119 orange Timing & Sync. Signal Bit#23 Non-inverted IN 45 NTS23 120 tan Timing & Sync. Signal Bit#23 inverted IN 46 ITS23 121 yellow Timing & Sync. Signal Bit#24 Non-inverted IN 47 NTS24 122 tan Timing & Sync. Signal Bit#24 inverted IN 48 ITS24 123 green Timing & Sync. Signal Bit#25 Non-inverted IN 49 NTS25 124 tan Timing & Sync. Signal Bit#25 inverted IN 50 ITS25 125 blue Timing & Sync. Signal Bit#26 Non-inverted IN 51 NTS26 126 tan Timing & Sync. Signal Bit#26 inverted IN 52 ITS26 127 violet Timing & Sync. Signal Bit#27 Non-inverted IN 53 NTS27 128 tan Timing & Sync. Signal Bit#27 inverted IN 54 ITS27 129 grey Timing & Sync. Signal Bit#28 Non-inverted IN 55 NTS28 130 tan Timing & Sync. Signal Bit#28 inverted IN 56 ITS28 131 white Timing & Sync. Signal Bit#29 Non-inverted IN 57 NTS29 132 tan Timing & Sync. Signal Bit#29 inverted IN 58 ITS29 133 black Timing & Sync. Signal Bit#30 Non-inverted IN 59 NTS30 134 tan Timing & Sync. Signal Bit#30 inverted IN 60 ITS30 135 brown Timing & Sync. Signal Bit#31 Non-inverted IN 61 NTS31 136 tan Timing & Sync. Signal Bit#31 inverted IN 62 ITS31 137 red Timing & Sync. Signal Bit#32 Non-inverted IN 63 NTS32 138 tan Timing & Sync. Signal Bit#32 inverted IN 64 ITS32 139 Ground GND 140 Ground GND CONNECTOR J2 THE SPECIFIC BACKPLANE BUS CONNECTOR ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown NO Connection on the MTG Rev. B Card 1 76 tan NO Connection on the MTG Rev. B Card 2 77 red NO Connection on the MTG Rev. B Card 3 78 tan NO Connection on the MTG Rev. B Card 4 79 orange NO Connection on the MTG Rev. B Card 5 80 tan NO Connection on the MTG Rev. B Card 6 81 yellow NO Connection on the MTG Rev. B Card 7 82 tan NO Connection on the MTG Rev. B Card 8 83 green NO Connection on the MTG Rev. B Card 9 84 tan NO Connection on the MTG Rev. B Card 10 85 blue NO Connection on the MTG Rev. B Card 11 86 tan NO Connection on the MTG Rev. B Card 12 87 violet NO Connection on the MTG Rev. B Card 13 88 tan NO Connection on the MTG Rev. B Card 14 89 grey NO Connection on the MTG Rev. B Card 15 90 tan NO Connection on the MTG Rev. B Card 16 91 white Card Address Bit#1 Non-inverted IN 17 NAC1 92 tan Card Address Bit#1 Inverted IN 18 IAC1 93 black Card Address Bit#2 Non-inverted IN 19 NAC2 94 tan Card Address Bit#2 Inverted IN 20 IAC2 95 brown Card Address Bit#3 Non-inverted IN 21 NAC3 96 tan Card Address Bit#3 Inverted IN 22 IAC3 97 red Card Address Bit#4 Non-inverted IN 23 NAC4 98 tan Card Address Bit#4 Inverted IN 24 IAC4 99 orange Card Address Bit#5 Non-inverted IN 25 NAC5 100 tan Card Address Bit#5 Inverted IN 26 IAC5 101 yellow Card Address Bit#6 Non-inverted IN 27 NAC6 102 tan Card Address Bit#6 Inverted IN 28 IAC6 103 green Function Address Bit#1 Non-inverted IN 29 NAF1 104 tan Function Address Bit#1 Inverted IN 30 IAF1 105 blue Function Address Bit#2 Non-inverted IN 31 NAF2 106 tan Function Address Bit#2 Inverted IN 32 IAF2 107 violet Function Address Bit#3 Non-inverted IN 33 NAF3 108 tan Function Address Bit#3 Inverted IN 34 IAF3 109 grey Function Address Bit#4 Non-inverted IN 35 NAF4 110 tan Function Address Bit#4 Inverted IN 36 IAF4 111 white Function Address Bit#5 Non-inverted IN 37 NAF5 112 tan Function Address Bit#5 Inverted IN 38 IAF5 113 black Function Address Bit#6 Non-inverted IN 39 NAF6 114 tan Function Address Bit#6 Inverted IN 40 IAF6 115 brown Function Address Bit#7 Non-inverted IN 41 NAF7 116 tan Function Address Bit#7 Inverted IN 42 IAF7 117 red Function Address Bit#8 Non-inverted IN 43 NAF8 118 tan Function Address Bit#8 Inverted IN 44 IAF8 119 orange Strobe Non-inverted IN 45 NSTB 120 tan Strobe Inverted IN 46 ISTB 121 yellow Direction Non-inverted IN 47 NDIR 122 tan Direction Inverted IN 48 IDIR 123 green Bidirectional Data Bit#1 Non-inverted IN 49 NDB1 124 tan Bidirectional Data Bit#1 Inverted IN 50 IDB1 125 blue Bidirectional Data Bit#2 Non-inverted IN 51 NDB2 126 tan Bidirectional Data Bit#2 Inverted IN 52 IDB2 127 violet Bidirectional Data Bit#3 Non-inverted IN 53 NDB3 128 tan Bidirectional Data Bit#3 Inverted IN 54 IDB3 129 grey Bidirectional Data Bit#4 Non-inverted IN 55 NDB4 130 tan Bidirectional Data Bit#4 Inverted IN 56 IDB4 131 white Bidirectional Data Bit#5 Non-inverted IN 57 NDB5 132 tan Bidirectional Data Bit#5 Inverted IN 58 IDB5 133 black Bidirectional Data Bit#6 Non-inverted IN 59 NDB6 134 tan Bidirectional Data Bit#6 Inverted IN 60 IDB6 135 brown Bidirectional Data Bit#7 Non-inverted IN 61 NDB7 136 tan Bidirectional Data Bit#7 Inverted IN 62 IDB7 137 red Bidirectional Data Bit#8 Non-inverted IN 63 NDB8 138 tan Bidirectional Data Bit#8 Inverted IN 64 IDB8 139 Ground GND 140 Ground GND CONNECTOR J4 EXTERNAL ENABLE 1 - 16 AND EXTERNAL BIT 1 - 16 ------------- INPUT CONNECTOR ------------------------------------------------------------------------------ CONNECTOR J4 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 External Enable # 16 Non-Inverted NEXEN16 2 External Enable # 16 Inverted IEXEN16 3 External Bit # 16 Non-Inverted NEXBT16 4 External Bit # 16 Inverted IEXBT16 5 External Bit # 15 Non-Inverted NEXBT15 6 External Bit # 15 Inverted IEXBT15 7 External Enable # 15 Non-Inverted NEXEN15 8 External Enable # 15 Inverted IEXEN15 9 External Enable # 14 Non-Inverted NEXEN14 10 External Enable # 14 Inverted IEXEN14 11 External Bit # 14 Non-Inverted NEXBT14 12 External Bit # 14 Inverted IEXBT14 13 External Bit # 13 Non-Inverted NEXBT13 14 External Bit # 13 Inverted IEXBT13 15 External Enable # 13 Non-Inverted NEXEN13 16 External Enable # 13 Inverted IEXEN13 17 External Enable # 12 Non-Inverted NEXEN12 18 External Enable # 12 Inverted IEXEN12 19 External Bit # 12 Non-Inverted NEXBT12 20 External Bit # 12 Inverted IEXBT12 21 External Bit # 11 Non-Inverted NEXBT11 22 External Bit # 11 Inverted IEXBT11 23 External Enable # 11 Non-Inverted NEXEN11 24 External Enable # 11 Inverted IEXEN11 25 External Enable # 10 Non-Inverted NEXEN10 26 External Enable # 10 Inverted IEXEN10 27 External Bit # 10 Non-Inverted NEXBT10 28 External Bit # 10 Inverted IEXBT10 29 External Bit # 9 Non-Inverted NEXBT9 30 External Bit # 9 Inverted IEXBT9 31 External Enable # 9 Non-Inverted NEXEN9 32 External Enable # 9 Inverted IEXEN9 33 External Enable # 8 Non-Inverted NEXEN8 34 External Enable # 8 Inverted IEXEN8 35 External Bit # 8 Non-Inverted NEXBT8 36 External Bit # 8 Inverted IEXBT8 37 External Bit # 7 Non-Inverted NEXBT7 38 External Bit # 7 Inverted IEXBT7 39 External Enable # 7 Non-Inverted NEXEN7 40 External Enable # 7 Inverted IEXEN7 41 External Enable # 6 Non-Inverted NEXEN6 42 External Enable # 6 Inverted IEXEN6 43 External Bit # 6 Non-Inverted NEXBT6 44 External Bit # 6 Inverted IEXBT6 45 External Bit # 5 Non-Inverted NEXBT5 46 External Bit # 5 Inverted IEXBT5 47 External Enable # 5 Non-Inverted NEXEN5 48 External Enable # 5 Inverted IEXEN5 49 External Enable # 4 Non-Inverted NEXEN4 50 External Enable # 4 Inverted IEXEN4 51 External Bit # 4 Non-Inverted NEXBT4 52 External Bit # 4 Inverted IEXBT4 53 External Bit # 3 Non-Inverted NEXBT3 54 External Bit # 3 Inverted IEXBT3 55 External Enable # 3 Non-Inverted NEXEN3 56 External Enable # 3 Inverted IEXEN3 57 External Enable # 2 Non-Inverted NEXEN2 58 External Enable # 2 Inverted IEXEN2 59 External Bit # 2 Non-Inverted NEXBT2 60 External Bit # 2 Inverted IEXBT2 61 External Bit # 1 Non-Inverted NEXBT1 62 External Bit # 1 Inverted IEXBT1 63 External Enable # 1 Non-Inverted NEXEN1 64 External Enable # 1 Inverted IEXEN1 CONNECTOR J5 EXTERNAL ENABLE 17 - 32 AND EXTERNAL BIT 17 - 32 ------------- INPUT CONNECTOR ------------------------------------------------------------------------------ CONNECTOR J5 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 External Enable # 32 Non-Inverted NEXEN32 2 External Enable # 32 Inverted IEXEN32 3 External Bit # 32 Non-Inverted NEXBT32 4 External Bit # 32 Inverted IEXBT32 5 External Bit # 31 Non-Inverted NEXBT31 6 External Bit # 31 Inverted IEXBT31 7 External Enable # 31 Non-Inverted NEXEN31 8 External Enable # 31 Inverted IEXEN31 9 External Enable # 30 Non-Inverted NEXEN30 10 External Enable # 30 Inverted IEXEN30 11 External Bit # 30 Non-Inverted NEXBT30 12 External Bit # 30 Inverted IEXBT30 13 External Bit # 29 Non-Inverted NEXBT29 14 External Bit # 29 Inverted IEXBT29 15 External Enable # 29 Non-Inverted NEXEN29 16 External Enable # 29 Inverted IEXEN29 17 External Enable # 28 Non-Inverted NEXEN28 18 External Enable # 28 Inverted IEXEN28 19 External Bit # 28 Non-Inverted NEXBT28 20 External Bit # 28 Inverted IEXBT28 21 External Bit # 27 Non-Inverted NEXBT27 22 External Bit # 27 Inverted IEXBT27 23 External Enable # 27 Non-Inverted NEXEN27 24 External Enable # 27 Inverted IEXEN27 25 External Enable # 26 Non-Inverted NEXEN26 26 External Enable # 26 Inverted IEXEN26 27 External Bit # 26 Non-Inverted NEXBT26 28 External Bit # 26 Inverted IEXBT26 29 External Bit # 25 Non-Inverted NEXBT25 30 External Bit # 25 Inverted IEXBT25 31 External Enable # 25 Non-Inverted NEXEN25 32 External Enable # 25 Inverted IEXEN25 33 External Enable # 24 Non-Inverted NEXEN24 34 External Enable # 24 Inverted IEXEN24 35 External Bit # 24 Non-Inverted NEXBT24 36 External Bit # 24 Inverted IEXBT24 37 External Bit # 23 Non-Inverted NEXBT23 38 External Bit # 23 Inverted IEXBT23 39 External Enable # 23 Non-Inverted NEXEN23 40 External Enable # 23 Inverted IEXEN23 41 External Enable # 22 Non-Inverted NEXEN22 42 External Enable # 22 Inverted IEXEN22 43 External Bit # 22 Non-Inverted NEXBT22 44 External Bit # 22 Inverted IEXBT22 45 External Bit # 21 Non-Inverted NEXBT21 46 External Bit # 21 Inverted IEXBT21 47 External Enable # 21 Non-Inverted NEXEN21 48 External Enable # 21 Inverted IEXEN21 49 External Enable # 20 Non-Inverted NEXEN20 50 External Enable # 20 Inverted IEXEN20 51 External Bit # 20 Non-Inverted NEXBT20 52 External Bit # 20 Inverted IEXBT20 53 External Bit # 19 Non-Inverted NEXBT19 54 External Bit # 19 Inverted IEXBT19 55 External Enable # 19 Non-Inverted NEXEN19 56 External Enable # 19 Inverted IEXEN19 57 External Enable # 18 Non-Inverted NEXEN18 58 External Enable # 18 Inverted IEXEN18 59 External Bit # 18 Non-Inverted NEXBT18 60 External Bit # 18 Inverted IEXBT18 61 External Bit # 17 Non-Inverted NEXBT17 62 External Bit # 17 Inverted IEXBT17 63 External Enable # 17 Non-Inverted NEXEN17 64 External Enable # 17 Inverted IEXEN17 ACCELERATOR CLOCK INPUT, BEAM CROSSING PULSE INPUT, CONNECTOR J6 PROM ADDRESS COUNTER RESET INPUT, PROM ADDRESS COUNTER ------------- CLOCK ENABLE INPUT, AND MONITOR OUTPUTS ------------------------------------------------------------------------------ CONNECTOR J6 PIN NUMBER FUNCTION MNEMONIC ------------------------------------------------------------------------------ 1 On Board Oscillator Monitor Non-Inverted NOBXO 2 On Board Oscillator Monitor Inverted IOBXO 3 PROM Counter Clock Monitor Non-Inverted NPACC 4 PROM Counter Clock Monitor Inverted IPACC 5 PROM Counter Reset Monitor Non-Inverted NPACR 6 PROM Counter Reset Monitor Inverted IPACR 7 PROM Counter Clock enable Non-Inverted NPACE 8 PROM Counter Clock enable Inverted IPACE 9 Ground GND 10 Ground GND 11 Beam Crossing Pulse Input Non-Inverted NBCPI 12 Beam Crossing Pulse Input Inverted IBCPI 13 Ground GND 14 Ground GND 15 Accelerator Clock Input Non-Inverted NACCI 16 Accelerator Clock Input Inverted IACCI CARDS ADDRESS SELECTOR SWITCH Switch U53 controls the Card Address at which this card will wake up. When a switch is CLOSED the corresponding bit in the Card Address is a 0 and when a switch is OPEN then the corresponding bit is a 1. ADDRESS SWITCH SECTION CARD ADDRESS BIT BIT VALUE ---------------- ------------------ ----------- 1 6 32 2 5 16 3 4 8 4 3 4 5 2 2 6 1 1 7 MUST BE CLOSED x 8 MUST BE CLOSED x BOARD ORDERS HISTORY: 20 boards ordered 8-FEB-1990, assembled summer1990 ETCH REVISION HISTORY: REVISION B FEB 1990 POWER REQUIREMENTS: VCC +5.0 Volts at 9.1 Amps VEE -5.2 Volts at 3.3 Amps ECO HISTORY: At this time (8-AUG-1990) there is one Required ECO for the MTG Rev. B cards. There is a mistake in the Ground Plane layer and no ground connections were made to pins #1 and #16 of U116 the 10H101 that drives the three differential ECL monitor signals off the card. These three signals are for monitoring the on board oscillator, the PROM Address Counter Clock, and the PROM Address Counter Reset signal. Connections to the Ground Plane are available from the bypass capacitors at each end of U116. The lead of the capacitor nearer the front of the board is the ground connection. To repair this problem connect a wire wrap wire, on the solder side of the board, to the ground lead of the bypass capacitor near the pin #8 - #9 end of U116. Solder this wire to pin #16 and then to pin #1 of U116 and finally connect this wire to the ground lead of the bypass capacitor at the pin #1 - #16 end of U116. This wire should be kept short and direct. It needs to be insulated where it passes under U116. If necessary glue it in place. ECO for use with Level 1.5: --------------------------- For use with Level 1.5 in several applications (e.g. Hold Transfer Control MTG, Start Digitize Control MTG, Level 1.5 Term Receiving MTG, and Level 1.5 Veto/Confirm MTG), an extra global signal must be given to each MTG channel. The ECO to do this is described below. An external reset signal that reaches the 32 pals on the MTG card is needed. This problem has an easy solution with the only added hardware being a 74LS541 octal buffer that fits into the spare dip J3. The external reset signal is brought in on connector J6 pins 7 and 8. This originally was the 'counter clock enable input', but has been determined to be useless. The destination of the 'counter clock enable input' is then cut. This neededs no further modification because this signal is routed to an enable on U117 that is active low and has an internal pull-down resistor. The external reset signal is then brought, after passing through its receiver, to a spare ECL/TTL converter U82. This signal is pulled-down near U82 i.e. at the end of its run. The external reset signal is then brought up to a 74LS541 that sits in the spare dip J3. The spare dip J3 has TTL power hard wired. This is good in this case since a TTL chip needs to be there. The external reset signal is then wired to four of the eight buffers in the 74LS541. Now the external reset signal is fanned out to the 32 pals in groups of 8. This again was not hard because the CBUS data bit 6 was borrowed to do the job. The 74ALS541 chip must be enabled. This is done by tying its two active-low enable inputs to GROUND. The CBUS data bit 6 is already wired up in groups of 8 to the pals that are needed to receive the external reset signal. Specifically to install the L1.5 ECO do the following: 1. Cut trace on solder side between U117 pin 14 and R34 pin 3. 2. Cut Trace on component side between U117 pin 14 and U115 pin 14. 3. Solder a wire-wrap wire on the solder side to U115 pin 14 bring this wire to U82 pin 11. Solder this wire and another wire-wrap wire to U82 pin 11. 4. The other wire from above is then soldered to R27 pin 2. 5. Place a 20 pin IC into spare dip J3. Solder Pins 10 and 20. 6. Rip up trace on solder side from U68 pin 13 to via. 7. Rip up trace on solder side from U69 pin 13 to via. 8. Rip up trace on solder side from U70 pin 13 to via. 9. Rip up trace on solder side from U71 pin 13 to via. 10. Solder wire-wrap wire into pin 18 of spare dip J3 bring this wire to via near U68 that used to be attached to pin 13 of U68 and solder. 11. Solder wire-wrap wire into pin 17 of spare dip J3 bring this wire to via near U69 that used to be attached to pin 13 of U69 and solder. 12. Solder wire-wrap wire into pin 16 of spare dip J3 bring this wire to via near U70 that used to be attached to pin 13 of U70 and solder. 13. Solder wire-wrap wire into pin 15 of spare dip J3 bring this wire to via near U71 that used to be attached to pin 13 of U71 and solder. 14. Solder a wire-wrap wire to U82 pin 12, Bring this wire to spare dip J3 and solder to pins 2, 3, 4, and 5. 15. Solder a wire-wrap wire to pins 1, 19, and 10 of the spare dip J3. 16. Solder the rest of the pins on the spare dip J3. PROM Address Line Signal Reflection ECO 1-NOV-1995 ------------------------------------------------------ In the summer of 1994 and again in the fall of 1995 erratic PROM Address counting was observed on two MTG cards (SN# 22 and SN# 24). One would typically see errors in the MTG output channels at a rate of something like one in 30k accelerator turns. After some initial poking around the real cause of this problem was traced to the quality of the TTL signals on the PROM Address lines. Very bad reflections were noticed on the high to low transitions on some of the PROM Adrs lines and the PROM Clock line. These lines are driven by 10H125 ECL to TTL converters and the high to low transition edge speed is in the 1 to 2 nsec range. The "under shoot" followed by positive reflection appears worst when multiple signals passing through a given 10H125 all make the high to low transition simultaniously. The typical reflection looked something like a 3 Volt peak undershoot centered at about 5 nsec after the beginning of the high to low tansition. This was followed by a +3 Volt reflection centered at about 12 nsec after the start of the high to low transition. This was followed by a 2 Volt undershoot centered at about 17 nsec after the beginning of the high to low transition. Things then appear to settle down. This was measured at the "far" end of the PROM Adrs line. It did not appear practical to RC shunt terminate the end of these lines because: All of these lines have long stubs (stub length about 1/3 line length). Some of these lines are driven near their middle. So series termination at the driving end was tried. Values of 22, 33, and 47 Ohms were tried with 47 Ohms appearing to give the best results. The traces from the 10H125 drives that run up to the horizontal distribution traces were removed and the connection from the drive chips to the horizontal distribution traces was made with a 47 Ohm 1/8 Watt carbon composition resistor. These resistors were added to the following signals: Signal Driven IC and Pin Number -------- -------------------------- Adrs 1 U80 pin 4 Adrs 2 U80 pin 13 Adrs 3 U80 pin 12 Adrs 4 U80 pin 5 Adrs 5 U81 pin 4 Adrs 6 U81 pin 13 Adrs 7 U81 pin 12 Adrs 8 U81 pin 5 Adrs 9 U80 pin 4 Adrs 10 U80 pin 13 Clock U80 pin 5 The resistors were installed on the component side of the card. One side of each resistor was soldered to the via in the horizontal distribution trace and the other side was soldered directly to the IC pin. The rather large value of 47 Ohms does not cause any DC trouble because the only loads are 4 CMOS CY7C245A chips at 10 uamp each and one 74ALS541 at 100 uamp. So the DC shift is only about 5 mVolts. With the resistors installed on all 11 lines there are no significant reflections visible at either the driving end or the far end of the lines. The scope measurements of these lines now show the following: PROM PROM PROM PROM PROM PROM Parameter A1 A4 A5 A8 A9 A10 --------------- ------ ------ ------ ------ ------ ------ Rise Time 2-3 2-3 2 2 2 3 Fall Time 2-3 3 3 3 3 2 / Clock Up Edge 4 4 4 4 4 3 H | before A% Falls O | L | Clock Up Edge 2 3 3 3 4 4 D \ before A% Rises S / A% Low before 34 33 33 33 32 33 E | Clock Up Edge T | U | A% High before 34 34 34 34 34 34 P \ Clock Up Edge Clock Rise Time 3 Clock Fall Time 3 Notes: The rise and fall times are measured from 0.8 Volts to 2.5 Volts. The setup and hold times are measured at 1.5 Volts. By far the worst setup time occurs when A9 falls, i.e. the 511 to 512 carry. On this transition the A9 line "stalls" out right at or just barely below 0.8 Volts. It holds there for perhaps 4 nsec which leaves 28 nsec between; A9 "clearly below" 0.8 V and PROM clock going above 1.5 Volts. All measurements were made on MTG SN# 24 using a Tek 475 scope. End of ECO's ------------------------------------------------------------------------------ TIMING CONSIDERATIONS IN RESETING THE MTG PROM ADDRESS ------------------------------------------------------ PROM ADDRESS COUNTER CLOCK AND ADDRESS PATH 1. Received by a 10H115 RECEIVER (1.7 nS max Tpd) 2. Passed through a 10H174 MUX (2.9 nS max Tpd) Delivered to 10H016 PROM Address Counter Delivered to CY7C245A PROM Clock 3. Clocking bank of 10H016 COUNTERS (3.5 nS CP->Q max) 4. Count converted to TTL by 10H125 (3.6 nS max Tpd) 5. Delivered to CY7C245A Address inputs PROM ADDRESS COUNTER RESET SIGNAL PATH 1. Received by a 10H115 (1.7 nS max Tpd) 2. NAND'ed with enable by 10H104 (2.2 nS max Tpd) 3. AND'ed with TCRESET by 10H104 (2.2 nS max Tpd) 4. Delivered to the PROM Address Counter What we want is a PROM Address Counter Reset signal that goes LOW before the positive Clock edge that should take the output of the counter to zero. This reset signal must be LOW by at least a setup time before this clock edge and must be high again at least a setup time before the positive clock edge that takes the output of the Rom Address Counter from zero to one.