********************************** * SINGLE BUFFERED SCALER CARD * ********************************** 8-JAN-1988 14:14 MODIFIED: 3-MAY-88 D.E. ADD THE SECTION ABOUT THE CONTROL SIGNAL LOGIC 17-MAY-88 S.G. ADD THE SECTION ABOUT MODIFICATIONS TO REV. A 10-AUG-88 D.E. CORRECT THE PIN OUT NUMBERING ON J1 GATE SIGNALS 5-AUG-89 D.E. FIX THE 540-541 QUESTION AND EXPLAIN THE LED'S. 18-NOV-89 D.E. Explain the pin out of the External Gate Signal inputs, and the Common Clock signal input. 22-APR-91 P.L. Add appendix table of scaler number vs trigger number and veto type 5-JUN-92 S.G. Add the "2 Clock" ECO for the Level 1.5 Timeout/DeadX and Level 1.5 Cycle/Skip SBSC's. BOARD DESCRIPTION ------------------ The Single Buffered Scaler Card , SBSC, provides 32 channel of 32 bits scalers per card. Each channel has a gate input(Gate #) which can be control by computer or external electrical control. All 32 channels on a SBSC board has a common clock input (CLK). By this arrangement user has two options to control the scalers. He can enable the specific gate(both by CBus or EX signal) for certain scaler to set the scaler counting the CLK signal, or use the CLK signal to enable the scaler to set scaler counting the gate signal. The scalers can be individually reseted from the computer over the C BUS. Each one of the 32 scalers consists of an integrated circuit 32 bit counter LS7060. The SCBC also has a "card address comparator",a "function address decoder" , a "Bi-direction data bus tranceiver" and "read-back latches" for reading back the control data. The 32 counters link in a cascade series. The output data is a 8 bits 8x4 data bus tree . All signal inputs of scalers are differential ECL signals. They are terminated on the SBSC card with a 110 ohm resistor. There are 32 LED to display the 32 gate status, one LED to display the CLK status, and one LED to display the board "wake up" (meaning that the card address is correct). THE PROGRAMING ------------------ There are 4 3-bits decoders to preform the "function address decoder". The 3 LS bits of function address are link to two decoders which are enabled by condition that the rest bits are 0. One of these decoders is also enabled by "read" signal. The output of this decoder is used to select control signal to be read back. Another decoder is enabled by "write" signal. The output of this one is used to control the "reset counter" and "Gate" signal for individual scaler. The 3MS bits go through two other decoders, while are enabled by the condition that the rest bits are 0. One of those decoder is enabled by "write" signal have two wires output be used, their conrespond function address are 32 and 64, these are used to control the "increment scan counter" and "reset scan counter/load" signals. (The board has option to send the glob "reset scan/load" signal a SBSC board by a external electrical control single.) Another decoder is enabled by "read" single which has one output wire be used, Their conrespond function address is 32. It is used to enable "read" all the data from the 32 dcaded scalers. The Function Address: ****************************************************************************** scaler function address 1-4 0 5-8 1 9-12 2 13-16 3 17-20 4 21-24 5 25-28 6 28-32 7 ===================================================== reset scan counter and load latch : 64 increment scan counter : 32 read data : 32 ===================================================== ************************************************************************** The control data: *************************************************************************** enable gate# reset scaler# data (0 = enable) (0 = reset) (bit #) 1,5,9,13,17,21,25,29 0 1,5,9,13,17,21,25,29 1 2,6,10,14,18,22,26,30 2 2,6,10,14,18,22,26,30 3 3,7,11,15,19,23,27,31 4 3,7,11,15,19,23,27,31 5 4,8,12,16,20,24,28,32 6 4,8,12,16,20,24,28,32 7 *************************************************************************** The control routine of reading data likes : write FUNC = 64 ! reset scan counter/load do i=1,128 read FUNC = 32 ! read data store data write FUNC = 32 ! ncreament scan counter end do write FUNC = 0 , DATA = 1 ! reset scaler # 1 read FUNC = 0 , DATA = 0 ! read the control data . . . ---------------------- CONTROL SIGNAL LOGIC ---------------------- 1. THE SCAN COUNTER RESET AND LATCH LOAD The Scan Counter can be reset and the Latches loaded either under software or hardware control. To do this via software requires only writing to Function Address 64. You may use any data during this write operation, but all zero is preferred. To do this via hardware requires setting the Timing & Sync Signal E to the HIGH state and then back to the LOW state. The default state of TSS E must be LOW. If nothing is connected to TSS E then it will default to LOW. 2. THE SCALER CLOCK SIGNAL (COMMON CLOCK) The Clock signal that is common to all 32 Scalers arrives on Timing and Sync Signal D. This TSS is received on the card by a normal Differential Line Receiver and fanned out to the Count Input (pin 1) of each of the 32 scalers. If nothing is connected to this TSS then its default state will be LOW. If this TSS is HIGH then it will inhibit all 32 scalers from counting. If this TSS is being used to increment the scalers (i.e. one of the two methods has been used to enable the scaler Gate) then the scalers will increment on the falling (negative) edge of this signal. The scaler will also increment, if this TSS signal is Low and a Gate enable makes a High to Low transition. Note: On some special SBSC's (e.g. the AND-OR Fired SBSC and the Start Digitization counter SBSC) the Common Clock signal does not arrive on T&SS Signal D, J2 pins 81 and 82, but rather on a part of J2 that is not part of the C-Bus, J2 pins 3 and 4. 3. EXTERNAL GATE SIGNALS AND THE "SCALER GATES" The "Scaler Gates" can be controlled either from software or from hardware via the Individual External Gate Signals. The hardware signals for controlling the 32 scaler gates are received by Inverting Differential Line Receivers and then sent to one input of a NOR gate. The other input to each NOR gate is an Enable Bit from the Scaler Control Register (Function Address 0 through 7). Thus when either the Control Register Enable Bit is HIGH or the External Gate Signal is LOW then the NOR Gate will send a LOW signal to the scaler and the scaler will be enabled to count. The default state of the External Gate Signal (the state with nothing connected) measured at its input to the NOR gate is LOW and thus with no hardware signal connected the software Control Register Enable Bit can control the "scaler gate". If an External Gate signal is going to be used to control a scaler gate then the Control Register Enable Bit should be set to zero and the scaler will be enabled when the External Gate signal is LOW and inhibited when the External Gate Signal is HIGH. Note that the "Scaler Gate" can also be used to increment the scaler. To do this the External Scaler Common Clock must be LOW and then the scaler will increment on either the falling edge of the External Gate Signal or on the one to zero transition of the Control Register Enable Bit. Note that the input circuit for the External Gate Signals is correct for direct connection to the FSTD "Disable Scaler" outputs. I.E. when the FSTD is disable for some reason then some FSTD Disable Scaler output will be LOW. When this is received by the inverting differential line receiver on the SBSC this will result in an HIGH signal to the input of the NOR gate and thus a LOW output from the NOR gate which enables the scaler to increment. The normal "non-disabled" state for the FSTD Disable Scaler output signals is HIGH. Note that when the cards are using 74ALS541 chips for the gate display LED drivers then when an LED is "on" it implies that that scaler will increment with the common clock. Note that the pinout of the input connector for the External Gate Signals is backwards from the standard convention for using twist and flat differential cable. What is conventionally labeled signal pair number 1 on the cable connected to the External Gate Signal input goes to scaler number 32. What is conventionally labeled signal pair number 32 on the cable is connected to the gate for scaler number 1. 4. REQUIRED BUS WRITE CYCLE When writing to the control registers of this card, the exact nature of the bus cycle is important. To ensure correct operation of the 74ALS990 read-back latches on this card, the duration of the STROBE signal must be 'nested' in the duration of the DIRECTION signal. If the STROBE signal and the DIRECTION signal change states simultaneously, it is possible to force a bus conflict situation during which the 74ALS990's latch false data. CONNECTION --------------- SINGLE BUFFER SCALER CARD CONNECTORS ------------------------------------------------- CONNECTOR J1 --------------- ------------------------------------------------------------------------------ PIN COLOR FUNCTION PLUG & # ON CABLE WIRE # MNEMONIC ON CABLE ------------------------------------------------------------------------------ 1 GROUND GND 2 GROUND GND 3 NOT USED 4 NOT USED 5 NOT USED . . . . . . 66 NOT USED 67 GROUND GND 68 GROUND GND 69 POWER +5.0V VCC 70 POWER +5.0V VCC 71 POWER -5.2V VEE 72 POWER -5.2V VEE 73 GROUND GND 74 GROUND GND 75 BROWN SCALER NUM.32 GATE CONTROL NON-INVERTED IN 1 NGT32 76 TAN SCALER NUM.32 GATE CONTROL INVERTED IN 2 IGT32 77 RED SCALER NUM.31 GATE CONTROL NON-INVERTED IN 3 NGT31 78 TAN SCALER NUM.31 GATE CONTROL INVERTED IN 4 IGT31 79 ORANGE SCALER NUM.30 GATE CONTROL NON-INVERTED IN 5 NGT30 80 TAN SCALER NUM.30 GATE CONTROL INVERTED IN 6 IGT30 81 YELLOW SCALER NUM.29 GATE CONTROL NON-INVERTED IN 7 NGT29 82 TAN SCALER NUM.29 GATE CONTROL INVERTED IN 8 IGT29 83 GREEN SCALER NUM.28 GATE CONTROL NON-INVERTED IN 9 NGT28 84 TAN SCALER NUM.28 GATE CONTROL INVERTED IN 10 IGT28 85 BLUE SCALER NUM.27 GATE CONTROL NON-INVERTED IN 11 NGT27 86 TAN SCALER NUM.27 GATE CONTROL INVERTED IN 12 IGT27 87 VIOLET SCALER NUM.26 GATE CONTROL NON-INVERTED IN 13 NGT26 88 TAN SCALER NUM.26 GATE CONTROL INVERTED IN 14 IGT26 89 GREY SCALER NUM.25 GATE CONTROL NON-INVERTED IN 15 NGT25 90 TAN SCALER NUM.25 GATE CONTROL INVERTED IN 16 IGT25 91 WHITE SCALER NUM.24 GATE CONTROL NON-INVERTED IN 17 NGT24 92 TAN SCALER NUM.24 GATE CONTROL INVERTED IN 18 IGT24 93 BLACK SCALER NUM.23 GATE CONTROL NON-INVERTED IN 19 NGT23 94 TAN SCALER NUM.23 GATE CONTROL INVERTED IN 20 IGT23 95 BROWN SCALER NUM.22 GATE CONTROL NON-INVERTED IN 21 NGT22 96 TAN SCALER NUM.22 GATE CONTROL INVERTED IN 22 IGT22 97 RED SCALER NUM.21 GATE CONTROL NON-INVERTED IN 23 NGT21 98 TAN SCALER NUM.21 GATE CONTROL INVERTED IN 24 IGT21 99 ORANGE SCALER NUM.20 GATE CONTROL NON-INVERTED IN 25 NGT20 100 TAN SCALER NUM.20 GATE CONTROL INVERTED IN 26 IGT20 101 YELLOW SCALER NUM.19 GATE CONTROL NON-INVERTED IN 27 NGT19 102 TAN SCALER NUM.19 GATE CONTROL INVERTED IN 28 IGT19 103 GREEN SCALER NUM.18 GATE CONTROL NON-INVERTED IN 29 NGT18 104 TAN SCALER NUM.18 GATE CONTROL INVERTED IN 30 IGT18 105 BLUE SCALER NUM.17 GATE CONTROL NON-INVERTED IN 31 NGT17 106 TAN SCALER NUM.17 GATE CONTROL INVERTED IN 32 IGT17 107 VIOLET SCALER NUM.16 GATE CONTROL NON-INVERTED IN 33 NGT16 108 TAN SCALER NUM.16 GATE CONTROL INVERTED IN 34 IGT16 109 GREY SCALER NUM.15 GATE CONTROL NON-INVERTED IN 35 NGT15 110 TAN SCALER NUM.15 GATE CONTROL INVERTED IN 36 IGT15 111 WHITE SCALER NUM.14 GATE CONTROL NON-INVERTED IN 37 NGT14 112 TAN SCALER NUM.14 GATE CONTROL INVERTED IN 38 IGT14 113 BLACK SCALER NUM.13 GATE CONTROL NON-INVERTED IN 39 NGT13 114 TAN SCALER NUM.13 GATE CONTROL INVERTED IN 40 IGT13 115 BROWN SCALER NUM.12 GATE CONTROL NON-INVERTED IN 41 NGT12 116 TAN SCALER NUM.12 GATE CONTROL INVERTED IN 42 IGT12 117 RED SCALER NUM.11 GATE CONTROL NON-INVERTED IN 43 NGT11 118 TAN SCALER NUM.11 GATE CONTROL INVERTED IN 44 IGT11 119 ORANGE SCALER NUM.10 GATE CONTROL NON-INVERTED IN 45 NGT10 120 TAN SCALER NUM.10 GATE CONTROL INVERTED IN 46 IGT10 121 YELLOW SCALER NUM. 9 GATE CONTROL NON-INVERTED IN 47 NGT 9 122 TAN SCALER NUM. 9 GATE CONTROL INVERTED IN 48 IGT 9 123 GREEN SCALER NUM. 8 GATE CONTROL NON-INVERTED IN 49 NGT 8 124 TAN SCALER NUM. 8 GATE CONTROL INVERTED IN 50 IGT 8 125 BLUE SCALER NUM. 7 GATE CONTROL NON-INVERTED IN 51 NGT 7 126 TAN SCALER NUM. 7 GATE CONTROL INVERTED IN 52 IGT 7 127 VIOLET SCALER NUM. 6 GATE CONTROL NON-INVERTED IN 53 NGT 6 128 TAN SCALER NUM. 6 GATE CONTROL INVERTED IN 54 IGT 6 129 GREY SCALER NUM. 5 GATE CONTROL NON-INVERTED IN 55 NGT 5 130 TAN SCALER NUM. 5 GATE CONTROL INVERTED IN 56 IGT 5 131 WHITE SCALER NUM. 4 GATE CONTROL NON-INVERTED IN 57 NGT 4 132 TAN SCALER NUM. 4 GATE CONTROL INVERTED IN 58 IGT 4 133 BLACK SCALER NUM. 3 GATE CONTROL NON-INVERTED IN 59 NGT 3 134 TAN SCALER NUM. 3 GATE CONTROL INVERTED IN 60 IGT 3 135 BROWN SCALER NUM. 2 GATE CONTROL NON-INVERTED IN 61 NGT 2 136 TAN SCALER NUM. 2 GATE CONTROL INVERTED IN 62 IGT 2 137 RED SCALER NUM. 1 GATE CONTROL NON-INVERTED IN 63 NGT 1 138 TAN SCALER NUM. 1 GATE CONTROL INVERTED IN 64 IGT 1 139 GROUND GND 140 GROUND GND ------------------------------------------------------------------------------ CONNECTOR J2 ------------- ------------------------------------------------------------------------------ PIN COLOR FUNCTION PLUG & MNEMONIC # ON CABLE WIRE # ON CABLE ------------------------------------------------------------------------------ 1 GROUND GND 2 GROUND GND 3 SCALER CLOCK INPUT NON-INVERTED NCLK 4 SCLAER CLOCK INPUT INVERTED ICLK 5 NOT USED 6 NOT USED . . . . 20 NOT USED 67 GROUND GND 68 GROUND GND 69 POWER +5.0 V VCC 70 POWER +5.0 V VCC 71 POWER -5.2 V VEE 72 POWER -5.2 V VEE 73 GROUND GND 74 GROUND GND 75 BROWN TIMING & SYNC. SIGNAL A NON-INVERTED IN 1 NTSA 76 TAN TIMING & SYNC. SIGNAL A INVERTED IN 2 ITSA 77 RED TIMING & SYNC. SIGNAL B NON-INVERTED IN 3 NTSB 78 TAN timing & sync. signal B inverted in 4 ITSB 79 ORANGE TIMING & SYNC. SIGNAL C NON-INVERTED IN 5 NTSC 80 TAN TIMING & SYNC. SIGNAL C INVERTED IN 6 ITSC 81 YELLOW TIMING & SYNC. SIGNAL D NON-INVERTED IN 7 NTSD 82 TAN TIMING & SYNC. SIGNAL D INVERTED IN 8 ITSD note: Timing Signal D is the SCALER COMMON CLOCK Input. 83 GREEN TIMING & SYNC. SIGNAL E NON-INVERTED IN 9 NTSE 84 TAN TIMING & SYNC. SIGNAL E INVERTED IN 10 ITSE note: Timing Signal E is the EXTERNAL SCAN RESET LOAD Input. 85 BLUE TIMING & SYNC. SIGNAL F NON-INVERTED IN 11 NTSF 86 TAN TIMING & SYNC. SIGNAL F INVERTED IN 12 ITSF 87 VIOLET TIMING & SUNC. SIGNAL G NON-INVERTED IN 13 NTSG 88 TAN TIMING & SYNC. SIGNAL G INVERTED IN 14 ITSG 89 GREY TIMING & SYNC. SIGNAL H NON-INVERTED IN 15 NTSH 90 TAN TIMING & SYNC. SIGNAL H INVERTED IN 16 ITSH 91 WHITE CARD ADDRESS BIT#1 NON-INVERTED IN 17 NAC1 92 TAN CARD ADDRESS BIT#1 INVERTED IN 18 IAC1 93 BLACK CARD ADDRESS BIT#2 NON-INVERTED IN 19 NAC2 94 TAN CARD ADDRESS BIT#2 INVERTED IN 20 IAC2 95 BROWN CARD ADDRESS BIT#3 NON-INVERTED IN 21 NAC3 96 TAN CARD ADDRESS BIT#3 INVERTED IN 22 IAC3 97 RED CARD ADDRESS BIT#4 NON-INVERTED IN 23 NAC4 98 TAN CARD ADDRESS BIT#4 INVERTED IN 24 IAC4 99 ORANGE CARD ADDRESS BIT#5 NON-INVERTED IN 25 NAC5 100 TAN CARD ADDRESS BIT#5 INVERTED IN 26 IAC5 101 YELLOW CARD ADDRESS BIT#6 NON-INVERTED IN 27 NAC6 102 TAN CARD ADDRESS BIT#6 INVERTED IN 28 IAC6 103 GREEN FUNCTION ADDRESS BIT#1 NON-INVERTED IN 29 NAF1 104 TAN FUNCTION ADDRESS BIT#1 INVERTED IN 30 IAF1 105 BLUE FUNCTION ADDRESS BIT#2 NON-INVERTED IN 31 NAF2 106 TAN FUNCTION ADDRESS BIT#2 INVERTED IN 32 IAF2 107 VIOLET FUNCTION ADDRESS BIT#3 NON-INVERTED IN 33 NAF3 108 TAN FUNCTION ADDRESS BIT#3 INVERTED IN 34 IAF3 109 GREY FUNCTION ADDRESS BIT#4 NON-INVERTED IN 35 NAF4 110 TAN FUNCTION ADDRESS BIT#4 INVERTED IN 36 IAF4 111 WHITE FUNCTION ADDRESS BIT#5 NON-INVERTED IN 37 NAF5 112 TAN FUNCTION ADDRESS BIT#5 INVERTED IN 38 IAF5 113 BLACK FUNCTION ADDRESS BIT#6 NON-INVERTED IN 39 NAF6 114 TAN FUNCTION ADDRESS BIT#6 INVERTED IN 40 IAF6 115 BROWN FUNCTION ADDRESS BIT#7 NON-INVERTED IN 41 NAF7 116 TAN FUNCTION ADDRESS BIT#7 INVERTED IN 42 IAF7 117 RED FUNCTION ADDRESS BIT#8 NON-INVERTED IN 43 NAF8 118 TAN FUNCTION ADDRESS BIT#8 INVERTED IN 44 IAF8 119 ORANGE STROBE NON-INVERTED IN 45 NSTB 120 TAN STROBE INVERTED IN 46 ISTB 121 YELLOW DIRECTION NON-INVERTED IN 47 NDIR 122 TAN DIRECTION INVERTED IN 48 IDIR 123 GREEN BIDIRECTIONAL DATA BIT#1 NON-INVERTED IN 49 NDB1 124 TAN BIDIRECTIONAL DATA BIT#1 INVERTED IN 50 IDB1 125 BLUE BIDIRECTIONAL DATA BIT#2 NON-INVERTED IN 51 NDB2 126 TAN BIDIRECTIONAL DATA BIT#2 INVERTED IN 52 IDB2 127 VIOLET BIDIRECTIONAL DATA BIT#3 NON-INVERTED IN 53 NDB3 128 TAN BIDIRECTIONAL DATA BIT#3 INVERTED IN 54 IDB3 129 GREY BIDIRECTIONAL DATA BIT#4 NON-INVERTED IN 55 NDB4 130 TAN BIDIRECTIONAL DATA BIT#4 INVERTED IN 56 IDB4 131 WHITE BIDIRECTIONAL DATA BIT#5 NON-INVERTED IN 57 NDB5 132 TAN BIDIRECTIONAL DATA BIT#5 INVERTED IN 58 IDB5 133 BLACK BIDIRECTIONAL DATA BIT#6 NON-INVERTED IN 59 NDB6 134 TAN BIDIRECTIONAL DATA BIT#6 INVERTED IN 60 IDB6 135 BROWN BIDIRECTIONAL DATA BIT#7 NON-INVERTED IN 61 NDB7 136 TAN BIDIRECTIONAL DATA BIT#7 INVERTED IN 62 IDB7 137 RED BIDIRECTIONAL DATA BIT#8 NON-INVERTED IN 63 NDB8 138 TAN BIDIRECTIONAL DATA BIT#8 INVERTED IN 64 IDB8 139 GROUND GND 140 GROUND GND ------------------------------------------------------------------------------ ****************************************************************************** FIXING : 1. FOR EXT. SCAN RESET/LOAD SIGNAL: Change the input signal from timeing & sync. #C to #E A. Cut the trace from J2-79 TO THE VIA. Cut the trace from J2-80 TO THE VIA. B. CONNECTE J2-83 TO THE VIA CONNECTED TO J2-79 BEFORE. CONNECTE J2-84 TO THE VIA CONNECTED TO J2-80 BEFORE. C. Remove resistor R201. 2. FIX THE SCAN RESET/LOAD LOGIC A. CUT TRACE U253 PIN1 - VIA CUT TRACE U253 PIN3 - VIA B. CONNECTE U253 PIN1 TO PIN5 CONNECTE U253 PIN4 TO VIA CONNECTED TO PIN1 BEFORE CONNECTE U253 PIN6 TO VIA CONNECTED TO PIN3 BEFORE CONNECTE U253 PIN3 TO VIA CONNECTED TO GROUND 3. CHANGE TEXT 'WAKUP' TO 'CLK' CHANGE TEXT 'CLK' TO 'WAKUP' 4. THE LED DRIVERS U185,U195,U205,U215 SHOULD BE 74ALS541 5. FIX COUNTERS: A. CUT TRACES BETWEEN PIN16 - PIN17 OF CHIP U131,U135,U141,U145 U151,U155,U161,U165 B. CONNECT PIN16 OF THESE CHIPS TO PIN16 OF THE CHIPS U(NUM+1). 6. FIX SCALER CLOCK INPUT A. Cut traces: J2-3 to (via leading to) U250 pin11 J2-4 to (via leading to) U250 pin10 B. Install traces: J2-81 to U250 pin11 J2-82 to U250 pin10 C. Remove resistor R202 JAN - 5 - 1988 ECOs NECESSARY FOR SBSC USE IN LEVEL 1.5 TRIGGER FRAMEWORK (Cycle/Skip and Timeout/DeadCrossing SBSC's) ---------------------------------------------------------- 1. Perform all of the ECOs described above EXCEPT FOR ECO #6. These SBSC's should not have their common clock signal moved to the CBUS. 2. These SBSC's need to have 2 Clock signals. One (the original Common Clock, located on J2-3 and J2-4) must clock the lower 16 scalers, and the other (the added Clock, located on J2-7 and J2-8) must clock the upper 16 scalers. The original Common Clock will still be displayed on the "CLOCK" LED at the front of the card. A. Cut the following traces: U252-15 to nearby via (solder side) U252-16 to nearby via (solder side) B. Add the following traces: U252-12 to via formerly connected to U252-15 (solder side) U252-13 to via formerly connected to U252-16 (solder side) U250-4 to U252-7 AND U252-8 (component side) J2-7 to U250-3 (solder side) J2-8 to U250-2 (solder side) ****************************************************************************** 22-APR-1991 Standard configuration of SBSC scaler number vs trigger number and veto type scaler specific trigger veto type ------ ---------------- --------- 0 n+3 Spare = Beam Crossing 1 Autodisable 2 Global disable 3 Auxiliary 4 Front-End Busy 5 Level 2 6 Level 1.5 7 Prescaler 8 n+2 Spare = Beam Crossing 9 Autodisable 10 Global disable 11 Auxiliary 12 Front-End Busy 13 Level 2 14 Level 1.5 15 Prescaler 16 n+1 Spare = Beam Crossing 17 Autodisable 18 Global disable 19 Auxiliary 20 Front-End Busy 21 Level 2 22 Level 1.5 23 Prescaler 24 n+0 Spare = Beam Crossing 25 Autodisable 26 Global disable 27 Auxiliary 28 Front-End Busy 29 Level 2 30 Level 1.5 31 Prescaler ******************************************************************************