---------------------------------------------------------------- ! ! ! FIRST LEVEL TRIGGER SYSTEM TRIGGER LATCH/FAN OUT CARD ! ! ! ---------------------------------------------------------------- Michigan State University - 12-Jun-1987 NOTE: IN GENERAL THE FUNCTION OF THE TIMING SIGNALS IN THIS ----- DESCRIPTION DOES NOT MATCH WHAT WAS BUILT. D.E. 22-AUG-1988 GENERAL DESCRIPTION The Trigger Latch Module (TLM) card is a dual purpose card. Its primary mode of operation is to receive 32 differential ECL signals via a front panel ribbon cable, latch those signals, and drive them out the backplane and one front panel connector. Its second mode of operation is as a FAN OUT card with the latching function disabled. In this mode of operation 32 differential signals are received via a front panel ribbon cable and driven out the backplane and an additional front panel connector. In addition to its latched or unlatched buffer function the TLM card forms a logical or of the 32 input signals, latches the logical or signal and provides the latched and unlatched versions of this signal out the front panel. There is one TLM used in latch mode to drive each section of DIGIMEM cards used in the Trigger Framework. TLM cards will also be used as needed in FAN OUT mode to buffer signals for distribution. This card receives 32 differential ECL signals from front panel ribbon cable J6. These signals are latched using a computer bus timing signal from connector J5. The signals are then driven out on connectors J1, J2, and J3. The Trigger Latch Module has 6 connectors for power and I/O. These connectors are labeled J1 through J6. The number of pins and function of each connector is listed in the table below. connector # pins function ---------------------------------------------- J1 128 power, buffered output groups 1 and 2 J2 128 power, buffered output groups 3 and 4 J3 64 buffered output group 5 J4 34 global trigger out J5 64 computer bus J6 64 TLM input lines The Trigger Latch Module uses only one power supply. A power supply -5.2 volts @ 3.5 amps is used to supply the power for all logic on the board. This supply is provided from connectors J1 and J2. PROGRAMMING The Trigger Latch module has no programable registers. The computer bus is brought to the TLM card only to provide four timing signals. One timing signal for the 32 bit latch, one timing signal for the global Latched Data, one to reset the global latched data, and one to control the LED's off signal. Timing signal H is used to control the LED's. The LED's are extinguished when this timing signal is asserted. Timing signal G is used to latch the input data. When this signal is low the output drivers follow the input signal. The input signal is latched on the FALLING edge of timing signal G and remains latched as long as timing signal G is held LOW. Timing signal F is used to latch the global trigger (the logical or of all 32 inputs). The global trigger is latched and held on the rising edge of timing signal F. Timing signal E is used to reset the global trigger latch. The global trigger is reset when timing signal E is asserted and is held in the reset state as long as timing signal E is held high. This information is summarized in the table below. Timing Signal Low State High State --------------------------------------------------- H LED's on LED's off G setup data latched transparent F (latch global trigger on rising edge) E no action reset global trigger The Trigger Latch Module has two places for wire wrap jumpers. With one jumper the card may be forced to be a Latch Module or a Buffer Module. Note this jumper is pre-etched for Latch Module operation and a trace must be cut to allow Buffer Module operation. The other wire wrap jumpers select which pins of J4 will carry the global trigger and latched global trigger signals. There are three pairs of differential led displays these are used to display the states of the Latch drive timing signal, the global trigger, and the latched global trigger. CONNECTORS J1 : FIRST LEVEL TRIGGER CONTROL COMPUTER BUS 140 PIN CONNECTOR ------------------------------------------------------------------------------ Plug & Pin Function Wire # Mnemonic # on cable ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Latched Data Bit#1 Non-inverted IN 1 NTL1 4 Latched Data Bit#1 Inverted IN 2 ITL1 5 Latched Data Bit#2 Non-inverted IN 1 NTL2 6 Latched Data Bit#2 Inverted IN 2 ITL2 7 Latched Data Bit#3 Non-inverted IN 1 NTL3 8 Latched Data Bit#3 Inverted IN 2 ITL3 9 Latched Data Bit#4 Non-inverted IN 1 NTL4 10 Latched Data Bit#4 Inverted IN 2 ITL4 11 Latched Data Bit#5 Non-inverted IN 1 NTL5 12 Latched Data Bit#5 Inverted IN 2 ITL5 13 Latched Data Bit#6 Non-inverted IN 1 NTL6 14 Latched Data Bit#6 Inverted IN 2 ITL6 15 Latched Data Bit#7 Non-inverted IN 1 NTL7 16 Latched Data Bit#7 Inverted IN 2 III7 17 Latched Data Bit#8 Non-inverted IN 1 NTL8 18 Latched Data Bit#8 Inverted IN 2 ITL8 19 Latched Data Bit#9 Non-inverted IN 1 NTL9 20 Latched Data Bit#9 Inverted IN 2 ITL9 21 Latched Data Bit#10 Non-inverted IN 1 NTL10 22 Latched Data Bit#10 Inverted IN 2 ITL10 23 Latched Data Bit#11 Non-inverted IN 1 NTL10 24 Latched Data Bit#11 Inverted IN 2 ITL11 25 Latched Data Bit#12 Non-inverted IN 1 NTL12 26 Latched Data Bit#12 Inverted IN 2 ITL12 27 Latched Data Bit#13 Non-inverted IN 1 NTL13 28 Latched Data Bit#13 Inverted IN 2 ITL13 29 Latched Data Bit#14 Non-inverted IN 1 NTL14 30 Latched Data Bit#14 Inverted IN 2 ITL14 31 Latched Data Bit#15 Non-inverted IN 1 NTL15 32 Latched Data Bit#15 Inverted IN 2 ITL15 33 Latched Data Bit#16 Non-inverted IN 1 NTL16 34 Latched Data Bit#16 Inverted IN 2 ITL16 35 Latched Data Bit#17 Non-inverted IN 1 NTL17 36 Latched Data Bit#17 Inverted IN 2 ITL17 37 Latched Data Bit#18 Non-inverted IN 1 NTL18 38 Latched Data Bit#18 Inverted IN 2 ITL18 39 Latched Data Bit#19 Non-inverted IN 1 NTL19 40 Latched Data Bit#19 Inverted IN 2 ITL19 41 Latched Data Bit#20 Non-inverted IN 1 NTL20 42 Latched Data Bit#20 Inverted IN 2 ITL20 43 Latched Data Bit#21 Non-inverted IN 1 NTL21 44 Latched Data Bit#21 Inverted IN 2 ITL21 45 Latched Data Bit#22 Non-inverted IN 1 NTL22 46 Latched Data Bit#22 Inverted IN 2 ITL22 47 Latched Data Bit#23 Non-inverted IN 1 NTL23 48 Latched Data Bit#23 Inverted IN 2 ITL23 49 Latched Data Bit#24 Non-inverted IN 1 NTL24 50 Latched Data Bit#24 Inverted IN 2 ITL24 51 Latched Data Bit#25 Non-inverted IN 1 NTL25 52 Latched Data Bit#25 Inverted IN 2 ITL25 53 Latched Data Bit#26 Non-inverted IN 1 NTL26 54 Latched Data Bit#26 Inverted IN 2 ITL26 55 Latched Data Bit#27 Non-inverted IN 1 NTL27 56 Latched Data Bit#27 Inverted IN 2 ITL27 57 Latched Data Bit#28 Non-inverted IN 1 NTL28 58 Latched Data Bit#28 Inverted IN 2 ITL28 59 Latched Data Bit#29 Non-inverted IN 1 NTL29 60 Latched Data Bit#29 Inverted IN 2 ITL29 61 Latched Data Bit#30 Non-inverted IN 1 NTL30 62 Latched Data Bit#30 Inverted IN 2 ITL30 63 Latched Data Bit#31 Non-inverted IN 1 NTL31 64 Latched Data Bit#31 Inverted IN 2 ITL31 65 Latched Data Bit#32 Non-inverted IN 1 NTL32 66 Latched Data Bit#32 Inverted IN 2 ITL32 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 Latched Data Bit#1 Non-inverted IN 1 NTL1 76 Latched Data Bit#1 Inverted IN 2 ITL1 77 Latched Data Bit#2 Non-inverted IN 1 NTL2 78 Latched Data Bit#2 Inverted IN 2 ITL2 79 Latched Data Bit#3 Non-inverted IN 1 NTL3 80 Latched Data Bit#3 Inverted IN 2 ITL3 81 Latched Data Bit#4 Non-inverted IN 1 NTL4 82 Latched Data Bit#4 Inverted IN 2 ITL4 83 Latched Data Bit#5 Non-inverted IN 1 NTL5 84 Latched Data Bit#5 Inverted IN 2 ITL5 85 Latched Data Bit#6 Non-inverted IN 1 NTL6 86 Latched Data Bit#6 Inverted IN 2 ITL6 87 Latched Data Bit#7 Non-inverted IN 1 NTL7 88 Latched Data Bit#7 Inverted IN 2 ITL7 89 Latched Data Bit#8 Non-inverted IN 1 NTL8 90 Latched Data Bit#8 Inverted IN 2 ITL8 91 Latched Data Bit#9 Non-inverted IN 1 NTL9 92 Latched Data Bit#9 Inverted IN 2 ITL9 93 Latched Data Bit#10 Non-inverted IN 1 NTL10 94 Latched Data Bit#10 Inverted IN 2 ITL10 95 Latched Data Bit#11 Non-inverted IN 1 NTL11 96 Latched Data Bit#11 Inverted IN 2 ITL11 97 Latched Data Bit#12 Non-inverted IN 1 NTL12 98 Latched Data Bit#12 Inverted IN 2 ITL12 99 Latched Data Bit#13 Non-inverted IN 1 NTL13 100 Latched Data Bit#13 Inverted IN 2 ITL13 101 Latched Data Bit#14 Non-inverted IN 1 NTL14 102 Latched Data Bit#14 Inverted IN 2 ITL14 103 Latched Data Bit#15 Non-inverted IN 1 NTL15 104 Latched Data Bit#15 Inverted IN 2 ITL15 105 Latched Data Bit#16 Non-inverted IN 1 NTL16 106 Latched Data Bit#16 Inverted IN 2 ITL16 107 Latched Data Bit#17 Non-inverted IN 1 NTL17 108 Latched Data Bit#17 Inverted IN 2 ITL17 109 Latched Data Bit#18 Non-inverted IN 1 NTL18 110 Latched Data Bit#18 Inverted IN 2 ITL18 111 Latched Data Bit#19 Non-inverted IN 1 NTL19 112 Latched Data Bit#19 Inverted IN 2 ITL19 113 Latched Data Bit#20 Non-inverted IN 1 NTL20 114 Latched Data Bit#20 Inverted IN 2 ITL20 115 Latched Data Bit#21 Non-inverted IN 1 NTL21 116 Latched Data Bit#21 Inverted IN 2 ITL21 117 Latched Data Bit#22 Non-inverted IN 1 NTL22 118 Latched Data Bit#22 Inverted IN 2 ITL22 119 Latched Data Bit#23 Non-inverted IN 1 NTL23 120 Latched Data Bit#23 Inverted IN 2 ITL23 121 Latched Data Bit#24 Non-inverted IN 1 NTL24 122 Latched Data Bit#24 Inverted IN 2 ITL24 123 Latched Data Bit#25 Non-inverted IN 1 NTL25 124 Latched Data Bit#25 Inverted IN 2 ITL25 125 Latched Data Bit#26 Non-inverted IN 1 NTL26 126 Latched Data Bit#26 Inverted IN 2 ITL26 127 Latched Data Bit#27 Non-inverted IN 1 NTL27 128 Latched Data Bit#27 Inverted IN 2 ITL27 129 Latched Data Bit#28 Non-inverted IN 1 NTL28 130 Latched Data Bit#28 Inverted IN 2 ITL28 131 Latched Data Bit#29 Non-inverted IN 1 NTL29 132 Latched Data Bit#29 Inverted IN 2 ITL29 133 Latched Data Bit#30 Non-inverted IN 1 NTL30 134 Latched Data Bit#30 Inverted IN 2 ITL30 135 Latched Data Bit#31 Non-inverted IN 1 NTL31 136 Latched Data Bit#31 Inverted IN 2 ITL31 137 Latched Data Bit#32 Non-inverted IN 1 NTL32 138 Latched Data Bit#32 Inverted IN 2 ITL32 139 Ground GND 140 Ground GND ----------------------------------------------------------------------------- J2 : FIRST LEVEL TRIGGER CONTROL COMPUTER BUS 140 PIN CONNECTOR ------------------------------------------------------------------------------ Plug & Pin Function Wire # Mnemonic # on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 Latched Data Bit#1 Non-inverted IN 1 NTL1 4 Latched Data Bit#1 Inverted IN 2 ITL1 5 Latched Data Bit#2 Non-inverted IN 1 NTL2 6 Latched Data Bit#2 Inverted IN 2 ITL2 7 Latched Data Bit#3 Non-inverted IN 1 NTL3 8 Latched Data Bit#3 Inverted IN 2 ITL3 9 Latched Data Bit#4 Non-inverted IN 1 NTL4 10 Latched Data Bit#4 Inverted IN 2 ITL4 11 Latched Data Bit#5 Non-inverted IN 1 NTL5 12 Latched Data Bit#5 Inverted IN 2 ITL5 13 Latched Data Bit#6 Non-inverted IN 1 NTL6 14 Latched Data Bit#6 Inverted IN 2 ITL6 15 Latched Data Bit#7 Non-inverted IN 1 NTL7 16 Latched Data Bit#7 Inverted IN 2 III7 17 Latched Data Bit#8 Non-inverted IN 1 NTL8 18 Latched Data Bit#8 Inverted IN 2 ITL8 19 Latched Data Bit#9 Non-inverted IN 1 NTL9 20 Latched Data Bit#9 Inverted IN 2 ITL9 21 Latched Data Bit#10 Non-inverted IN 1 NTL10 22 Latched Data Bit#10 Inverted IN 2 ITL10 23 Latched Data Bit#11 Non-inverted IN 1 NTL10 24 Latched Data Bit#11 Inverted IN 2 ITL11 25 Latched Data Bit#12 Non-inverted IN 1 NTL12 26 Latched Data Bit#12 Inverted IN 2 ITL12 27 Latched Data Bit#13 Non-inverted IN 1 NTL13 28 Latched Data Bit#13 Inverted IN 2 ITL13 29 Latched Data Bit#14 Non-inverted IN 1 NTL14 30 Latched Data Bit#14 Inverted IN 2 ITL14 31 Latched Data Bit#15 Non-inverted IN 1 NTL15 32 Latched Data Bit#15 Inverted IN 2 ITL15 33 Latched Data Bit#16 Non-inverted IN 1 NTL16 34 Latched Data Bit#16 Inverted IN 2 ITL16 35 Latched Data Bit#17 Non-inverted IN 1 NTL17 36 Latched Data Bit#17 Inverted IN 2 ITL17 37 Latched Data Bit#18 Non-inverted IN 1 NTL18 38 Latched Data Bit#18 Inverted IN 2 ITL18 39 Latched Data Bit#19 Non-inverted IN 1 NTL19 40 Latched Data Bit#19 Inverted IN 2 ITL19 41 Latched Data Bit#20 Non-inverted IN 1 NTL20 42 Latched Data Bit#20 Inverted IN 2 ITL20 43 Latched Data Bit#21 Non-inverted IN 1 NTL21 44 Latched Data Bit#21 Inverted IN 2 ITL21 45 Latched Data Bit#22 Non-inverted IN 1 NTL22 46 Latched Data Bit#22 Inverted IN 2 ITL22 47 Latched Data Bit#23 Non-inverted IN 1 NTL23 48 Latched Data Bit#23 Inverted IN 2 ITL23 49 Latched Data Bit#24 Non-inverted IN 1 NTL24 50 Latched Data Bit#24 Inverted IN 2 ITL24 51 Latched Data Bit#25 Non-inverted IN 1 NTL25 52 Latched Data Bit#25 Inverted IN 2 ITL25 53 Latched Data Bit#26 Non-inverted IN 1 NTL26 54 Latched Data Bit#26 Inverted IN 2 ITL26 55 Latched Data Bit#27 Non-inverted IN 1 NTL27 56 Latched Data Bit#27 Inverted IN 2 ITL27 57 Latched Data Bit#28 Non-inverted IN 1 NTL28 58 Latched Data Bit#28 Inverted IN 2 ITL28 59 Latched Data Bit#29 Non-inverted IN 1 NTL29 60 Latched Data Bit#29 Inverted IN 2 ITL29 61 Latched Data Bit#30 Non-inverted IN 1 NTL30 62 Latched Data Bit#30 Inverted IN 2 ITL30 63 Latched Data Bit#31 Non-inverted IN 1 NTL31 64 Latched Data Bit#31 Inverted IN 2 ITL31 65 Latched Data Bit#32 Non-inverted IN 1 NTL32 66 Latched Data Bit#32 Inverted IN 2 ITL32 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 Latched Data Bit#1 Non-inverted IN 1 NTL1 76 Latched Data Bit#1 Inverted IN 2 ITL1 77 Latched Data Bit#2 Non-inverted IN 1 NTL2 78 Latched Data Bit#2 Inverted IN 2 ITL2 79 Latched Data Bit#3 Non-inverted IN 1 NTL3 80 Latched Data Bit#3 Inverted IN 2 ITL3 81 Latched Data Bit#4 Non-inverted IN 1 NTL4 82 Latched Data Bit#4 Inverted IN 2 ITL4 83 Latched Data Bit#5 Non-inverted IN 1 NTL5 84 Latched Data Bit#5 Inverted IN 2 ITL5 85 Latched Data Bit#6 Non-inverted IN 1 NTL6 86 Latched Data Bit#6 Inverted IN 2 ITL6 87 Latched Data Bit#7 Non-inverted IN 1 NTL7 88 Latched Data Bit#7 Inverted IN 2 ITL7 89 Latched Data Bit#8 Non-inverted IN 1 NTL8 90 Latched Data Bit#8 Inverted IN 2 ITL8 91 Latched Data Bit#9 Non-inverted IN 1 NTL9 92 Latched Data Bit#9 Inverted IN 2 ITL9 93 Latched Data Bit#10 Non-inverted IN 1 NTL10 94 Latched Data Bit#10 Inverted IN 2 ITL10 95 Latched Data Bit#11 Non-inverted IN 1 NTL11 96 Latched Data Bit#11 Inverted IN 2 ITL11 97 Latched Data Bit#12 Non-inverted IN 1 NTL12 98 Latched Data Bit#12 Inverted IN 2 ITL12 99 Latched Data Bit#13 Non-inverted IN 1 NTL13 100 Latched Data Bit#13 Inverted IN 2 ITL13 101 Latched Data Bit#14 Non-inverted IN 1 NTL14 102 Latched Data Bit#14 Inverted IN 2 ITL14 103 Latched Data Bit#15 Non-inverted IN 1 NTL15 104 Latched Data Bit#15 Inverted IN 2 ITL15 105 Latched Data Bit#16 Non-inverted IN 1 NTL16 106 Latched Data Bit#16 Inverted IN 2 ITL16 107 Latched Data Bit#17 Non-inverted IN 1 NTL17 108 Latched Data Bit#17 Inverted IN 2 ITL17 109 Latched Data Bit#18 Non-inverted IN 1 NTL18 110 Latched Data Bit#18 Inverted IN 2 ITL18 111 Latched Data Bit#19 Non-inverted IN 1 NTL19 112 Latched Data Bit#19 Inverted IN 2 ITL19 113 Latched Data Bit#20 Non-inverted IN 1 NTL20 114 Latched Data Bit#20 Inverted IN 2 ITL20 115 Latched Data Bit#21 Non-inverted IN 1 NTL21 116 Latched Data Bit#21 Inverted IN 2 ITL21 117 Latched Data Bit#22 Non-inverted IN 1 NTL22 118 Latched Data Bit#22 Inverted IN 2 ITL22 119 Latched Data Bit#23 Non-inverted IN 1 NTL23 120 Latched Data Bit#23 Inverted IN 2 ITL23 121 Latched Data Bit#24 Non-inverted IN 1 NTL24 122 Latched Data Bit#24 Inverted IN 2 ITL24 123 Latched Data Bit#25 Non-inverted IN 1 NTL25 124 Latched Data Bit#25 Inverted IN 2 ITL25 125 Latched Data Bit#26 Non-inverted IN 1 NTL26 126 Latched Data Bit#26 Inverted IN 2 ITL26 127 Latched Data Bit#27 Non-inverted IN 1 NTL27 128 Latched Data Bit#27 Inverted IN 2 ITL27 129 Latched Data Bit#28 Non-inverted IN 1 NTL28 130 Latched Data Bit#28 Inverted IN 2 ITL28 131 Latched Data Bit#29 Non-inverted IN 1 NTL29 132 Latched Data Bit#29 Inverted IN 2 ITL29 133 Latched Data Bit#30 Non-inverted IN 1 NTL30 134 Latched Data Bit#30 Inverted IN 2 ITL30 135 Latched Data Bit#31 Non-inverted IN 1 NTL31 136 Latched Data Bit#31 Inverted IN 2 ITL31 137 Latched Data Bit#32 Non-inverted IN 1 NTL32 138 Latched Data Bit#32 Inverted IN 2 ITL32 139 Ground GND 140 Ground GND ---------------------------------------------------------------------------- J3 : AUX TLM OUTPUT CONNECTOR ------------------------------------------------------------------------------ Pin # Color on on cable Function Mnemonic Cable ------------------------------------------------------------------------------- 1 Brown Latched Data Bit#32 Non-inverted NTL32 2 Tan Latched Data Bit#32 Inverted ITL32 3 Red Latched Data Bit#31 Non-inverted NTL31 4 Tan Latched Data Bit#31 Inverted ITL31 5 Orange Latched Data Bit#30 Non-inverted NTL30 6 Tan Latched Data Bit#30 Inverted ITL30 7 Yellow Latched Data Bit#29 Non-inverted NTL29 8 Tan Latched Data Bit#29 Inverted ITL29 9 Green Latched Data Bit#28 Non-inverted NYL28 10 Tan Latched Data Bit#28 Inverted ITL28 11 Blue Latched Data Bit#27 Non-inverted NTL27 12 Tan Latched Data Bit#27 Inverted ITL27 13 Violet Latched Data Bit#26 Non-inverted NTL26 14 Tan Latched Data Bit#26 Inverted ITL26 15 Grey Latched Data Bit#25 Non-inverted NTL25 16 Tan Latched Data Bit#25 Inverted ITL25 17 White Latched Data Bit#24 Non-inverted NTL24 18 Tan Latched Data Bit#24 Inverted ITL24 19 Black Latched Data Bit#23 Non-inverted NTL23 20 Tan Latched Data Bit#23 Inverted ITL23 21 Brown Latched Data Bit#22 Non-inverted NTL22 22 Tan Latched Data Bit#22 Inverted ITL22 23 Red Latched Data Bit#21 Non-inverted NTL21 24 Tan Latched Data Bit#21 Inverted ITL21 25 Orange Latched Data Bit#20 Non-inverted NTL20 26 Tan Latched Data Bit#20 Inverted ITL20 27 Yellow Latched Data Bit#19 Non-inverted NTL19 28 Tan Latched Data Bit#19 Inverted ITL19 29 Green Latched Data Bit#18 Non-inverted NTL18 30 Tan Latched Data Bit#18 Inverted ITL18 31 Blue Latched Data Bit#17 Non-inverted NTL17 32 Tan Latched Data Bit#17 Inverted NTL17 33 Violet Latched Data Bit#16 Non-inverted NTL16 34 Tan Latched Data Bit#16 Inverted ITL16 35 Grey Latched Data Bit#15 Non-inverted NTL15 36 Tan Latched Data Bit#15 Inverted ITL15 37 White Latched Data Bit#14 Non-inverted NTL14 38 Tan Latched Data Bit#14 Inverted ITL14 33 Black Latched Data Bit#13 Non-inverted NTL13 40 Tan Latched Data Bit#13 Inverted ITL13 41 Brown Latched Data Bit#12 Non-inverted NTL12 42 Tan Latched Data Bit#12 Inverted ITL12 43 Red Latched Data Bit#11 Non-inverted NTL11 44 Tan Latched Data Bit#11 Inverted ITL11 45 Orange Latched Data Bit#10 Non-inverted NTL10 46 Tan Latched Data Bit#10 Inverted ITL10 47 Yellow Latched Data Bit#9 Non-inverted NTL9 48 Tan Latched Data Bit#9 Inverted ITL9 49 Green Latched Data Bit#8 Non-inverted NTL8 50 Tan Latched Data Bit#8 Inverted ITL8 51 Blue Latched Data Bit#7 Non-inverted NTL7 52 Tan Latched Data Bit#7 Inverted ITL7 53 Violet Latched Data Bit#6 Non-inverted NTL6 54 Tan Latched Data Bit#6 Inverted ITL6 55 Grey Latched Data Bit#5 Non-inverted NTL5 56 Tan Latched Data Bit#5 Inverted ITL5 57 White Latched Data Bit#4 Non-inverted NTL4 58 Tan Latched Data Bit#4 Inverted ITL4 59 Black Latched Data Bit#3 Non-inverted NTL3 60 Tan Latched Data Bit#3 Inverted ITL3 61 Brown Latched Data Bit#2 Non-inverted NTL2 62 Tan Latched Data Bit#2 Inverted ITL2 63 Red Latched Data Bit#1 Non-inverted NTL1 64 Tan Latched Data Bit#1 Inverted ITL1 ----------------------------------------------------------------------------- J5 : COMPUTER BUS CONNECTOR ------------------------------------------------------------------------------ Pin # Color on on cable Function Mnemonic Cable ---------------------------------------------------------------------------- 1 Brown Bidirectional Data Bit#8 Non-inverted NDB8 2 Tan Bidirectional Data Bit#8 Inverted IDB8 3 Red Bidirectional Data Bit#7 Non-inverted NDB7 4 Tan Bidirectional Data Bit#7 Inverted IDB7 5 Orange Bidirectional Data Bit#6 Non-inverted NDB6 6 Tan Bidirectional Data Bit#6 Inverted IDB6 7 Yellow Bidirectional Data Bit#5 Non-inverted NDB5 8 Tan Bidirectional Data Bit#5 Inverted IDB5 9 Green Bidirectional Data Bit#4 Non-inverted NDB4 10 Tan Bidirectional Data Bit#4 Inverted IDB4 11 Blue Bidirectional Data Bit#3 Non-inverted NDB3 12 Tan Bidirectional Data Bit#3 Inverted IDB3 13 Violet Bidirectional Data Bit#2 Non-inverted NDB2 14 Tan Bidirectional Data Bit#2 Inverted IDB2 15 Grey Bidirectional Data Bit#1 Non-inverted NDB1 16 Tan Bidirectional Data Bit#1 Inverted IDB1 17 White Direction Non-inverted NDIR 18 Tan Direction Inverted IDIR 19 Black Strobe Non-inverted NSTB 20 Tan Strobe Inverted ISTB 21 Brown Function Address Bit#8 Non-inverted NAF8 22 Tan Function Address Bit#8 Inverted IAF8 23 Red Function Address Bit#7 Non-inverted NAF7 24 Tan Function Address Bit#7 Inverted IAF7 25 Orange Function Address Bit#6 Non-inverted NAF6 26 Tan Function Address Bit#6 Inverted IAF6 27 Yellow Function Address Bit#5 Non-inverted NAF5 28 Tan Function Address Bit#5 Inverted IAF5 29 Green Function Address Bit#4 Non-inverted NAF4 30 Tan Function Address Bit#4 Inverted IAF4 31 Blue Function Address Bit#3 Non-inverted NAF3 32 Tan Function Address Bit#3 Inverted NAF3 33 Violet Function Address Bit#2 Non-inverted NAF2 34 Tan Function Address Bit#2 Inverted IAF2 35 Grey Function Address Bit#1 Non-inverted NAF1 36 Tan Function Address Bit#1 Inverted IAF1 37 White Card Address Bit#6 Non-inverted NAC6 38 Tan Card Address Bit#6 Inverted IAC6 33 Black Card Address Bit#5 Non-inverted NAC5 40 Tan Card Address Bit#5 Inverted IAC5 41 Brown Card Address Bit#4 Non-inverted NAC4 42 Tan Card Address Bit#4 Inverted IAC4 43 Red Card Address Bit#3 Non-inverted NAC3 44 Tan Card Address Bit#3 Inverted IAC3 45 Orange Card Address Bit#2 Non-inverted NAC2 46 Tan Card Address Bit#2 Inverted IAC2 47 Yellow Card Address Bit#1 Non-inverted NAC1 48 Tan Card Address Bit#1 Inverted IAC1 49 Green LED's off Non-inverted NTSH 50 Tan LED's off Inverted ITSH 51 Blue LATCH STROBE Non-inverted NTSG 52 Tan LATCH STROBE Inverted ITSG 53 Violet GLOBAL STROBE Non-inverted NTSF 54 Tan GLOBAL STROBE Inverted ITSF 55 Grey LATCH RESET Non-inverted NTSE 56 Tan LATCH RESET Inverted ITSE 57 White Timing & Sync. Signal D Non-inverted NTSD 58 Tan Timing & Sync. Signal D Inverted ITSD 59 Black Timing & Sync. Signal C Non-inverted NTSC 60 Tan Timing & Sync. Signal C Inverted ITSC 61 Brown Timing & Sync. Signal B Non-inverted NTSB 62 Tan Timing & Sync. Signal B Inverted ITSB 63 Red Timing & Sync. Signal A Non-inverted NTSA 64 Tan Timing & Sync. Signal A Inverted ITSA ----------------------------------------------------------------------------- J6 : TLM INPUT CONNECTOR ------------------------------------------------------------------------------ Pin # Color on on cable Function Mnemonic Cable ---------------------------------------------------------------------------- 1 Brown Input Data Bit#32 Non-inverted NDA32 2 Tan Input Data Bit#32 Inverted IDA32 3 Red Input Data Bit#31 Non-inverted NDA31 4 Tan Input Data Bit#31 Inverted IDB31 5 Orange Input Data Bit#30 Non-inverted NDA30 6 Tan Input Data Bit#30 Inverted IDA30 7 Yellow Input Data Bit#29 Non-inverted NDA29 8 Tan Input Data Bit#29 Inverted IDA29 9 Green Input Data Bit#28 Non-inverted NDA28 10 Tan Input Data Bit#28 Inverted IDA28 11 Blue Input Data Bit#27 Non-inverted NDA27 12 Tan Input Data Bit#27 Inverted IDA27 13 Violet Input Data Bit#26 Non-inverted NDA26 14 Tan Input Data Bit#26 Inverted IDA26 15 Grey Input Data Bit#25 Non-inverted NDA25 16 Tan Input Data Bit#25 Inverted IDA25 17 White Input Data Bit#24 Non-inverted NDA24 18 Tan Input Data Bit#24 Inverted IDA24 19 Black Input Data Bit#23 Non-inverted NDA23 20 Tan Input Data Bit#23 Inverted IDA23 21 Brown Input Data Bit#22 Non-inverted NDA22 22 Tan Input Data Bit#22 Inverted IDA22 23 Red Input Data Bit#21 Non-inverted NDA21 24 Tan Input Data Bit#21 Inverted IDA21 25 Orange Input Data Bit#20 Non-inverted NDA20 26 Tan Input Data Bit#20 Inverted ID120 27 Yellow Input Data Bit#19 Non-inverted NDA19 28 Tan Input Data Bit#19 Inverted IDA19 29 Green Input Data Bit#18 Non-inverted NDA18 30 Tan Input Data Bit#18 Inverted IDA18 31 Blue Input Data Bit#17 Non-inverted NDA17 32 Tan Input Data Bit#17 Inverted NDA17 33 Violet Input Data Bit#16 Non-inverted NDA16 34 Tan Input Data Bit#16 Inverted IDA16 35 Grey Input Data Bit#15 Non-inverted NDA15 36 Tan Input Data Bit#15 Inverted IDA15 37 White Input Data Bit#14 Non-inverted NDA14 38 Tan Input Data Bit#14 Inverted IDA14 33 Black Input Data Bit#13 Non-inverted NDA13 40 Tan Input Data Bit#13 Inverted IDA13 41 Brown Input Data Bit#12 Non-inverted NDA12 42 Tan Input Data Bit#12 Inverted IDA12 43 Red Input Data Bit#11 Non-inverted NDA11 44 Tan Input Data Bit#11 Inverted IDA11 45 Orange Input Data Bit#10 Non-inverted NDA10 46 Tan Input Data Bit#10 Inverted IDA10 47 Yellow Input Data Bit#9 Non-inverted NDA9 48 Tan Input Data Bit#9 Inverted IDA9 49 Green Input Data Bit#8 Non-inverted NDA8 50 Tan Input Data Bit#8 Inverted IDA8 51 Blue Input Data Bit#7 Non-inverted NDA7 52 Tan Input Data Bit#7 Inverted IDA7 53 Violet Input Data Bit#6 Non-inverted NDA6 54 Tan Input Data Bit#6 Inverted IDA6 55 Grey Input Data Bit#5 Non-inverted NDA5 56 Tan Input Data Bit#5 Inverted IDA5 57 White Input Data Bit#4 Non-inverted NDA4 58 Tan Input Data Bit#4 Inverted IDA4 59 Black Input Data Bit#3 Non-inverted NDA3 60 Tan Input Data Bit#3 Inverted IDA3 61 Brown Input Data Bit#2 Non-inverted NDA2 62 Tan Input Data Bit#2 Inverted IDA2 63 Red Input Data Bit#1 Non-inverted NDA1 64 Tan Input Data Bit#1 Inverted IDA1 ----------------------------------------------------------------------------- DRAWINGS - List of all the drawings produced with drawing numbers. List of every paper written about this board. BOARD HISTORY REVISION A: 16 built late 1986 and 1987. Signal line TRIGGER SUM has no pull down resistor. A 470 Ohm resistor TRIGGER SUM to VEE must be added. All boards were assembled with R80 and R83(??) incorrectly valued at 470 Ohms these resistors should be 56 Ohms. - Parts used : Quantity Item ----------- ---------- 8 10133 3 106A471 42 10H101 1 10H104 4 10H109 9 10H115 1 10H131 8 7902 6 DIALCO2001 1 110A560 23 316A560 4 316B101 1 470 OHM 1/4 WATT 1 3M34 1 34 PIN HEADER 1 8 PIN HEADER 1 3 PIN HEADER 3 3MR64 2 RBM140 65 MONOCAP 16 CCAP10005 PRODUCTION RUN 2 of REVISION A: ------------------------------- Eight more cards built summer 1988. These are the exact (?) same as earlier cards except for the first listed problem. 1. There is a short circuit at the Input connector (J6) between bit 32 and the Vee supply. To fix this cut the bit 32 traces and replace with wire wrap wire. This is on the "solder side" of the board. 2. If the card is going to be used with a LATCH STROBE Signal then the circuit near U63 should be changed so that LATCH STROBE is not ANDED with TRIGGER SUM to make LATCH DRIVE. This can be done by: Cut the trace between U63 pin 5 and U63 pin 7, Cut the trace between U41 pin 2 and U63 pin 5 (on top of card), Add a jumper between U41 pin 2 and U63 pin 7, Add a jumper between U63 pin 5 and U63 pin 9. This modification is needed with the cards from both the first and second production run. This modification is needed by the TLM card is slot 10 of the top backplane in rack M101 (Busy Signal to Specific Trigger Disable DIGIMEM's) and by the TLM in slot 10 of the top backplane of rack M102 (Specific Triggers Fired to Start Digitize DIGIMEM's). 3. If the TLM is going to use the GLOBAL TRIGGER output, without using a GLOBAL STROBE then the following modification should be made: Cut the trace from U54 pin 2 to U63 pin 6 on the bottom of the card, Install a jumper from U63 pin 6 to U63 pin 9. With this modification the TRIGGER SUM will always be driven off the card as GLOBAL TRIGGER. In addition if the LATCHED TRIGGER output is going to be used then make the following modifications to cause the LATCHED TRIGGER output to update on the falling edge of the LATCH STROBE signal (the same edge that puts the latches into Hold): Cut trace going between R82 pin 5 and U53 pin 7 (cut it on the top of the card near R82, Connect a jumper between R82 pin 6 and the plate through near pin 5 of this resistor network from which the trace was removed in the first step, Connect a jumper between U53 pin 10 and U53 pin 13, Connect a jumper between U53 pin 15 and U65 pin 11, Connect a jumper between U65 pin 10 and the plate through near this pin that leads to U63 pin 3, R81 pin 4. This modification is needed by the TLM in slot 10 of the top backplane of rack M102 (Specific Triggers Fired to Start Digitize DIGIMEM's). 4. If the TLM is not going to be used with a CBUS connection and you want the LED's to work then cut the trace going to U53 pin 12. 5. If the J4 connector outputs (GLOBAL TRIGGER, LATCHED TRIGGER) are going to be used then wire J8 pins 1 through 8 to J7 pins 1 through 8. 6. The full details of all the modifications required to make a TLM work in the LS mode are only included in a suplemental drawing with the TLM print set. 7. There are 3 types of TLM's: T ==> Transparent Mode, B ==> Bussed Mode, and LS ==> Latched Sum Mode. 8. In the LS Mode TLM the Data Latches and the Latched Sum are updated on the falling edge of the TLM Latch Clock; High ==> Follow, Low ==> Hold, Falling Edge ==> Latch. D.E. 31-AUG-1988