Non FSTD Cell Framework Scalers ----------------------------------- Rev. 6-MAY-1993 This file describes the L1 Framework scalers that are not part of FSTD Cells. It describes the clock and gate signals that control these scalers. VME Transfer: Wait Buffer, Wait DMA, Idle, Display M101 Slot 16 ------------------------------------------------------------------- This is a DBSC with CA=35. All 4 scalers have their clock signal inputs strapped together with no termination on any of them. All "Gate A" signal inputs are independent and do have terminators. Their is nothing connected to the "Gate B" inputs. VME Trans Prepare, Data Block Builder Busy, L1 in P1, L1 in P2 M101 Slot 15 ----------------------------------------------------------------------------- This is a DBSC with CA = 33. The first 2 scalers (Ch 1 and Ch2) have their clock inputs strapped together and are not terminated. Channels 1 and 2 have the "Gate A" inputs connected to the "Gate B" inputs with no terminators. Gate signals may enter in the "A" gate and be terminated at the "B" gate contacts on the backplane. The second 2 scalers (Ch3 and Ch 4) have their clock inputs strapped together and are not terminated. Channels 3 and 4 have the "Gate A" inputs connected to the "Gate B" inputs with no terminators. Gate signals may loop in an out the "A" and "B" gate backplane contacts. Beam Cross Num, Gated Beam Cross Num, L1 in P3, L1 in P4 M101 Slot 14 -------------------------------------------------------------------------- This is a DBSC with CA = 45. The first 2 scalers (Ch 1 and Ch2) have their clock inputs strapped together and are not terminated. Channels 1 and 2 have terminators on the "Gate A" inputs and nothing connected to the "Gate B" inputs. The second 2 scalers (Ch3 and Ch 4) have their clock inputs strapped together and are not terminated. Channels 3 and 4 have the "Gate A" inputs connected to the "Gate B" inputs with no terminators. Transfer Number, Start Digitize Number, L1 in P3, L1 in P4 M101 Slot 13 ---------------------------------------------------------------------------- This is a DBSC with CA = 43. The first 2 scalers (Ch 1 and Ch2) have terminators on their clock inputs and nothing on their Gate inputs. The second 2 scalers (Ch3 and Ch 4) have their clock inputs strapped together and are not terminated. Channels 3 and 4 have the "Gate A" inputs connected to the "Gate B" inputs with no terminators. Control Signals for the L1 per Bunch Scalers and the P% Gate inputs to the AND-OR Network and the Skip Beam Crossing inputs to the AND-OR Network -------------------------------------------------------------------------- A separate "special" CTMBD is installed in the bottom slot of rack M101. Only the Timing Signal section of this CTMBD is used (the CBus section is not used). This CTMBD provides the termination for the T&SS bus that feeds the normal MBD's in rack M101 and it provides a buffered copy of all 32 Framework Main Timing MTG timing signals. At this time 12 of the buffered timing lines are in use as described below: The 6 signals for the P% Gates are carried on individual cables from the CTMBD to the Gate A inputs of the L1 Triggers per Bunch DBSC's. In these DBSC's these signals loop from the Gate "A" contacts to the Gate "B" contacts. From the Gate "B" contact these P% Gate signals continue on another set of cables to the AND-OR Network input patch panel. Recall that the DBSC Gate inputs are low active (i.e. a low signal enables the DBSC to increment). Thus the P% Gate signals are connected to the DBSC's "up side down" so that they appear low active to the DBSC's and high active to the AND-OR network inputs. A buffered copy of the L1 Triggers per Bunch DBSC Clock signal comes out of the CTMBD and is carried on a cable to these DBSC's. It enters the clock input for Ch #3 or the Ch #4 of one of these DBSC's and on the DBSC card it loops to the other channel where it is again carried on cable to the next L1 per Bunch DBSC card. At the last "exit" there is a terminator instead of more cable. The three Skip Beam Crossing signals are carried on cable directly from the CTMBD to the input patch panel for the AND-OR Network. The Write A Pipe and the Read A Pipe signals are carried on cable directly form the CTMBD to the input patch panel for the AND-OR Network. Front-End Busy per Geographic Section M102 slot 18 in the FSTD backplane ---------------------------------------------------------------------------- This SBSC is used to count the number of beam crossings during which each Geographic Sectors Front-End Busy signal is active. This SBSC card is set up like a "normal" SBSC card in an FSTD cell (i.e. it receives the SBSC Common Increment Clock, T&SS Line #9, on specific backplane bus timing line #d, and it receives the SBSC Reset/Load, T&SS Line #10 on the specific backplane bus timing line #E). Recall that the other two "special" SBSC (the AND-OR Fired Count, and the Start Digitization Count) receive their Clock signal from a special source and that they receive it on backplane bus line timing line A. The gate control signal for this Front-End Busy per Geographic Section SBSC comes from the front panel output of the Busy Latched TLM module in M101. The cable on its way from the Busy Latched TLM module to the individual gate input connector on the rear of the SBSC goes through a "flip" by passing the signals through an intermediate connection (two standard flat cable connectors plugged into each other with AMP pins). By making the gate signals go through the above wiring the gate signals arrive at the SBSC with the proper polarity to enable the SBSC to increment when a Geographic Section is Busy, and in the proper order so that Geographic Sector #1 is on scaler #1 of the SBSC. This SBSC is setup in the "standard" way. Reset all the channels (by writing zero in the control registers) and then enable the external gate signals to control the individual scalers (write 170 in the control registers). Layout of the Non-FSTD Scalers in Rack M101 ------------------------------------------------- cf. file TRGSCAL:SCALER_ASSIGMENTS.TXT Setup of the Scalers in the Bottom of Rack M114 Foreign and Ours ------------------------------------------------------------------- Slot 19 CA=56 DBSC Foreign Scalers 4:1 Scaler #1 counts the number of beam crossings that we are into a Main Ring type 29 Cycle. This is a special DBSC channel with an External Hardware Reset Input. See the DBSC description file for details. This is Foreign Scaler #4. The special reset signal for scaler #1 comes on pair #17 on the cable from the M122 NIM to ECL for M114 scalers module. This is the top Lemo connector. Scaler #2, Foreign #3 is the Never Ever Reset Beam Crossing Number. Scaler #3, Foreign #2 is the BX Counts of MicroBlank. The Gate A control signal for scaler #3 comes on pair #11 on the cable from the M122 NIM to ECL for M114 scalers module the 7th from the top Lemo. Scaler #4, Foreign #1 is the BX Counts of MRBS_Loss. The Gate A control signal for scaler #4 comes on pair #12 on the cable from the M122 NIM to ECL for M114 scalers module the 6th from the top Lemo. I believe that all 4 of these scalers use the DBSC Increment Clock signal and that all 4 of their Clock inputs are strapped together without any terminators. The DBSC Increment Signal loops through this card and then goes down to Slot 12 i.e. Foreign 32:29. I believe that scalers 3 and 4 are controlled by their Gate A input which do have a 110 ohm terminator. Slot 12 CA=35 DBSC Foreign Scalers 32:29 Scaler #1, Foreign #32 is not used. Scaler #2, Foreign #31 is not used. Scaler #3, Foreign #30 is not used. Scaler #4, Foreign #29 is the BX count of MRBS_Loss .OR. MicroBlank. The Gate A control signal for scaler #4 comes on pair #10 on the cable from the M122 NIM to ECL for M114 scalers module the 8th from the top Lemo. All 4 of these scalers use the DBSC Increment Clock signal and all 4 of their Clock inputs are strapped together without any terminators. The DBSC Increment Signal loops through this card and then goes down to Slot 11 i.e. Foreign 36:33. All 4 of these scalers are controlled by their Gate A input which do have a 110 ohm terminator. Slot 11 CA=32 DBSC Foreign Scalers 36:33 Scaler #1, Foreign #36 is the BX count of MR Veto Cal Low. Scaler #2, Foreign #35 is the BX count of MR Veto Muon Low. Scaler #3, Foreign #34 is the BX count of MR Veot Cal High. Scaler #4, Foreign #23 is the BX count of MR Veto Muon High. All 4 of these scalers use the DBSC Increment Clock signal and all 4 of their Clock inputs are strapped together with a terminator on the output on the connector on the backplane. All 4 of these scalers are controlled by their Gate A input which do have a 110 ohm terminator. The Gate A control signals for these 4 scalers come on pairs #9:#6 on the cable from the M122 NIM to ECL for M114 Scalers Module. Pair #9 is the Cal_Low signal from the 9th from the top Lemo for Foreign scaler #36. Pair #6 is the Muon_High signal from the 12th from the top Lemo for Foreign Scaler #33. Slot 8 CA=23 DBSC Level 1.5 Cycle Count, Level 1.5 Potential Event Count, Level 0 Good Scalers #1, #2, and #3 have a terminator on there Clock Input and nothing on their Gate Inputs. Slot 7 CA=20 DBSC Level Zero Good per Bunch Scalers Bunches P5:P6 Skip Level 1.5, Data Block Builder Cycle Count. The clock lines for scalers #1 and #2 are strapped together. The gate lines for scalers #1 and #2 are looped in on Gate A and out on Gate B. Thus the Bunch Gates should be connected to the Gate A Inputs and the terminator put on the Gate B Input. Scalers #3 and #4 have a terminator on there Clock Input and nothing on their Gate Inputs. Slot 6 CA=17 DBSC Level Zero Good per Bunch Scalers Bunches P1:P4 The clock lines for all 4 scalers are strapped together. On all 4 scalers the gate lines are looped in on Gate A and out on Gate B. Thus the Bunch Gates should be connected to the Gate A Inputs and a terminator put on the Gate B Input. ++++++++++===========+++++==========++++==========++++==========+++========= Layout of the 24 scalers for Norm Amos and Luminosity Measurement ----------------------------------------------------------------- Rev 26-AUG-92 Twenty four Foreign DBSC Scalers will be provided for Norm Amos to use to measure Luminosity . These scalers will count 4 different quantities (supplied by L0) on a per bunch bases. These scalers will increment on a given beam crossing only if certain "Beam Quality" and "Live Crossing" conditions have been satisfied. A Specific Trigger is programmed to establish these "Live Crossing" conditions. Once this Specific Trigger is setup to provide this "Live Crossing" indicator it can not be used as a normal Specific Trigger to cause the L1 system to fire. Typical programming of this special Specific Trigger will be: And-Or Terms: +L0_Fast_Z_Good, -CALNE_PLS, -L1_DBL_BUFFERED, +Skip_One_BeamX, -MRBS_LOSS, -Micro_Blank. These And-Or Terms establish the "Beam Quality" conditions. In addition this special Specific Trigger will have the following "Disable" signals enabled: Global Disable (i.e. COOR Disable), L2 Disable, Front_End Busy Disable. These disable signals along with the "Beam Quality" And-Or Terms define the signal "Live Crossing". The Geographic Section Front-End Busy to Specific Triggers Disabled Lookup Memory for this special Specific Trigger is programmed to look at the same set of Geographic Section Front-End Busy signals as the other global acquisition physics triggers. Technical Note: The "Live Crossing" output signal from the FSTD card will be strobed by the Framework Main MTG signal #7 the And-Or Strobe. This will both validate the "Live Crossing" signal as a clock type signal for use by the DBSC's and will hold off any positive edges on this signal during L1.5 Decision Cycles. The 24 Foreign Scalers will be on 6 DBSC cards located in slots 13 through 18 in the lower backplane of rack M114. Each of the 6 DBSC's will be used to count the 4 quantities for a given P_Bunch number. The bottom DBSC in slot #13 with Card Address 38 will count the quantities for the P1 bunch. The top DBSC in slot #18 with Card Address 53 will count the quantities for the P6 bunch. The P1 through P6 Bunch Gate signal will connect to the GATE-A inputs of all 4 scalers on a given DBSC card. The quantities to be counted will be connected as "gate type signals" to the GATE-B inputs of 6 scales (one on each of the DBSC cards). This bussing is taken care of by cabling on the backplane. On a given beam crossing a given scaler will increment only if; it is the proper P%_Bunch, the quantity to be counted is sending its signal, and the special "Live Crossing" Specific Trigger fires. Functions needed by the Spec Trig for generating the "Live Crossing" signal 1. Use the And-Or Inputs 2. COOR Enable Disable 3. L2 Disable 4. Front-End Busy Disable 5. Generation of a "live crossing" signal as a special kind of Specific Trigger Fired. 6. Locking the normal FSTD output to the Start Digitization TLM at an ECL low. 7. Provide new FSTD outputs to take the special Spec Trig Fired to the 24 Luminosity DBSC's as a clock signal. Foreign Scalers #5 through #28 Layout of the Quantities to be counted in the 24 DBSC Channels ------------------------------------------------------------------ Foreign #8 Foreign #7 Foreign #6 Foreign #5 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 18 Qty_1,P6 Qty_2,P6 Qty_3,P6 Qty_4,P6 Card Adrs 53 Foreign #12 Foreign #11 Foreign #10 Foreign #9 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 17 Qty_1,P5 Qty_2,P5 Qty_3,P5 Qty_4,P5 Card Adrs 50 Foreign #16 Foreign #15 Foreign #14 Foreign #13 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 16 Qty_1,P4 Qty_2,P4 Qty_3,P4 Qty_4,P4 Card Adrs 47 Foreign #20 Foreign #19 Foreign #18 Foreign #17 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 15 Qty_1,P3 Qty_2,P3 Qty_3,P3 Qty_4,P3 Card Adrs 44 Foreign #24 Foreign #23 Foreign #22 Foreign #21 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 14 Qty_1,P2 Qty_2,P2 Qty_3,P2 Qty_4,P2 Card Adrs 41 Foreign #28 Foreign #27 Foreign #26 Foreign #25 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 13 Qty_1,P1 Qty_2,P1 Qty_3,P1 Qty_4,P1 Card Adrs 38 In the above layout sketch it is assumed that: Qty_1 is (Live_Crossing) * L0(0) per Bunch Qty_2 is (Live_Crossing) * L0(1) per Bunch Qty_3 is (Live_Crossing) * L0(2) per Bunch Qty_4 is (Live_Crossing) * L0(1) * Vertex(i) per Bunch I believe that L0(0) is just a beam crossing clock. I believe that L0(1) is the "slow" L0 one and only one vertex signal. I believe that L0(2) is just the Fast_Z_Good signal. I believe that L0(1) * Vertex(i) is the slow L0 one and only one vertex times some vertex within distance x of z=0 signal. Layout of the Backplane Signal Input Connector View from the Backplane Side ----------------------------------------------------------------------------- Scale #4 Scale #3 Scaler #2 Scaler #1 -------------- ------------- -------------- -------------- Clk,Gt-B,Gt-A Clk,Gt-B,Gt-A Clk,Gt-B,Gt-A Clk,Gt-B,Gt-A -------------- ------------- -------------- -------------- ST_30,Qty_4,P6 ST_30,Qty_3,P6 ST_30,Qty_2,P6 ST_30,Qty_1,P6 <--P6 ST_30,Qty_4,P5 ST_30,Qty_3,P5 ST_30,Qty_2,P5 ST_30,Qty_1,P5 <--P5 ST_30,Qty_4,P4 ST_30,Qty_3,P4 ST_30,Qty_2,P4 ST_30,Qty_1,P4 <--P4 / | | | | Clk 2 | | | | ST_30,Qty_4,P3 ST_30,Qty_3,P3 ST_30,Qty_2,P3 ST_30,Qty_1,P3 <--P3 ST_30,Qty_4,P2 ST_30,Qty_3,P2 ST_30,Qty_2,P2 ST_30,Qty_1,P2 <--P2 ST_30,Qty_4,P1 ST_30,Qty_3,P1 ST_30,Qty_2,P1 ST_30,Qty_1,P1 <--P1 / Clk 1 | | | | /|\ /|\ /|\ /|\ | | | | Qty_4 Qty_3 Qty_2 Qty_1 Modifications to the FSTD to use Specific Trigger #30 as a Live Crossing Signal Generator ------------------------------------------------------------ I will assume that Spec Trig #30 uses channel #3 on an FSTD card. Need to stop the Fired*Enab_3 signal from going to the Spec Trig Fired TLM card. Need to make 2 new copies of the Fired*Enab_3 signal to use as a clock signal by the 24 new scalers. Cut the Fired*Enab_3 signal which runs from U65-P3 to U84-P4. Cut it near the U65 end on the long trace which runs across the front of the card. At the U84 end of this cut signal the off card driver input signal will be left to float to a good ECL low (i.e. this Spec Trig Fired will never reach the Start Digitize TLM). At the U65 end this cut signal will be connected to 2 new off card drivers with will drive this signal as the clock signals to the 24 Foreign DBSC scalers. The drivers which are used as the 2 new off card drivers are the driver for the AO_Fired_3 signal and the AO_Fired_4 signal. These signals are not used off card so we may steel their drivers. To free the AO_Fired_3 off card driver, cut the U65-P14 to U83-P4 trace in its short vertical section where it leaves U65 before it starts its long horizontal run. To free the AO_Fired_4 off card driver, cut the U66-P14 to U83-P7 trace in its short vertical section where it leaves U65 before it starts its long horizontal run. Now connect the Fired*Enab_3 signal to the AO_Fired_3 off card driver by installing a 110 ohm resistor (back terminator) between the via near U65-P3 and the via that begins the run to U83-P4. Now connect the Fired*Enab_3 signal to the AO_Fired_4 off card driver by installing a 110 ohm resistor (back terminator) between the via near U65-P3 and the via that begins the run to U83-P7. Now the output connector J4 pins 5,6 which had been Fired*Enab_3 will always be ECL low and will continue to connect to the Spec Trig #30 input of the Start Digitize TLM. Now the output connector J4 pins 13,14 and 15,16 which had been AO_Fired_3 and AO_Fired_4 will instead drive off card the Fired*Enab_3 signal. This will connect to the 24 Foreign Scaler clock inputs. Note: Because this card was "designed" with the terminators at the driving end of the Fired*Enab_% signals and the AO_Fired_% signals it will be necessary to use series terminators where the new outputs are generated for the Fired*Enab_3 siganl to keep the 24 Foreign scalers from seeing rough clock edges and counting wrong. Setup of the 6 DBSC Cards for Foreign Scalers #5 through #28 ----------------------------------------------------------------- Foreign #8 Foreign #7 Foreign #6 Foreign #5 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 18 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 53 Terminate all Gate_B Inputs. Bus together all Clock Uses P_Gate_6. Inputs and terminate near Ch#1. Foreign #12 Foreign #11 Foreign #10 Foreign #9 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 17 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 50 All Gate_B Inputs are open. Bus together all Clock Inputs. Uses P_Gate_5. Foreign #16 Foreign #15 Foreign #14 Foreign #13 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 16 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 47 All Gate_B Inputs are open. Bus together all Clock Inputs. Uses P_Gate_4. Foreign #20 Foreign #19 Foreign #18 Foreign #17 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 15 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 44 All Gate_B Inputs are open. Bus together all Clock Uses P_Gate_3. Inputs and terminate near Ch#1. Foreign #24 Foreign #23 Foreign #22 Foreign #21 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 14 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 41 All Gate_B Inputs are open. Bus together all Clock Inputs. Uses P_Gate_2. Foreign #28 Foreign #27 Foreign #26 Foreign #25 DBSC Ch #1 DBSC Ch #2 DBSC Ch #3 DBSC Ch #4 Slot 13 Bus together all Gate_A Inputs and terminate near Ch#4. Card Adrs 38 All Gate_B Inputs are open. Bus together all Clock Inputs. Uses P_Gate_1.