LOCATION OF THE DATA FROM THE FSTD SCALERS ========================================== SPECIFIC TRIGGERS 1 THROUGH 16 ------------------------------ MOTHER BOARD ADDRESS 132 FSTD CHANNEL FIRED FSTD CHANNEL ENABLED CARD CARD FUNCTION ADDRESS FUNCTION ADDRESS SPCF ADRS FSTD ADRS DBSC PREVIOUS CURRENT PREVIOUS CURRENT TRIG OF CHAN OF CHAN CROSSING CROSSING CROSSING CROSSING NUMB FSTD NUMB DBSC NUMB LSB MSB LSB MSB LSB MSB LSB MSB ---- ---- ---- ---- ---- --- --- --- --- --- --- --- --- 1 1 1 3 1,2 1 - 5 129-133 9 - 13 137-141 2 1 2 3 3,4 17 - 21 145-149 25 - 29 153-157 3 1 3 2 1,2 1 - 5 129-133 9 - 13 137-141 4 1 4 2 3,4 17 - 21 145-149 25 - 29 153-157 5 5 1 7 1,2 1 - 5 129-133 9 - 13 137-141 6 5 2 7 3,4 17 - 21 145-149 25 - 29 153-157 7 5 3 6 1,2 1 - 5 129-133 9 - 13 137-141 8 5 4 6 3,4 17 - 21 145-149 25 - 29 153-157 9 9 1 11 1,2 1 - 5 129-133 9 - 13 137-141 10 9 2 11 3,4 17 - 21 145-149 25 - 29 153-157 11 9 3 10 1,2 1 - 5 129-133 9 - 13 137-141 12 9 4 10 3,4 17 - 21 145-149 25 - 29 153-157 13 13 1 15 1,2 1 - 5 129-133 9 - 13 137-141 14 13 2 15 3,4 17 - 21 145-149 25 - 29 153-157 15 13 3 14 1,2 1 - 5 129-133 9 - 13 137-141 16 13 4 14 3,4 17 - 21 145-149 25 - 29 153-157 SPECIFIC TRIGGERS 17 THROUGH 32 ------------------------------- MOTHER BOARD ADDRESS 68 FSTD CHANNEL FIRED FSTD CHANNEL ENABLED CARD CARD FUNCTION ADDRESS FUNCTION ADDRESS SPCF ADRS FSTD ADRS DBSC PREVIOUS CURRENT PREVIOUS CURRENT TRIG OF CHAN OF CHAN CROSSING CROSSING CROSSING CROSSING NUMB FSTD NUMB DBSC NUMB LSB MSB LSB MSB LSB MSB LSB MSB ---- ---- ---- ---- ---- --- --- --- --- --- --- --- --- 17 17 1 19 1,2 1 - 5 129-133 9 - 13 137-141 18 17 2 19 3,4 17 - 21 145-149 25 - 29 153-157 19 17 3 18 1,2 1 - 5 129-133 9 - 13 137-141 20 17 4 18 3,4 17 - 21 145-149 25 - 29 153-157 21 21 1 23 1,2 1 - 5 129-133 9 - 13 137-141 22 21 2 23 3,4 17 - 21 145-149 25 - 29 153-157 23 21 3 22 1,2 1 - 5 129-133 9 - 13 137-141 24 21 4 22 3,4 17 - 21 145-149 25 - 29 153-157 25 25 1 27 1,2 1 - 5 129-133 9 - 13 137-141 26 25 2 27 3,4 17 - 21 145-149 25 - 29 153-157 27 25 3 26 1,2 1 - 5 129-133 9 - 13 137-141 28 25 4 26 3,4 17 - 21 145-149 25 - 29 153-157 29 29 1 31 1,2 1 - 5 129-133 9 - 13 137-141 30 29 2 31 3,4 17 - 21 145-149 25 - 29 153-157 31 29 3 30 1,2 1 - 5 129-133 9 - 13 137-141 32 29 4 30 3,4 17 - 21 145-149 25 - 29 153-157 WIRING BETWEEN THE FSTD and DBSC ************************************ The outputs of the FSTD gate control signals going to the DBSC are active HIGH i.e. they go HIGH when the DBSC should be incrementing. The Gate Inputs of the DBSC card are active LOW i.e. the counter can only increment when the Gate Input is LOW and is inhibited from incrementing when the Gate Input is HIGH. The default state of the DBSC Gate Inputs is LOW, thus enabling the counters to increment. To properly control the DBSC, the gate control signals from the FSTD must be inverted before connection to the DBSC. Each of the 4 channels on a DBSC card has its own serarate Clock Input connection. For their application in the FSTD cell all 4 Clock Inputs on the DBSC card will be wired together using the vias for the terminator resistors for the Clock Inputs (NO terminators are used). Then to bring the DBSC Increment Clock fromm the TSS Bus to the DBSC only one patch cord is used between TSS Bus Signal D on pins 81 and 82 to the DBSC channel 4 Clcok Input on pins 25 and 26. FSTD to DBSC Patch Cords -------------------------- FSTD DBSC FSTD FUNCTION DBSC CHANNEL CONNECTION CONNECTION --------------- -------------- ---------- ---------- CH #1 FIRED UPPER DBSC CH #1 3&4 UPPER 3&4 CH #1 ENABLED UPPER DBSC CH #2 27&28 UPPER 9&10 CH #2 FIRED UPPER DBSC CH #3 9&10 UPPER 15&16 CH #2 ENABLED UPPER DBSC CH #4 33&34 UPPER 21&22 CH #3 FIRED LOWER DBSC CH #1 15&16 LOWER 3&4 CH #3 ENABLED LOWER DBSC CH #2 39&40 LOWER 9&10 CH #4 FIRED LOWER DBSC CH #3 21&22 LOWER 15&16 CH #4 ENABLED LOWER DBSC CH #4 45&46 LOWER 21&22 FSTD CONNECTOR J2 ------------------ ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 3 FSTD CH#1 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF1 4 FSTD CH#1 FIRED GATE SIGNAL TO DBSC Inverted ISTF1 5 SPARE Non-Inverted NSPARE 6 SPARE Inverted ISPARE 7 SPARE Non-Inverted NSPARE 8 SPARE Inverted ISPARE 9 FSTD CH#2 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF2 10 FSTD CH#2 FIRED GATE SIGNAL TO DBSC Inverted ISTF2 11 SPARE Non-Inverted NSPARE 12 SPARE Inverted ISPARE 13 SPARE Non-Inverted NSPARE 14 SPARE Inverted ISPARE 15 FSTD CH#3 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF3 16 FSTD CH#3 FIRED GATE SIGNAL TO DBSC Inverted ISTF3 17 SPARE Non-Inverted NSPARE 18 SPARE Inverted ISPARE 19 SPARE Non-Inverted NSPARE 20 SPARE Inverted ISPARE 21 FSTD CH#4 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF4 22 FSTD CH#4 FIRED GATE SIGNAL TO DBSC Inverted ISTF4 23 SPARE Non-Inverted NSPARE 24 SPARE Inverted ISPARE 25 SPARE Non-Inverted NSPARE 26 SPARE Inverted ISPARE 27 FSTD CH#1 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE1 28 FSTD CH#1 ENABLED GATE SIGNAL TO DBSC Inverted ISTE1 29 SPARE Non-Inverted NSPARE 30 SPARE Inverted ISPARE 31 SPARE Non-Inverted NSPARE 32 SPARE Inverted ISPARE 33 FSTD CH#2 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE2 34 FSTD CH#2 ENABLED GATE SIGNAL TO DBSC Inverted ISTE2 35 SPARE Non-Inverted NSPARE 36 SPARE Inverted ISPARE 37 SPARE Non-Inverted NSPARE 38 SPARE Inverted ISPARE 39 FSTD CH#3 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE3 40 FSTD CH#3 ENABLED GATE SIGNAL TO DBSC Inverted ISTE3 41 SPARE Non-Inverted NSPARE 42 SPARE Inverted ISPARE 43 SPARE Non-Inverted NSPARE 44 SPARE Inverted ISPARE 45 FSTD CH#4 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE4 46 FSTD CH#4 ENABLED GATE SIGNAL TO DBSC Inverted ISTE4 47 SPARE Non-Inverted NSPARE 48 SPARE Inverted ISPARE 49 SPARE Non-Inverted NSPARE 50 SPARE Inverted ISPARE DBSC CONNECTOR J2 ------------------ ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 3 Gate A Scaler Number 1 Non-Inverted NGAS1 4 Gate A Scaler Number 1 Inverted IGAS1 5 Gate B Scaler Number 1 Non-Inverted NGBS1 6 Gate B Scaler Number 1 Inverted IGBS1 7 Clock Scaler Number 1 Non-Inverted NCLS1 8 Clock Scaler Number 1 Inverted ICLS1 9 Gate A Scaler Number 2 Non-Inverted NGAS2 10 Gate A Scaler Number 2 Inverted IGAS2 11 Gate B Scaler Number 2 Non-Inverted NGBS2 12 Gate B Scaler Number 2 Inverted IGBS2 13 Clock Scaler Number 2 Non-Inverted NCLS2 14 Clock Scaler Number 2 Inverted ICLS2 15 Gate A Scaler Number 3 Non-Inverted NGAS3 16 Gate A Scaler Number 3 Inverted IGAS3 17 Gate B Scaler Number 3 Non-Inverted NGBS3 18 Gate B Scaler Number 3 Inverted IGBS3 19 Clock Scaler Number 3 Non-Inverted NCLS3 20 Clock Scaler Number 3 Inverted ICLS3 21 Gate A Scaler Number 4 Non-Inverted NGAS4 22 Gate A Scaler Number 4 Inverted IGAS4 23 Gate B Scaler Number 4 Non-Inverted NGBS4 24 Gate B Scaler Number 4 Inverted IGBS4 25 Clock Scaler Number 4 Non-Inverted NCLS4 26 Clock Scaler Number 4 Inverted ICLS4 17 MAY 1988