Three groups of Thirty Six Scalers -------------------------------------- Original Rev. 29-SEPT-1995 Current Rev. 25-OCT-1995 The cards to implement the 3 groups of 36 scalers will be mounted in a 20 slot Framework style backplane. The backplane used has 14 slots with just the CBus bussed and and a separate section of 6 slots with just the CBus bussed. All other pins in this backplane are free. Layout of the 36 Bunch Scaler Backplane M125 Solder Side View -------------------------------------------------------------------- J4 J3 J2 J1 -------------------------------------------- 20. | ======== ======== ======== ======== | | |||||||| | 19. | ======== ======== ======== ======== | BBB Adrs = 88 to L15CT | |||||||| | Fanout Master Clk to MTG's 18. | ======== ======== ======== ======== | | |||||||| | 17. | ======== ======== ======== ======== | BBB Adrs = 96 to the | |||||||| | 36 Bunch Scalers & MTG's 16. | ======== ======== ======== ======== | | |||||||| | 15. | ==TERM== ======== ======== ======== | | | 14. | ======== ======== ======== ======== | MTG CA=56 Scan Reset & | |||||||| | Load, Com Clk Gates 13. | ======== ======== ======== ======== | | |||||||| | 12. | ======== ======== ======== ======== | SBSC CA=10 Lum 0:31 | |||||||| | 11. | ======== ======== ======== ======== | SBSC CA=20 P Loss 0:31 | |||||||| | 10. | ======== ======== ======== ======== | SBSC CA=30 /P Loss 0:31 | |||||||| | 9. | ======== ======== ======== ======== | | |||||||| | 8. | ======== ======== ======== ======== | MTG CA=50 Bunches 0:31 | |||||||| | 7. | ======== ======== ======== ======== | | |||||||| | 6. | ======== ======== ======== ======== | MTG CA=53 Bunches 32:52 | |||||||| | 5. | ======== ======== ======== ======== | | |||||||| | 4. | ======== ======== ======== ======== | SBSC CA=13 Lum 32:52 | |||||||| | 3. | ======== ======== ======== ======== | SBSC CA=23 P Loss 32:52 | |||||||| | 2. | ======== ======== ======== ======== | SBSC CA=33 /P Loss 32:52 | |||||||| | 1. | ==Term== ======== ======== ======== | |__________________________________________| J4 J3 J2 J1 Rear "Solder Side" View Cabling of the M125 Backplane _____________________________ The CBus #3 cable (from the COMINT in M114) plugs into J4 at Slot 20. The J4 on Slots 15:20 are bussed together. This connects the COMINT CBus #3 to the "COMINT Side" CBus connector of both of the BBB cards (Slots 17, and 19). This bussing also terminates the CBus #3 from the COMINT with a terminator at J4 Slot 15. Plugged into J3 Slot 19 is the CBus cable that goes to the L15CT MTG card file. The BBB that is plugged into slot 19 also provides the fanout for the Master clock signals that drive the L15CT MTG and the two MTG's that control the 36 bunch scalers. This is handled in the following way: The 26.552 MHz Master Clock is is received on the first 3 pairs of J2 and then terminated. These are the BBB signal paths that would normally service T&SS Bus Ch# 1, 2, and 3. The 26.552 MHz signal is driven out on the first 3 pairs of J1. One copy of this signal goes to the L15CT MTG, another copy goes to the two MTG's for the 36 bunch scalers, and the third output is for monitoring. The once per turn marker from the Master Clock is is received on pairs 7, 8, and 9 of J2 and then terminated. These are the BBB signal paths that would normally service T&SS Bus Ch# 7, 8, and 9. The once per turn marker signal is driven out on pairs 7, 8, and 9 of J1. One copy of this signal goes to the L15CT MTG, another copy goes to the two MTG's for the 36 bunch scalers, and the third output is for monitoring. Plugged into J3 Slot 17 is the short CBus cable that goes to J4 Slot 14 i.e. this is the CBus that will operate the SBSC and the MTG's for the 36 bunch scaling. The J4 connectors on Slots 1 through 14 are bussed together to carry this Back Plane CBus for the 36 Bunch Scalers and their MTG's. Connector J4 at Slot #1 holds the terminator for this backplane CBus. The output signals from the MTG in Slot 8 are connected to the Gate Inputs of the SBSC's in Slots 10, 11, and 12. This is accomplished by a ribbon cable with 5 connectors on it that plugs into J2 of slots 8, 10 ,11, 12, and 13. Slot 13 is used for the terminator for these MTG output signals. The output signals from the MTG in Slot 6 are connected to the Gate Inputs of the SBSC's in Slots 2, 3, and 4. This is accomplished by a ribbon cable with 5 connectors on it that plugs into J2 of slots 1, 2, 3, 4, and and 6. Slot 1 is used for the terminator for these MTG output signals. MTG in Slot #14 _______________ The MTG in Slot #14 (CA=56) is used to control the loading of the SBSC scaler output registers. Typically the output registers are loaded about once every 5 seconds when TCC fills its Monitor Pool. The steps in loading the SBSC scaler output registers are the following: 1. TCC sets the output of Slot #14 MTG Channel #1 (FA=0) HIGH This MTG channel uses a normal Bit2 type PAL. TCC keeps this channel set HIGH for at least 25 usec. This channel may be kept HIGH for as long as TCC wants but it must be high for at least 25 usec and then it must be returned LOW before the output registers can be loaded again. 2. This long asynchronous HIGH from Channel #1 is connected to the ExtBit control input of Channel #2. Channel #2 uses a Bit8 type PAL (direct input test trigger type PAL). This PAL synchronizes the signal from Channel #1 to the once per turn clock and makes an output that remains HIGH for one turn. The output from Channel #2 is used as a control input for Channels #3, #6, #7, and #8. The one turn long control output from Channel #2 is feed to the ExtEnb control input of Channel #3 and the inverted form of the output from Channel #2 is feed to the ExtEnb control input of Channels #6, #7, and #8. 3. The ROM pattern for Channel #3 contains the 2 usec long Scan Reset & Load signal for the SBSC Scalers. This MTG channel uses a Bit2 type of PAL and is setup to output its ROM pattern only when its ExtEnb control input is HIGH. Thus, during a turn when the output from Channel #2 is HIGH the SBSC's will be sent a Scan Reset & Load. The Scan Reset & Load output from Channel #3 is connected to the SBSC's input for this signal which is backplane CBus Timing Signal #E. The SBSC's receive their Scan_Reset_&_Load signal on their CBus Timing Signal E connector. So the output from Ch #3 of the MTG in Slot 14 is routed to the backplane CBus that covers Slots 1 through 14. 4. Channels #6, #7, and #8 of the MTG in Slot #14 are used to gate off the scaler increment signals that come from the Level 0 electronics. The signals from the Level 0 electronics can pass through these MTG channels only if the one turn long control signal from Channel #2 is LOW. The outputs from these three MTG channels are connected to the SBSC Common Clock Inputs. The signals comming from the L0 electronics are normally at a LOW voltage level and pulse HIGH for 100 nsec. The SBSC Common Clock input needs to see a signal that is normally voltage HIGH and pulses LOW. This lets the SBSC increment on the leading edge of the signal comming from L0. When the MTG channels that process the L0 signals are disabled (to allow the Scan Reset & Load operation to take place) they go to a voltage LOW. So putting this all together we see that we want to have an inversion between the output of these MTG channels and the Common Clock inputs to the SBSC's. The SBSC card has two ways of receiving its Common Increment Clock: either via CBus Timing Signal D or via the first pair of pins on J3. The AND-OR Fired SBSC's and the Start Digitization counter SBSC's receive their Common Increment Clock on the first pair of pins on J3. The SBSC's used in the 36 bunch scaler card file will also use the first pair of pins on J3 to receive the Common Increment Clock. Slot #14 MTG Channel #6 controls the Level 0 Luminosity signal, Channel #7 controls the P Loss signal and Channel #8 controls the /P Loss signal. Channels #6, #7, and #8 all use Bit2 type PALs. The only ROM patters needs for the MTG in Slot #14 are for Channel #2 (the one turn long control signal) and for Channel #3 the Scan Reset & Load signal. Details about the Scan Reset & Load signal: On the LS7060 integrated circuit pin #12 is the Scan Reset & Load input and is active LOW. This pin can be driven LOW by either a CBus write to FA=64 or by taking CBus Timing Signal "E" HIGH. The Scan Reset & Load signal must be in its active state for a minimum of 1 usec. The counters must not have incremented for a minimum of 2 usec before the Scan Reset & Load signal is put in its active state. It takes the chip 250 nsec to recover from being told to Scan Reset & Load. What SBSC Counts What ? -------------------------------------------------------------- SBSC Channel W0:W31 SBSC's W32:W63 SBSC's Number Function Function ------- ---------------------------- ------------------------------- 1 Window W0 looking at P1 Window W32 looking at EN9 2 Window W1 looking at P2 Window W33 looking at EN10 3 Window W2 looking at P3 Window W34 looking at ES11 4 Window W3 looking at P4 Window W35 looking at EN12 5 Window W4 looking at P5 Window W36 looking at P25 6 Window W5 looking at P6 Window W37 looking at P26 7 Window W6 looking at P7 Window W38 looking at P27 8 Window W7 looking at P8 Window W39 looking at P28 9 Window W8 looking at P9 Window W40 looking at P29 10 Window W9 looking at P10 Window W41 looking at P30 11 Window W10 looking at P11 Window W42 looking at P31 12 Window W11 looking at P12 Window W43 looking at P32 13 Window W12 looking at EN1 Window W44 looking at P33 14 Window W13 looking at EN2 Window W45 looking at P34 15 Window W14 looking at EN3 Window W46 looking at P35 16 Window W15 looking at EN4 Window W47 looking at P36 17 Window W16 looking at ES5 Window W48 looking at EN13 18 Window W17 looking at EN6 Window W49 looking at EN14 19 Window W18 looking at P13 Window W50 looking at EN15 20 Window W19 looking at P14 Window W51 looking at EN16 21 Window W20 looking at P15 Window W52 looking at ES17 22 Window W21 looking at P16 Window W53 looking at EN18 23 Window W22 looking at P17 Not Used Gate Locked DISABLED 24 Window W23 looking at P18 Not Used Gate Locked DISABLED 25 Window W24 looking at P19 Counts P1 in 6x6 operation 26 Window W25 looking at P20 Counts P2 in 6x6 operation 27 Window W26 looking at P21 Counts P3 in 6x6 operation 28 Window W27 looking at P22 Counts P4 in 6x6 operation 29 Window W28 looking at P23 Counts P5 in 6x6 operation 30 Window W29 looking at P24 Counts P6 in 6x6 operation 31 Window W30 looking at EN7 Counts Accelerator TURNS 32 Window W31 looking at EN8 Gate is always ENABLED, sum check Recall Details about the Operation of the SBSC Cards -------------------------------------------------------- The Common Clock signal is received on the SBSC and fanned out to all 32 scalers without inversion. The SBSC Common Clock input is connected to pin #1 on the LS7060 integrated circuits. If the SBSC gates are enabled then the scaler will increment on the falling (i.e. High to Low transition) of the SBSC's Common Clock Input. So for this application we will want the Common Clock signal to remain HIGH most of the time and to pulse low to increment the enabled scalers. The "gate" of each scaler is pin #2 of the LS7060 integrated circuit. This pin must be LOW to enable the scaler to increment on the falling edge of the SBSC Common Clock. Pin #2 will be LOW if either: The control register gate bit is set HIGH or the external gate signal input is set LOW. So for this application the control register gate bit will be set LOW and then when the external gate input is LOW the scaler will be enabled to increment. Note: All SBSC's should have 74ALS541's driving their GATE LED display. With this driver an LED is illuminated when its gate is enabled, i.e. LED "on" implies this scaler can increment. The pinout of the External Gate inputs is backwards, i.e. the gate input for scaler #1 has the high pin numbers and the gate input for scaler #32 has the low pin numbers. Recall the Layout of the Cards Used the 36 Bunch Scaler Backplane ----------------------------------------------------------------- BBB - Bus Buffer Board SBSC Card Back To To Ext Plane MBD MBD Gates CBus _____________________________ _____________________________ ||___| |___| |___| |___| | ||___| |___| |___| |___| | | | | | | | | | | | | ^ V ^ V | | v ^ | | | | | | | | v | | |---<--| |---<--| | | Gate CBus | | TSS CBus | | Control | | | | | | | | | | | | | ----------------------------- ----------------------------- Front Top View Front Top View MTG Card Back TSS Plane OUTPUT CBUS _____________________________ ||___| |___| |___| |___| | | | | | | ^ ^ | | v | | | | ^ | | | | | __________ | || | | ----------------------------- EXT INPUT Front Top View What does the Gate timing look like for the SBSC's ?? _____________________________________________________ Slightly Edited Note from Dan Owen Fermi Lab , 5-OCT-1995 The outcome of the 36x36 meeting with Mike Martens is that we will have a total of 54 (x3) scalers to record the Prot halo, Anti prot halo, and Fast Z lum. The 54 "time windows" consist of 3 batches of 18. Within a batch of 18, 12 will be centered on the bunch crossing times for that batch; these will be followed by 6 "empty" windows. The spacing between windows is 21 buckets except for a singe 14 bucket spacing between two of the "empty windows in each batch. Below I attempt to indicate the time distribution of a complete revolution of the 36 bunches. I have put the "short spacing" between the 5th and 6th empty windows but it has not yet been decided if this is where it will go (but that is the most likely spot). f f f f f f f f f f f f e e e e e e f f f f f f f f f f f f e e e e e e f f f f f f f f f f f f e e e e e e 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 Now, 13-OCT-1995, this all changed. Now they say that the 5th of the 6 empty windows will be the short window. So the empty windows need to be: 21 21 21 21 14 21 ALL details about the MTG PROM's for this 36 Bunch Test Scalers are in the file PROMs_for_36_Bunch_Test_Scalers.Txt . TRICS initialization of the 36x36 Scaler Crate ---------------------------------------------- Note that TRICS_INIT_AUXI is used to override the default settings listed below. All 3 MTG cards are initialized to sweep the PROM using "standard" window with a preset value of 100 and a terminal count of 651 (and thus will require reprogramming to account for cable delays, cf. the ERPB MTG). All MTG control registers will be programmed with 36 = and should thus be reprogrammed with 22 = The Channels of the Load Control MTG will receive the following default settings ch # 1 = tss_Force_Low = 9 ch # 2 = init_dirin_mtg_ch = 10 ch # 3 = tss_ROM_Gated = 4 ch # 6,7,8 = tss_Ext_Gated = 2 All channels of both Gate Control MTGs will get the following default setting ch # 1:32 = tss_Sel_Rom = 12 For all 3 sets of SBSC cards, all control registers (i.e. all channels) will receive the following default setting: First 0 is loaded to reset the channels; then 170 is loaded to enable all four channels controlled by each SBSC control register.