To: L2 System; Dave, Jan, Jim Calorimeter; Dean Muon; Mike and Kamel Central; Marvin Online System; Bruce Offline; Serban Please read and send your comments to me about the following proposed change to the 16 bit "Event Number" which is carried on the Trig-Acq-Sync cables to the various Front-End System and a change in the source of the "Trigger Number" in the Head Bank. Also will someone from each of the 3 front-end systems (Calo, Muon, Central) let me know which edge of which signal they use to latch the 16 bit number carried on the Trig-Acq-Sync cables ( e.g. leading or trailing edge of either Start Digitize or Hold Transfer). Thanks, Dan +*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+* Proposed Modification of the 16 bit Number Carried on the Trigger-Acquisition-Synchronization Cables to the Front-End Systems --------------------------------------------------------------------- Rev. 7-MAY-1992 As I expect you have heard, in order to operate with the L1.5 Trigger it will be necessary to modify the content of the "16 bit Event Number" that is sent over the Trigger-Aquisition-Synchronization cables from the Trigger Framework to the various Front-End Systems and to the L2 Supervisor and L2 Sequencer. Because these 16 signals are going to have a new definition and because there has been some confusion in the past about their name (e.g. trigger number vs event number) I propose that we give them a new name: "TAS Number". The 16 bit TAS Number will consist of two parts: The high order 12 bits of the TAS Number will come from the lowest 12 bits of the 40 bit "Start Digitization Count" scaler. The lowest 4 bits of the TAS Number will come from the lowest 4 bits of the 40 bit "Transfer Count" scaler. _________________________________________________ | | | 16 Bit TAS Number | | -------------------- | | | | Carried on Trig-Acq-Sync Cables to Front-Ends | | and supplied to the L2 Super and L2 Sequencer | | | | MSB LSB | | bit 15 ... bit 4 bit 3 ... bit 0 | |_______________________________________________| ___________________ _________________ ^ ^ | | +--<--+ +-----<-------<------+ | | _______+_______ ______+_______ ______________________________________ ____________________________________ | | | | | bit 39 .. bit 12 bit 11 .. bit 0 | | bit 39 .. bit 4 bit 3 .. bit 0 | | MSB LSB | | MSB LSB | | | | | | 40 bit Start Digitization Count | | 40 bit Transfer Count | | --------------------------------- | | ----------------------- | |____________________________________| |__________________________________| The Start Digitization Count scaler will increment each time the Trigger Framework sends out Start Digitization signals to the Front-End Systems. The Transfer Count scaler will increment only when an event is actually transfered to the Level 2 system (i.e. a Level 1 Specific Trigger fires that does not need L1.5 confirmation or else a Level 1 Specific Trigger fires that does need L1.5 confirmation and it is confirmed by L1.5). The Transfer Count will NOT increment in response to triggers that are rejected at Level 1.5 (i.e. triggers that did not result in the transfer of an event to the L2 system). As in the current operation, these scalers will increment after the conditions described above take place in preparation for the next time that a trigger fires. The TAS Number, which is carried on the Trig-Acq-Sync cables, will be incorporated in: the Crate Headers, the Crate Trailers, and in the Sequencer Trailers. The same TAS number that is sent to the Front-End systems is also supplied to both the L2 Supervisor and the L2 Sequencer for use in their readout control operations. As part of the readout process the L2 system checks each event to verify that all 16 bits of the TAS Number in all the Crate Trailers and in all the Sequencer Trailers do match. The "Trigger Number" that is put in the Head Bank will be all 40 bits of the "Transfer Count" scaler. Thus the TAS Number in the Crate Header, the Crate Trailer, the Sequencer Trailer, and as used by the L2 Supervisor and L2 Sequencer will match the Head Bank Trigger Number in the lowest 4 bits only.