This started as a list of things we are planning/hoping to do during the shutdown which begins on July 20th Now it has become the general "to do" work list. ------------------------------------------------------------ Rev. 31-MAR-1993 xx 1. Bring enough ECO'd CAT3 cards to replace some of the non-ECO'd CAT3 cards currently installed in Tier 3. The cards we would like/need to replace are at least: EM 1st lookup (the one that feeds IMLRO/T4) HD 1st lookup (the one that feeds IMLRO/T4) Total 1st lookup ??? EM 2nd lookup ??? HD 2nd lookup ??? Total 2nd lookup ??? (broken some other way anyway) In the fullness of time we need to replace them all with good tested ECO'd CAT3 cards. The CAT3 cards at MSU are not tested. xx 2. Fix the Data Block Builder so that it stops as soon as possible. xx 3. Bring some extra good, tested CTFE cards to use as spares. xx 4. Fix the ETA -9, PHI 8 HD trigger tower (CTFE problem) xx 5. Bring good, cut, installable C channel for M110 (and M111/M112?). xx 6. Bring T-channel for the top of M110/111/112 ??? xx 7. See if we can fix 2nd lookup. Maybe just doing (1) above does it. It was a CTMBD TSS wiring problem, i.e. no 2nd LU in one Tier 1 crate. xx 8. CA bit of value 16 on M109 T2 has a problem that must be fixed. No it was just CA switches set wrong. ?? 9. EM Ref Set 3 ETA = +1..+4, PHI = 1..8 is broken and must be fixed. During the most recent tests this was all OK 10-SEPT-92 ?? 10. See if we can find an obvious problem on the FMLN which would cause the "extra increment" error. Look @ decoded FA 4 and 5 lines. This problem was with the 1st FMLN. It tests all OK at MSU. The 2nd FMLN is all OK at D0 Hall. Have not yet "retested" the 1st FMLN at D0 Hall after it was checked at MSU. xx 11. Fix power contactor for M107. xx 12. Bring spare contactor box to Fermi and install. 13. Switch for 68K terminal to go between 68K and terminal server. xx 14. More Panduit cover. It is @ MSU in the Leo Memorial Room. xx 16. Investigate and repair the problem with the Front-End Busy per Geographic Section SBSC scaler for Geographic Section #2. repaired about 1st of OCT. Broken 64 conductor cable, Not connector. xx 17. Modify the TLM card for Front-End Bussies to bring out the Front-End Busy for Geo Section #1 i.e. the COMINT Card. Use this for the Double Buffer Full signal to the And-Or Network and to gate the gated beam crossing scaler. xx?? 18. Find and remove all epoxy on the Rack M114 backplane connectors. xx 19. "Repair" the straping on the L15 Control MTG. Some straping is setup as temporary wires on the connectors; move it to the headers. xx 20. Pull the cable inverter in the L15 cables from the front of the L15 patch panel to the rear of the L15 patch panel. xx 21. In the L1 Main Timing MTG rename the "Last 4 Ticks" signal to the "And-Or SBSC Clock" signal and put it under proper control of the L15 Stretch signal. Edit Trics_Init_Auxi, L15_Obey, and L15 Ignore to control the PAL for this newly named And-Or SBSC Clock signal. Done 1-OCT-1992 xx 22. Fix the Geo Section #21 problem that it has when running with L15. xx 23. Fix the problem that Spec Trig #1 has when trying to run L15. xx 24. Fix the problem with the Framework Expansion final Cal Trig readout: L0 readout problem, Px-Py readout problem, EM Et - HD Et readout problem. Philippe fixes it. This is a Latch-Shift signal and must be gated by Front-End Busy and Clear Most Recent. xx 25. Work on BLS cables, BLS trigger hybrids, and any CTFE analog problems. xx 26. Setup the 24 foreign scalers as defined in the Grannis and Amos notes. Pull apart Spec Trig #30 or else thing about a cleaver way to use the And-Or part of Spec Trig #31 as the clock for these 24 scalers. xx 27. Change how the Write A/B control line switches state when there is a L15 reject so that L15 information is not lost. See details in the notebooks. xx 28. Get Power Pan PDS numbers and brick SN's. 29. Make a diagram of all the current single signals. xx 30. CTFE PROM tests of the new PROM's in eta 7 and 8 HD. xx 31. Install the last of the L15 PAL's. Now it is all set for Spec Trig's 0:15 and L15 Terms 0:17 32. Find and understand the problem with the allowing L1 Cal Trig lookup memory page select track the L0 Fast Z. xx 33. Find and understand the problem with the Tier 3-4 crate having high order bits become set if M114 is powered off and then on. Does Tier 3-4 really draw lots of extra power with M114 off. Why does cycling the Tier 3-4 power fix the problem. It the problem caused by high order operand lines that are driven only by on card spreaders? ---> 100k ECL spreader bias networks xx 34. Find and understand the problem with L1 blowing about one transfer in 20k to L2. This probably only happens when L15 is running at high reject rate. It probably causes what looks to VTC as a monitor data only event. It probably involves a sync error in the A,B pipes. It is what currently causes TRICS to log re-sync required error which do not release the virtual memory. xx 35. Find and understand the problem with the L1 FW causing a 30 nsec pulse to sometimes leak out on start digitize lines to Calo ADC when they are running 12 calibs. Is it H101 ?? Is it a timing problem since M114 moved. Setting the Start Digitize MTG late by 1 tick appears to fix (aka hide) this problem. xx 36. The DBSC scaler that counts the number of COMINT Data Blocks that have been built (or I expect that it is really the number of time that COMINT has at least started to build a Data Block) is not working or else not connected. I think that this is M114 Slot 7 Scaler #4. Verify what scaler it is and the cabling to it and the documentation. 37. Get the signal COMINT Data Block Builder Running connected to an AND-OR Network Input Term. There may already be a term named or assigned to some like this. xx 38. Verify that all is OK (or else find the problems) with all the L15 Terms and with running L15 on all Spec Trigs 0:15. ******++++++++++++======++++++++======++++++=======+++++=======++++=====****** List of things to do BEFORE the 16 week Shutdown ---------------------------------------------------- xx 1. Fix the problem with some L1.5 Terms or with putting L15 on some Spec Trig's. xx 2. Understand - Explain the problem with running the Fast Z tracking in the Level 1 Calorimeter Trigger. xx 3. 10k event run for verifying the operation of the L1 system. xx 4. Hi Eta GAP runs and Hi Eta Veto runs for Harry. 5. Install the 10nonH101 IML cards in the L1 Framework. xx 6. De 10H101 the last two FSTD cards. xx 7. Understand, straighten out, cleanup and label the State Scalers for the VTC. Are we monitoring the best set of States? What DBSC, What cables? Labels and variables in TrgMon? ******++++++++++++======++++++++======++++++=======+++++=======++++=====****** List of things to do DURING the 16 week Shutdown ---------------------------------------------------- 1. Test the 2nd FMLN; do it still have an error at Fermi but not at MSU? 2. ECO and Test two more CAT3's for operation in the negative momentum Tier 3. xx 3. Cleanup the M114 BBB Timing-Sync Bus cables. There are two of these cables that are currently swapped. AND remain swapped. 4. ECO and test perhaps 2 more CAT2's for operation as Tier 2 Adders. xx 5. Rework of the resistors on the BLS cards and the CTFE Terminator-Attenuators. xx6. Make cables, connect, and setup a 2nd FSTD to produce the Missing Pt number and to read it out through an IMLRO. NO I do not think this is worth it. xx 7. Make cables, connect, and setup the Tier 3 EM and HD CAT3 Thresholds 4:7 cards to have a remaining pedestal of 50 and to drive the Tier 4 Total Et CAT3 card(s). Setup the Tier 3 EM and HD CAT3 Thresholds 0:3 cards to have zero pedestal and to drive the IMLRO for readout of Global EM Et and Global HD Et. We will pull 50 off by another means. xx 8. Install the cabling for the voltage monitoring of all L1 power supplies. 9. Connect the COMINT Data Block Building Running And-Or Network Input Term and the DBSC scaler that counts the number of Data Blocks that the COMINT has started building. xx 10. Investigate what happens in the Tier 3-4 when M114 power is turned off. xx 11. Install the last short section of the 24" cable tray and its cover. xx 12. Install the Large Tile cables and cards. x 13. Full diagnostics runs of Framework and Cal Trig. xx 14. Replace +5V power supply in all Tier #2 and #3 pans x 15. Fix Water leak in M111 xx 17. install 700 Hz readout xx 18. install new TCC ******++++++++++++======++++++++======++++++=======+++++=======++++=====****** Current D0 Hall Work Rev. 17-NOV-1994 1. Get back to regular L1 Cal Trig testing including Large Tile testing which should now work all OK. Some of this will require exclusive use of the system. 2. Find sometime when beam running to run VTC code to see the two versions of IMLRO data that occurs during "T5" mismatch. 3. Possible start running, as the standard version, VTC code that looks for all IMLRO mismatches except for "T5". 4. Continue looking at the 16:31 L1 Spec Trig SBSC scalers to verify that the occasional "jumps" seen for some Spec Trig's on TrgMon have now gone away (because of de-H-ing the MBD's). 5. If everything looks stable, return the Data Block Builder to full speed. 6. Get all air flow sensors running again. Think about adding the differential pressure gauge as an air flow sensor. 7. When there is a scheduled down time, add wire wrap wires to the MBD's and CTMBD's to make all 10H115's happy. 8. Check if there are any MBD's at NWA. Is it time to recover all of the stuff from NWA? 9. Get regularly scheduled Pulser Runs done by Detector Shifters under way.