1993 Archive ============ D-Zero Hall L1 Framework and L1 Calorimeter Trigger Logbook --------------------------------------------------------------- current Log book is in D0_HALL_LOGBOOK.LBK .............................................................................. Date: 27-DEC-1993 At: MSU Topics: Trouble with +13,1 EM and HD readback The EM and the HD Trigger Towers at eta +13 phi 1 are reading back incorrectly; typically showing a value of a few tens of GeV. There appears to be no problem in actually generating triggers. When read by hand these channels show the corrent value of "8". CBus=0, MBA=202, FA=32, FA 224 EM and FA 225 is HD. .............................................................................. Date: 20,21,22-DEC-1993 At: Fermi Topics: Spare LTCC to Fermi, Known BLS to L1 Problems, Need to edit TrgMisc:Start_ 68020.Txt and need to make a TrgMisc: Start_TCC.Txt, Replace a BBB, Turn on |eta|=17:20 and watch the Temperatures, Replace two CTFE's in |Eta|=17:20, Fix the radiator leak in the bottom of M102 Temporary init error on one L15 digimem reg Is the eta 17..20 tier#2 wiring different? Eta +/- 1..16 CHTCR PROMs were tested. Eta +/- 1..20 Phi 1..5 CTFE PROMs tested Several Random Test Runs temporary 66 Gev EMEt traced to tier#3 ring of fire cause 800 Hz 15 GeV Glob EM Et Run Find DAC on 17..20. Spare LTCC to Fermi ------------------- Take two spare LTCC cards to D0 Hall. LTCC SN#8 and SN#9. This is recorded in their inventory sheets. Known BLS to L1 Problems and a Repair ------------------------------------- From Dan Owen's pulser run on about the 18th Dec the following BLS to L1 Cal Trig problems are known: -16,9 HD reads 60% of the expected value -15,25 EM reads 85% of the expected value -5,28 EM reads 25% of the expected value +6,13 HD reads 300% of the expected value +6,13 HD was repaired. It had a bad Term-Attn. The other three locations have not yet been looked at. Need to edit TrgMisc:Start_ 68020.Txt and need to make a TrgMisc:Start_TCC.Txt ---------------------------------------- The TrgMisc:Start_ 68020.Txt file needs to be edited and "re-posted" on the West wall of M113. Everything is OK except where it says the L1 68k Console and Keyboard are located. We need to make a TrgMisc:Start_TCC.Txt file to explain about the necessity to type a "B" after the >>> prompt on the TCC Console after it is powered up. I'm going to mount the TCC Console Keyboard in the top of M114 in front of the old TCC. Replace a BBB ------------- The BBB for MBA=200 CBus=0 was causing some problems. Typically a few registers with the same FA but different CA's would become corrupted when running Random-Cell test. This would randomly happen in any of the 4 backplanes services by this BBB (but more so in mba 201). Thus, BBB SN#9 was pulled and returned to MSU. BBB SN# 8 was installed. This appears to have fixed this problem. This corruption was first noticed during initialize trigger tower. Then again caused problems during Random tests, where a threshold register would get corrupted. Then again during 3 initialiazations after the power off to fix the radiator in the bottom of M102 Fix the radiator leak in the bottom of M102 ------------------------------------------- radiator work time: 22-DEC-1993 00:13:20.88 --- 03:29:02.99 The lower radiator between M102 and M103 had a pinhole on the M102 side of the manifold. The two water hoses were cut between the radiator and the floor. The back 2 screws were removed to be able to swing the radiator towards M103 and get to the leak. The side, top, and bottom of the manifold were brushed, flux-ed, and covered with tin solder. The radiator was put back in service without the clamp on this manifold. The stay-clean created enough smoke to get the VESDA (and the SOD) excited (the blower wasn't even running). +----+ | | +--------| radiator | | | ------+ +--------| (air flow into the drawing) water | | | hose | | | ------+ +--------| | (*) | | +--------| +----+ | | (*) leak location Temporary init error on one L15 digimem reg ------------------------------------------- After the long power off to fix the radiator leak, we ran 5 INITIALIZE in a row. During the first 3 we noticed the corruption of registers in the MBAs 201, 204 or 207. The last 2 racks were still off. We had one instance of a failure to initialize some registers on the ANDOR card at 0 129 16, but where the later initialization of the specific triggers, showed that the registers were correctly written after all. On all intialize we had a systematic failure to initialize the L1.5 digimem register at @ cbus 0 mba 57 ca 34 fa 27 which corresponds to Spec Trig #11 Requiring of L1.5 Term #14. Manual read/write showed that bit #4 (value 8) was stuck high. We had 10 initialization between 22-DEC-1993 03:29 and 04:48 that showed these errors. The next initialize was at 14:44 and no longer had such errors. Turn on |eta|=17:20 and watch the Temperatures ---------------------------------------------- Turn on the 4 Tier 1 card files in the two high eta racks. New Trigger Tower Range is: POS_NEG,E_1_20,P_1_32 time: 22-DEC-1993 14:33 Edit TRICS_BOOT_AUXI.DAT to reflect total coverage. Before turning ON After turning ON Tier 1 in M111 and M112 Tier 1 in M111 and M112 ------------------------- ------------------------- air flow 300 to 310 lfpm air flow 300 to 310 lfpm water temp 54.1 water temp 54.7 66.7 66.0 109.2 68.2 67.3 110.1 66.7 109.6 109.6 68.1 110.5 110.5 Work on and Replace two CTFE's in |Eta|=17:20 -------------------------------------------- The CTFE at eta -17:-20 phi 25 had -20,25 HD stuck at 255. A bent pin on the opamp was straightened and put in to its socket to fix the problem. The CTFE at eta -17:-20 phi 16 readout 0 for both EM and HD. It also sent all zeros to its Tier 1 CAT2 cards and its CHTCR card. I.E. it acted just like all zeros were coming out of its ADC. It worked OK for Test Reg Data. Pulled SN# 318 and installed SN#305 and this fixed the problem. Philippe points out that SN# 318 probably has a bad -1V ADC Ref Supply. SN# 318 is returned to MSU The CTFE at eta -17:-20 phi 6 gave errors for -17,6 Tot Et Ref Set #1. Pull CTFE SN# 312 and replace with SN#315 and the problem is fixed. Broken EN# 312 is returned to MSU. These errors were intermittent. The random test would notice the global sum for Tot Et Ref Set #1 would be behind by one count. But doing the loop again would not repeat the error. The method for locating the channel was to wait until random test found an error, use the TRICS_ACCESS tree browser to write down all tier #3 inputs, let random test redo the same loop, re-read the tier#3 inputs, and find the one that changed. Next, let random test find another error, and apply the same method again on the tier #2 inputs to find the bad tier #1 sum, and finally again on the tier # 1 inputs the bad chtcr input. The eta 17..20 tier#2 wiring different? --------------------------------------- Using the TRICS_ACCESS tree browser, we were not reading (get 0) the tier#2 PX and Py inputs on the expected operands. It appears that they were wired to different operands than the other two tier #2. Eta +/- 1..16 CHTCR PROMs were tested. -------------------------------------- The CHTCR PROM test was run successfully on all eta +/-1..16 CHTCRs. This test can only address one card at a time. The method is to 1) use 0 loop of random test to set all towers to simu mode with 0 for input 2) select the first CHTCR for PROM test, run the test 3) use initialize Trigger Tower to clean up the state left by the test. 4) go back to (2) for next CHTCR *** 27-SEP-1994 update: use instead 1) use initialize Trigger Tower to clean up the state left by the test. 2) select the first CHTCR for PROM test, run the test 3) go back to (1) for next CHTCR Eta +/- 1..20 Phi 1..5 CTFE PROMs tested ---------------------------------------- A test of all Lookup PROMs was started. This test doesn't yet know how to deal with Tier#1 to tier#2 truncation of the MSB. This truncation happens at 4096. One can thus only test 3 phis at a time in a given cell. The test was successfully carried on all etas for phis 1..2, then 3..5. The method is to 1) use 0 loop of random test to set all towers to simu mode with 0 for input 2) select the Lookup test on the desired phi range, and run it. Expect to have the test find unexpected startup global sums, as it is not controlling the whole set of towers. The test must be allowed to resynchronize, and this has to be done again for each of the 8 pages. 3) use 0 loops of random test again, to clean up the state left by the test. 4) go back to (2) for next phi segment. An attempt was made at 6..11, which failed with what seems to be a problem of this test with reading negative numbers out of Tier#3. My guess is that there still is some kind of problem underneath. Random Test Runs ---------------- 194,635 Loops on 21-DEC-1993 20:00 - 00:09 Full test over 1..16, all ref sets, types, pages etc, while 17..20 was still OFF We had some Glob TOt Tower count errors arround loop 38-39k with strong evidence of what was later identified as the BBB problem (at MBA addresses 201, 204, 207) We had some Glob EM Tower count errors arround loop 42-46k that were investigated to be the BBB problem (at MBA addresses 201, 204, 207..) The global counts were off by one count, until the random test finally hits the tower that was corrupted, and also noticess that the threshold comparator is off. Looking at the content of the reference set register for this tower showed that it no longer was what the random test had programmed earlier. Then run again untill loop 190295 where we have similar problem for same reason. 100,000 loops on 22-DEC-1993 04:20 - 04:35 (i.e. 9s per 1k Loops) Full test over 1..16, all ref sets, types, pages, etc, with 17..20 powered OFF No error 309,835 loops on 22-DEC-1993 19:25 - 20:44 Full test over 1..16, all ref sets, types, pages etc, but with 17..20 powered ON No error untill loop 309818 We then had Px Momentum and Global EM Tower count problems Left over problems. Right before leaving to return to MSU, run on all etas 1..20 with all ref sets, all ref types, but on page #4 only There were problems with EM tower count ref#0. What is now peculiar is that the count is behind by 2 (all at once), then comes back (500-800 loops later) to what it should be, then gets off by 2 again. Most of the time, the error is reproduced by redoing the same loop. There was 3 instances of this over about 4k loops. Temporary 66 Gev EMEt traced to tier#3 -------------------------------------- After this power off, we witnessed again the global CalTrig display show occasional 66 GeV readout of Global Em Et (and corresponding Tot Et). Using a fake trigger set with a 15 GeV EM Et Threshold we saw an andor rate of >100 KHz. Dan Power-cycled the Tier#3 and this effect went away. The Andor rate on the same fake trigger is now about 800 Hz. TRGMON ADC dump helped to attribute this to the ring of fire. Run Find DAC on 17..20. ----------------------- We ran FIND_DAC on the last two racks. The two CTFEs that were replaced showed (of course) a significant change in their DAC_BYTE. But we saw also DAC_BYTE increment 6 for HD,POS,E_20,P_32 26->32 ............................................................................. Date: 17-DEC-1993 At: Fermi Topics: run random and lookup tests restore sending mail on CalTrig errors release TRGMON with Lg Tile Ref Set - chtcr tests now ok, but only eta +1..4 phi 1..8 was run - try finding out what is causing errors in random tests - correction registers still need to be zeroed by hand - px/py correction registers need to be loaded with a big number to avoid dithering around zero as the code does not read these counts as sign integers very confusing, no conclusion - try running lookup test - tier #1 truncation is in the way very confusing, no conclusion - update user1:[trguser]mail_server.com remove the IF statement skipping the mail messages for calorimeter trigger initialization errors - make our version of TRGMON available to the world in USER1:[TRGUSER.TRGMON] (2 files: TRMGON_MAIN.EXE and RUN_TRGMON.COM) .............................................................................. Date: 16-DEC-1993 At: Fermi Topics: Run Find_DAC, load new values of 1..16 Power up tier#2 17..20 Update INIT_AUXI for location of L0-L1 Problem with LTCC in Tier 3, Replace the Cal Trig MTG Momentum Map Select PALs, Turning of M114 still screws up Tier 3, Tests of Large Tile Trigger, Problem with the Parameter Page Display of L1 Trig rack voltages, second version of the VTC program, A 4th CAT2 problem (eta +1:+4 phi 25:32). - Successful run of Find_DAC over eta 1..16 Paste these new values in INIT_DAC_BYTES.LSM, and 17..20 are left intact These values were generated on the new TCC with TRICS V5.2. This run took 33 minutes. - Dan reconnects the power supply in tier#2 17..20 and turn this tier #2 on. - Update TRICS_INIT_AUXI.DAT Change the location of the L0-L1 box from Tier#2 9..16 to Tier#2 17..20 (i.e. from mba 209 to 249) - propagate above change to USER1:[TRGUSER.DIRECT_TO_TCC]FORCE_L0_FAST_Z.MSG and copy to msu::hepe:[TRGUSER.DIRECT_TO_TCC] Problem with LTCC in Tier 3 --------------------------- The Tier 3 LTCC card showed a problem on most of its output of having 20 nsec spikes even when none of its inputs were connecteded to a signal source and it was not receiving either its input latch clock or its Am29525 Latch-Shift clock. These output glitches would go high for about 20 nsec. The worst cases were high about 20% of the time. This problem went away when when the modifier input was strapped for Tier 2 operation (i.e. there was only a problem when it was strapped for Tier 3 operation). The problem appears to be the high positive common mode voltage at the input to the 100314 receivers when the LTCC Modifier input is strapped to default to Tier 3 operation. As designed and when strapped for Tier 3 operation the common mode input is about plus 1.1 Volts. When strapped for Tier 2 operation the common mode is about -0.60 Volts. The "old standard" 3.9 K and 5.6 K spreaders were originally picked for operation between +5 and -5.2 Volts. A better choice for +5 and -4.5 Volt operation might be 5.6k to -4.5 Volts and 10k (or better yet 11k) to +5 Volts. This gives a common mode voltage of about -1.2 volts and about 60 mV across 100 ohm terminator. It would be best to mount R127 and R129 in sockets so that both the voltage source (J9, J10, J11, J12) and the SIP resistors can move when the default Modifier is changed from Tier 2 to Tier 3. To get things going here we removed the J9 to J10 jumper and installed an AMP housing with a 750 ohm resistor. This puts the common mode for Tier 3 defaults at about minus 1 Volt. Replace the Cal Trig MTG Momentum Map Select PALs -------------------------------------------------- For operation with the Large Tile Trigger the Momentum Map Select lines must pick the center page for the first lookup and then page 8 for the second lookup i.e. the Large Tile lookup. This is easy to do with the CTMapSel type of PAL but the Momentum Map Select MTG Channels had Bit2 PALs installed in them (i.e. Cal Trig MTG Chanels 12, 13, and 14. The Bit2 parts were removed and the CTMapSel PALs installed. This also requires a change in the TRICS_Init_Auxi both to switch from Bit2 to CTMapSel and then to setup up the selection of 1st lookup center page followed by 2nd lookup page 8. While replacing the Bit2 PALs M114 was turned off and Tier 3 was still running. When M114 was turned back on and the system initialized the Total Et display in the Global Cal Trig display in TrgMon showed the normal problem of 16K or 32K GeV. As usual this was fixed by turning Tier 3 off and then back on. Thus the new +5 Volt bricks in the Tier 2-3 Power Pans has not fixed this old problem. Thus is M114 is going to be off then ALWAYS turn off Tier 3. Tests of Large Tile Trigger --------------------------- Verified that letting the Momentum PROM's do two lookups (1st from the center page and the 2nd from page 8) did not bother the operation of the missing Pt trigger (i.e. the FMLN). This appeared all OK. Verify that all Large Tile Ref Sets so the same And-Or rate if they are all set to the same threshold. This had a problem that Ref Sets 0:3 were a little smaller And-Or rate than Ref Sets 4:7. This problem was traced to the Py CAT2 in eta -5:-8 phi 17:24. Replacing this water damaged CAT2 made all Large Tile Ref Sets show the same rate. CAT2 SN# 23 was pulled out and replaced with SN# 142. Verify that an monotonic spectrum of Large Tile Ref Set thresholds gives a rational monotonic set of And-Or rates. Philippe has data from this test which was done with no MR beam and no TeV beam. A copy of this plot is in the paper log book. A 4th CAT2 problem ------------------ The Py CAT2 at (eta +1:+4 phi 25:32) started showing the problem of always reading back with the LSB data bit set high. Pull CAT2 SN# 83 and install SN# 152. The problem with SN#83 is a broken R86 and a solder bridge on the solder side. This solder bridge has been marked but not repaired on the card. Problem with Parameter Page Display of L1 Rack Voltages ------------------------------------------------------- Discovered a problem with the Parameter Page display of voltages from all 4 Tier 2-3 Power Pans. The -2V and +5V labels and displays were swapped. All Tier 1's and M114 and L1 Framework rack displays all looked OK. The problem is in Dan Owens Hardware database data. He will fix it. Second version of the VTC Program --------------------------------- TrgCur: now contains two versions of the VTC program. They are RunMe68020.ABS_Eta_1_20 this does NOT insert zero energy response anywhere RunMe68020.ABS_Eta_1_16 this DOES insert zero energy response for eta 17:20 Currently the standard load file RunMe68020.ABS is a copy of the RunMe68020.ABS_Eta_1_16 file so that people can work with L2 filters and such. Things to bring to Fermi: ------------------------- Spare LTCC cards blank 16R6 BCN PALs D cell Flashlight batteries .............................................................................. Date: 14&15-DEC-1993 At: Fermi Topics: Swap the rest of the HD PROMs, Plug in the rest of the Term-Attn's except for 6 values on 2 CTFE cards Restack the rest of the racks Restore INIT_DAC_BYTES with all etas Turn on caltrig to eta |16| Modify TRICS_BOOT_AUXI Instal new TCC LSM object file - The eta |5..8| were destacked, new HD PROMS and Term-Attn's were installed. Green 1992 Term-Attn's were replaced with Yellow 1993 Term Attn's. The eta +9..+16 racks received new Term-Attn's and were restacked. - Some eta +7 and +8 eta Term-Attn networks were permanently relabeled to be eta +5. They have the exact same value. - 5 CTFE cards could not receive correct Term-Attn Networks: 1 CTFE at eta -5..-8, phi 1 uses an eta -9 Term-Attn network on eta -7 and -8 4 CTFE at eta +9..+12, phi 1, phi 2, phi 3 and phi 4 use an eta +1 rev 1990 Term-Attn network on eta +12 - copy MSU::LSMP$DATA:NEW_D0HTCC_FILE_FOR_L15CT.LSO to D0HTCC::[TRIGGER]LOOKUP_SYSTEM_MANAGER.ZEB, and TRGCUR: This file describes the new HD PROMS for L15CT. move TEMP_D0HTCC_FILE_L15CT.LSO to [TRG_CURRENT.OBSOLETE] move and rename old TRGCUR:LOOKUP_SYSTEM_MANAGER.ZEB to [.OBSOLETE]LOOKUP_SYSTEM_MANAGER.ZEB_PRE_L15CT - modify TRICS_BOOT_AUXI.DAT Find better method for shrinking eta coverage. It is required by TRICS that the towers in INIT_DAC_BYTES.LSM exactly match the coverage currently defined. Failure to interpret the file will cause TRICS to keep the old value (init default is 10) as DAC_BYTE. Also any tower not defined in INIT_DAC_BYTES.LSM keeps its old (10) DAC_BYTE. Editing this file every time we shrink coverage or restore a larger coverage is inconvenient. We have a file with pedestal for eta 1..20, but would like to limit the current coverage to 1..16. The new method is the following: TRICS_BOOT_AUXI.DAT now first defines a full coverage (or whatever appropriate coverage for the INIT_DAC_BYTES.LSM), then loads INIT_DAC_BYTES.LSM, then (if necessary) defines the actual more limited coverage. - restore the 2-DEC-93 version of INIT_DAC_BYTES.LSM - The Calorimeter Trigger was turned back on out to eta |16| - fix tree offset problem and build new system. The problem was in the computation of the sum_zeresp to figure the tree_offsets, the code was copied and insufficiently updated, so that it was using EMEt lookup 4 times to compute the tree offsets. It loaded the same tree correction in Tier 3 for EM Et, EM L2, HD Et, HD L2. All the Global Energy sums were off except for EM Et. - Jan G and Bruce G setup a download of a Specific Trigger using Large Tiles. The messages from COOR to TCC are fine. At this time Tier 1 is not connected to tier 2. The Large Tile Tier #3 that was still generating a 15kHz Andor rate. The scope shows that we have asynchronous noise pulses out of the tier 3 LTCC. This noise remains with all inputs unplugged, and CalTrig timing signals are shut off. The tiwer #2 LTCC cards do not show similar noise. Dan changes the resistor spreader circuitry for the mode select PROM address line that sets ltcc for tier #3 mode. - Fix TRICS Tree Browsing software to read CAT3 operands. The problem was with a register address shift while reading CAT3 operands Use Tree browing to locate a problem with tier #1 cat2 for eta -5..-8, phi 1..8 was 255 too low and read phi 7 input as 0 card replaced, problem gone Pulled CAT2 SN# 55 and installed CAT2 SN# 153. and tier #1 cat2 for eta -5..-8, phi 17..24 was %X180 too high card replaced, problem gone Pulled CAT2 SN# 87 and installed CAT2 SN# 200. - Try to detect a problem that seemed to make Global EMEt read 16 GeV more than EM L2, even when all towers were excluded and both lookups locked on page 4. We excluded all EM towers, and set a specific trigger to require 250 MeV of EM Et. The Andor rate stayed at zero. The problem that we thought we saw earlier was gone. - Extend this testing method to other quantities. Exclude all EM and HD trigger towers and verify that the andor rate stays at zero when one requires 250 MeV of Tot Et or any tower above an EM refset of 250 MeV or any tower above an Tot refset of 500 MeV - Remember that $TRICS_ACCESS ->Coor.Access->Initialize.Trg.Twr can de-exclude trigger towers but wipes out reference sets. .............................................................................. Date: 8,9,10-DEC-1993 At: Fermi Topics: ReStack Tier 1 -9:-12, -13:-16, Start using the new TCC, And-Or Terms for Norm MR_Veto, Review all Bagby rack And-Or Term connections. Installed the new TCC and its BA23 box above rack M114. We have switched to using the new TCC. I need to bring a power plug next week so that I can bring the power connection for these boxes to the power outlet strip inside M114. New Term-Attn Networks (yellow 1993) installed in rack -9:-12 and -13:-16. These racks were restacked. They have yellow 1993 HD PROM's. The bottom 4 cards in rack -9:-12 still need their -12 Term-Attn Network installed. Set up 3 new signals for Norm from the Bagby NIM rack (MR_Veto_Low, MR_Veto_ High, MU_HV_Recovery). Edited Trig_Config.CTL to set these up. Review of the cabling from Bagby to us follows: NIM to ECL Pair on Module Lemo the 17 And-Or Term Current Connector Pair Cable Number And-Or Term Name ------------- ----------- ----------- ----------------------------- 1st i.e. top 17 120 MR_CAL_LOW 2nd from top 16 121 MR_MUON_LOW 3rd from top 15 122 MR_CAL_HIGH 4th from top 14 123 MR_MUON_HIGH 5th from top 13 124 MRBS_LOSS 6th from top 12 125 MICRO_BLANK 7th from top 11 126 MIN_BIAS 8th from top 10 127 LV0_HALOP 9th from top 9 116 MR_PERMIT 10th from top 8 117 MU_HV_RECOVERY <----- 11th from top 7 118 LV0_HALOPB 12th from top 6 119 MR_VETO_LOW <----- 13th from top 5 115 MR_VETO_HIGH <----- 14th from top 4 Not Connected 15th from top 3 Not Connected 16th i.e. bottom 2 Not Connected In addition And-Or Terms #113 and #114 are open and the pins accessable and term #112 is open but its pins are covered by the AMP housing for lower numbered terms. .............................................................................. Date: 3-DEC-1993 At: Fermi Topics: Boot TCC, VESDA Test, Edit Trics_Init_Auxi.dat Some one tripped of the L1 system at about 9AM this morning so I used this as an opportunity to boot TCC and pick up the 2DEC93 system. A little after 10 this morning we made a test of the VESDA. Test smoke was sprayed for about 5 seconds into the front of rack M108. The trip occured about 10 seconds after the spray. The VESDA analog display was pinned for about 5 minutes. This test was somewhat complicated by the fact that right after the test smoke was sprayed someone used a walky-talky in the 1st MCH. But there is no indication that this caused the trip i.e. the whole RPSS was shut of via the VESDA. I edited TrgCur:TRICS_Init_Auxi.dat to change the comments about Ch #30 and #31 in the Cal Trig MTG. These are now the Tier 2 and Tier 3 LTCC timing signals. I changed the comments to indicate this. NO functional change was made. I distributed this file to D0HTCC[Trigger] and to MSUHEP::[TrgCur- DZero]. .............................................................................. Date: 2-DEC-1993 At: Fermi Topics: Measure the timing of Start Digitize, TCC files for eta 1:8 operation and the old HD PROM's still in eta 5:8, More L15CT equipment arrives, Cook new CRCToken parts. Make a test of the timing of the Start Digitize signal. This was measured on a Tek 2467B analog scope (i.e. not on a digital logic analyzer). It was measured using Geographic Section #6 (recall that #5 and #6 are currently free). At normal Test Trigger was started and then cranked up to 50 Hz. TRICS was used to add Geo Section #6 to the normal Geo Section #1 of the Test Trigger. The ECL to Scope Box with the twisted cable that stretches it to 32 nsec was used to listen to the Start Digitize signal. The other scope input was the normal T0 Ref Mark through the normal 32 nsec cable. The results are: Start Digitize goes up at 2542 nsec after BX or average of 951 nsec before the next BX. Start Digitize falls 204 nsec after BX. Start digitize lasts for an average of 1152 nsec. All of these numbers should be within +- 10 nsec plus the scope calibration. This information was put in the Run_1A_Timing file in the Timing_and_Control sub directory. It fits in OK with the other estimates of the timing of Start Digitize. D0HTCC related stuff: Edit Trics_Boot_Auxi.dat to set the Cal Trig eta coverage to 1:8 Copy Philippe's Temp_D0HTCC_File_L15CT.LSO to D0HTCC::[Trigger] Lookup_System_Manager.ZEB This is a "special" version that has eta's 5:8 still with the old HD PROM's. Use ELoadHTCC to set EWork1:Trics_V50.Sys_2DEC93 as the running system but did NOT trigger the node. The 2DEC93 system puts Large Tiles eta range control under the influence of run time TRIG_TWR eta range messages. On Friday morning I will boot D0HTCC after the VESDA test. We received the two DeBug pod and software packages today from White Mountain Systems via Ariel. Still no sign of the 2nd new TCC Cooked two of the new CRCToken 16RA8 parts. Data Sum = 7E28 Xmit Sum = 4C05 Both parts cooked OK, not fuse errors no vector errors. .............................................................................. Date: 1-DEC-1993 At: Fermi Topics: Install Tier 2-3 G10 insulators, shelves for the new TCC and the BA23. Turn on |eta| = 1:8 new water leak, speed up the blower, some temperatures, Inventory of the L15 CT Ariel equipment that arrived, Wrote a file to describe the Tier 3 LTCC card to AND-OR Network Input Terms Cables. When installing the last of the shockless system G10 parts I noticed that the two high eta Tier 2 card files did not have the insulator strip installed between the power bar mounting bolts and the aluminum angle that the card file sits in. I installed G10 insulators M111 and M109. M107 and M105 did have insulators already installed. It is hard to believe that we forgot to install insulators in M111 and M109. A BA23 is 17" wide and 25" long (deep) and less than 6" high. A uVAX 4k is 19" wide and 16" long (deep) (plus more for cables out of the back) and less than 6" high. M114 is 24" wide and 30" deep. It has a 3" build out in front. The rear 6 3/4" are covered by a cable tray that runs along the back of the racks. The VT300 covers some of the center section of the front build out. The power contactor box takes of 2 inches along the east side of the rack (starting about 12" inches from the front of the rack and running for 7" along the east side. For shelves, cut 22" by 23" 1/8" Aluminum. Use 1/2 rod for legs. Mount legs 3/4" from edge. This gives about 19" by 20" of free clearance. First shelve is 6" above the top of the rack (to clear our cables and the next shelve is 6" above that. We found a new water leak today. It is the bottom radiator in rack M102. A strap clamp was put on this radiator yesterday. Now it is leaking from where the the threaded receptacle connects to the vertical header pipe. We turned off the water to M102 and I disconnected one of the hoses from the center aisle distribution manifold. This leak is in the side of the short header pipe so it is not clear what to do i.e. solder it, glue it, cut the header off and put two hoses on... Turned on Tier 1's in M103 through M106, Tier 2 in M105 and Tier 3 in M107. Made a pedestal run to fit with the South BLS racks that are off. The blower was brought up to full speed. Stable Temps with just FW running and slow blower: 59.2 58.5 57.2 55.0 water temp 59.4 58.2 57.7 0.70" diff air pressure Stable Temps with FW and the above listed Cal Trig running full speed blower: 64.9 64.2 77.0 54.7 water temp 64.9 78.7 77.6 1.35" diff air pressure Inventory of what arrived from Ariel: Smaller white box shipping 1Z 2X0 743 02 0000 2035 It says PO P22200 Hydra-II Ariel serial 7052 Fermi sticker 084182 TI assembler software (this item is not listed on the white) (Fermilab Packing List ) Larger brown box shipping 1Z 2X0 743 02 0000 2026 It says PO P07890 Hydra-II Ariel serial 7044 Fermi sticker 084183 Hydra-II Ariel serial 7040 Fermi sticker 084184 Hydra-II Ariel serial 7047 Fermi sticker 084338 Wrote a file to describe the Cable that carries the Tier 3 LTCC Card to AND-OR Network Input Terms signals. This is LARGE_TILE_TIER_3_TO_AND_OR_TERMS.TXT in the [D0_TEXT.CABLING] directory. Now I just need to make them. .............................................................................. Date: 30-NOV-1993 At:Fermi Topics: Reinstall the 8 Pack Radiators, Clamps and mud flaps on radiators, Receive more L15 CT stuff The two 8 Pack Radiators were reinstalled this morning. They were vacuumed and combed before they were installed. They do not look in too bad a shape. We once again are running with the top aluminum blocker panels off. Dan Owen has installed the strap type clamps on the top two radiators in racks M106 through M111, and in the two Trigger Framework racks M101, M102. I have installed strap type clamps on the three radiators in M114. I installed shroud G10 pieces (mud flaps) on the last of the Cal Trig racks. Summary of strap clamps, mud flaps, and solder: Both 8 Pack Radiators have been soldered Trig Framework has strap type clamps. M114 has strap type clamps Cal Trig Racks: M103 through M105 mud flaps on all 4 radiators M106 through M111 strap clamps and mud flaps on the top two radiators and just mud flamps on the bottom two radiators. We have 4 spare strap type clamps and 2 or 3 spare brass clamps. More L15 Cal Trig stuff has arrived: The 4 power supplies for the L15 CT VME crates have arrived, an Ariel Box with a Hydra-II and the assembler software, and an Ariel box with 3 Hydra-II's. All 4 Hydra's had been opened and Fermi inventory labels attached. .............................................................................. Date: 22-NOV-1993 At: Fermi Topics: Work on the 8 Pack Radiators, install the G10 Shockless System parts on all Lower Tier 1 card files Pulled the 8 Pack Radiators out of the 2 end air flow racks so that they can have their header pipe ends soldered over and spray covers installed. Moved M100 out of the way to pull the M100 end 8 Pack. I was able to get the M113 end 8 pack out through the M113 rear door. I only needed to pull the RPSS and cables out of the M113. They did not finish soldering or covering either of the 8 Packs today so I put things back together and started it up all OK. The schedule now calls for reinstalling the 8 packs next Monday. I remain very concerned about the senseless bending and damage to the cooling fins. Dan Owen does not think that it makes much difference. Reinstalled the Shockless System G10 parts in the lower Tier 1 card files. It is not at all clear if the RTV dike on the horizontal G10 piece helps or hurts. i.e. water flowing down the backs of the vertical G10 Shockless System parts is not forced to flow towards the rear. .............................................................................. Date: 22-NOV-1993 At: MSU Topics: Look at CRC PAL Errors Checked the CRC PAL errors that Dan found at Fermi last week. (1) CRCSTROB This error on test vector #2 is another example of a problem with the $0 AMD software. The "expected value" of the output pins 16-19 (the /CRDY outputs) were not specified by CHECK statements for this "vector" in the .PDS file, but instead are the values that the AMD software "expects." In this case, the AMD software expected the outputs pins to be LOW. I have no idea why the AMD software expected this, the pins are clearly in an undefined state (they have not received a RESET, nor have they received a CLOCK). The pins are described in the comments of the SIMULATION section of the .PDS file as being in an undefined state. There are no "instructions" available in the AMD PALASM-2 simulation language to check the "undefined-ness" of a pin. The output pins simply default to some state (based on the internal design of the output macrocell). When Dan ran the test vectors, they defaulted to output HIGH which conflicted with the AMD software's choice of LOW. Again, they are in fact UNDEFINED for Vector #2. Summary: The CRCSTROB chip works as designed. No re-design of this part is required. I will "fix" the .JDC file and annotate the .PDS file to indicate that a "fix" is required to the .JDC if the part is ever revised. (2) CRCTOKEN The errors on the test vectors for CRCTOKEN on the other hand show an actual error in the PAL design. This is another type of error that we have seen before. The problem is this: we have one D-flip-flop feeding another D-flip-flop in a "shift register" configuration as shown below: .-- CACK_DELAYED .-------. | .-------. /CACK -|>o----| D Q |--*----| D Q |--- /CREQ | | | | .---|> | .---|> | | `-------' | `-------' CLOCK ---*---------------' (the D input of each flip-flop is also OR'd with the VMERESET signal to force the flip-flops to a known initial state) I expected this circuit to cause the inverted /CACK to arrive at the CACK_DELAYED output after the first rising edge of CLOCK, and arrive at the /CREQ output after the second rising edge of CLOCK. This is what the AMD software also thought would happen. What actually happens in the PAL is different, though. With only one rising edge of CLOCK, the inverted /CACK propagates through BOTH flip-flops. We have seen this type of error in 16RA8 PALs before, but now we see that it can happen with the CE16V8 parts as well. This error is a timing problem within the PAL. Summary: The CRCTOKEN part does not work as it should. A re-design is required. The AMD software did not detect this error in the design (but it is surprising that it is not possible to build a shift register with a CE16V8 PAL. .............................................................................. Date: 18-NOV-1993 At: Fermi Topics: Install G10 shrouds, cook CRC PAL's 19-NOV-1993 Installed more G10 shrouds around the backs of radiators. Now all radiators in M103, M104, and M105 have shrouds on all radiators and racks M106 through M112 have shrouds on the lower 2 radiators. NONE of these radiators have strap type clamps on them. The horizontal G10 piece of all shockless system for the Tier 1 card files have been RTVed to try to force any dripping water to the rear of the rack. Cooked two of Steve's first draft CRCToken PALS. They have Data Sum = 476D Xmit Sum = 17A7. There were vector errors (I expect the free AMD software has struck again). On the first pass vectors: 7, 8, 17, 18, 45, 46, 59, 60, 73, 74 give errors. On the second pass vectors 31 and 32 also give errors. There are 76 test vectors. Typical errors look like Pin Numbers ---------------------------- 111 1111 1112 Vector 1234 5678 9012 3456 7890 This is the 16V8 part. -------- ------------------------------ 1111 1xxx 0N0L LLLH HHHN 7 1111 1xxx 0N0L LLLL LLLN 0111 1xxx 0N0L LLLH HHHN 8 0111 1xxx 0N0L LLLL LLLN 1111 1xxx 0N0L LLLH HHHN 17 1111 1xxx 0N0L LLLL LLLN 0111 1xxx 0N0L LLLH HHHN 18 0111 1xxx 0N0L LLLL LLLN Cooked two of Steve's first draft CRCStrob PALS. They have Data Sum = 8DD4 Xmit Sum = ACDB. There was a vector error (I expect the free AMD software has struck again). On the first pass and on the second pass vector #2 gave an error. There were 28 test vectors. Pin Numbers ---------------------------- 111 1111 1112 Vector 1234 5678 9012 3456 7890 This is the 16RA8 part. -------- ------------------------------ 1111 1xx0 0N0H HHHL LLLN 2 1111 1xx0 0N0H HHHH HHHN .............................................................................. Date: 11-NOV-1993 At: Fermi Topics: Install G10 shrouds around the backs 12-NOV-1993 of the radiators, replace the top radiator in M111. Installed G10 shrouds around the backs of the radiators in 2 1/2 racks. It takes about 3 to 4 hours to cut and install the shrouds in a rack. Worked on M103, M104, and the top of M105. It looks like these shrouds (aka shingles) will stop a direct spray into the electronics but the drips running down them are likely to be intercepted by cross running cables and then transported to the horizontal G10 pieces of the shockless system and then run forward into the backplane. We need to add an RTV dike to this horizontal G10 shockless system part. The top radiator in M111 has had a leak in a copper pipe where the turn around tube connects to the long tube that runs through the cooling fins. Dan Owen has tried epoxy and RTV to plug this leak but it did not work. I was able to get this radiator out and replace it with one that had been pressure tested at 250 psi. I left the Tier 2-3 Power Pan out of the top of M112 until next week so that we can check again on this new radiator. Water flow is back on in rack M111. Gave the leaking radiator to Del to autoppse. .............................................................................. Date: 9-NOV-1993 At: MSU Topics: Crate ID's for Level 1.5 Cal Trig. Having talked with Jan Guida, we will use Crate ID's: 81 and 91 for the two Level 1.5 Cal Trigger crates. .............................................................................. Date: 4-NOV-1993 At: D0Hall Topics: Change COMINT PROM's and VTC code, 5-NOV-1993 Change the Crate Header Version Number and the L1 Revision Numbers, Installed the new version of TRICS, Edited Trig_Config.CTL, Install the And-Or card for Large Tile Ref Sets, make the new VTC code official, Talked with Del and Dan about G10 shrouds around the ends of the radiators. The CBus 0 COMINT PROM's were changed from Rev E to Rev F. The basic difference is that Rev F has the Large Tile Trigger readout in it. The source file for these new COMINT PROM's is: August_1993_CBus_0.ASF which makes the IBM/PC files ComMBA0F.dat, ComCAD0F.dat, and ComFAD0F.dat. The Data IO UniSite Model 48 sum check for these parts is: CAD = 000283B2 FAD = 000CE2F3, MBA = 000D2128. This is still all single COMINT operation stuff. The CBus 1 PROM's were not changed. The VTC code was changed to drop the 68k based Jet List Service and to stop making the 8 Lists of Spec Trigs Programmed to depend on a given Ref Set AND Fired on this Event. As part of this, the Crate Header Version Number and the L1 Revision Numbers were both changed. See the entry in this log book from 13-JUL-1993 for more details on Version Number. Crate Header Version Number was 6 and today changed to 8. L1 Revision Numbers were $03020102 and today changed to $04030203 | | | | VTC code Revision ----+ | | +---- Lookup System Revision COMINT PROM Rev ------+ +------ Trig Hardware Revision Started the new TRICS running; TRICS_V50.SYS_3NOV93 This adds the Large Tile Trigger programming, the ITC fix and the MPt FMLN programming. Edited the Online:[Detector.Resources]Trig_Config.CTL file to include the And-Or Input Terms for the Large Tile Trigger. Installed an And-Or card in M114 to be the "buffer" for the Spec Trig vs Large Tile Ref Set data. This is slot 3 of the bottom backplane of M114. The And-Or card installed is SN# AOC-68. There are only two spares left in the Fermi cabinet. Made the new cut of VTC code official. Talked with Del and Dan about making G10 (Del wants aluminum) shrouds around the ends of the radiators to control the spray from a future leak. The big question is what to do about the 8 packs at each end. .............................................................................. Date: 21-OCT-1993 At: D0Hall Topics: Received more L1 and L15 CT equipment and 22-OCT-1993 Repair the Direct-In-Test-Trigger MTG Received the following equipment for L1 and L15 CT: 1. The missing two sacks of allen screws for the VME crates. 2. Two MVME135-001 CPU modules SN 1346081 and SN 1348038 3. The first of the two new TCC's: VRM17-HA,H4 Monitor, uVAX 4000 model 60 box #AB32001C73, pQBA module #928, VS40DB module #862, Quantum 127 MB Driver #162233682350F, DataRam 16 MB expansion memory, LK401 keyboard, Mouse, Monitor cable, high density cables, bulkhead panel/cables, TK50 tape, hardware and software manuals. Direct-In-Test-Trigger MTG -------------------------- Muon people came to me and said, "A pulser bit is broken". The translation of this is that And-Or Network Input Term #6 was not working. I localized the problem to the MTG for the Direct-In-Test-Triggers. The output from Ch #7 of the MTG was making a 37 nsec blip instead of going up and staying up for one beam crossing 3.5 usec period. I replaced the 10H125 input ECL gate because it was socketed because they had cooked this part before. That was not the problem. The problem was the PAL (type BIT 8) had died. I replaced it and all was well from the point of view of the scope and things started working OK again. .............................................................................. Date: 14-OCT-1993 & At: D0Hall Topics: Received more L15 CT equipment, Work 15-OCT-1993 on Tier 1 CTFE PROM's Term-Attn's, Install LTCC cards, Meeting with Marvin, Dean, Mike Fortner, and Ken Johns, Signals for Nor Amos We received all of the items from Dawn VME including VME and VSB backplanes and fan trays. This stuff is transported to MSU. PROM's were installed in the cards for racks eta = -9:-12 and eta = +13:+16. The cards were pulled out of the rack for eta -13:-16 and the PROM's and Term-Attn's were pulled out of the cards and taken to MSU. Installed the LTCC cards as follows: Timing LTCC Card Service Signal LTCC Address File Card Eta Card Supplying Resistors Modifier Rack Slot SN# Range Address T&SS H Cut Jumpers ---- ---- ---- ------- ------- --------- --------- -------- M105 3 3 5:8 21 G none Tier 2 M105 2 2 1:4 11 H A,B,C Tier 2 M109 3 5 13:16 21 G none Tier 2 M109 2 4 9:12 11 H A,B,C Tier 2 M111 10 6 17:20 11 C none Tier 2 M107 4 7 Tier 3 54 F none Tier 3 LTCC Address Modifier is LOW for Tier 2 and HIGH for TIER 3 operation. Meeting with Marvin, Dean, M Fortner, and K Johns about triggering in Run II. The general idea continues to have "front end" buffers that can be loaded in perhaps 5 or 7 usec, more L1 trig's during a L15 decision, and only one L1 trig per super bunch, and if the L1 trig comes late in a super bunch then the next next super bunch may need to be skipped. Marvin is going to write up a note. Norm Amos wants copies of some of the Muon L1 Trigger signals that go into L1 FW and AND-OR Input Terms. This is temporary stuff for testing and setup of his Active MR Veto stuff. On top of M102 I will tap into the 17 pair cable that brings Muon L1 Trig to the L1 FW by crushing on a flat cable connector. I will put the Hi-Z ECL test box up there to listen to and buffer copies of the desired signals to Norm in rack M122. .............................................................................. Date: 8-OCT-1993 At: D0Hall Topics: Receive more L15 CT equipment, Work & 7-OCT-1993 on Tier 1 CTFE PROM's Term-Attn's, Work on water leaks, Hoods on Tier 2-3 25 pin connectors. Put new PROM's (yellow) in eta -17:-20 phi 9:32 and restacked it. Now all of M103, M104, M111, M112 have their new PROM's and have been restacked. Pulled CTFE's from M107, M108, M109 (i.e. |eta| = 9:12 and eta +13:16). Pulled the PROM's and Term-Attn's from all of these cards. Installed new (yellow) PROM in eta +9:+12. All of the pulled HD PROM's were white and all of the pulled Term-Attn's were white Jan 1992. Pulled the lower Tier 1 Power Pans from M103 (PDM-25) and from M106 (PDM-06). Put hose clamps on the nylon water manifolds (two clamps on each manifold). The plug end of one of the M106 manifolds had a very small drip leak. In M103 one manifold had small drip leaks from both ends. Re-installed the Power Pans and did shorts checks. Put hoods (back shells) on the 25 pin connectors on the Tier 2-3 Power Pans that needed them. Now all of the Tier 2-3 Power Pans and cable harnesses have hoods on their 25 pin connectors. Received the following L15 CT equipment and took it to MSU: Schroff qty 6 of the rear panels (they still owe use the hex cap screws) Ariel Assembler Linker Simulator Hydra HY2B-4-S1 SN # 7010 (it had the Hydra I documentation with it and no driver software). They still owe us the debuger XDS510 JTAG stuff on this order. This was PO # N99540 stuff. .............................................................................. Date: 1-OCT-1993 At: D0Hall Topics: Today and yesterdays work: Tier 2-3 30-SEP-1993 Power Pans, Install new PROM's, L15 CT equipment to MSU. In the +5V and -5.2 Volt power cables on all 4 Tier 2-3 running Power Pans and on the 2 spare Tier 2-3 Power Pans there is now a 25 pin connector so that the wiring harness may stay connected to the backplane when the Power Pan is removed. It is wired as follows: +5 Volts pins 1:10, 14:23 -5.2 Volts pins 12:13, 24,25 no connection to pin 11 All of the 4 installed Tier 2-3 Power Pans have been shorts checked again after this work. Connector hoods are still needed on some of these connectors (6 of the 10). The +5 Volt wiring harness behind the Tier 3 backplane has been cleaned up so that all 4 Tier 2-3 backplanes now have OK power wiring. All of M103, M104, and M111 (i.e. |eta| = 1:4 and eta = +17:+20) now have their new HD PROM's installed and have been shorts checked. In addition the top 8 phi's in rack M112 (i.e. eta = -17:-20) have their new HD PROM's installed. The rest of the CTFE's in M112 have been pulled out and the HD PROM's removed to take back to MSU. Three racks worth of HD PROM's are coming back to MSU. Recall the setup in these rack: M103 and M104 i.e. |eta| = 1:4 Green 1:4 Term-Attn Net's Yellow HD PROM's White EM, Px, and Py PROM's M111 and M112 i.e. |eta| = 17:20 Red 5:8 Term-Attn Net's Yellow HD PROM's White EM, Px, and Py PROM's L15 CT new equipment that was received at Fermi that is coming back to MSU on this trip: qty = 2 of MVME-135 BUG PROM's (This order was for 2.) qty = 4 of MVME-214 (This order was for 4.) qty = 3 of the Ironics I/O card (This is the last 3 from the order for 5.) .............................................................................. Date: 29-SEP-1993 At: D0Hall Topics: Yesterdays pressure test, During yesterdays cooling water pressure test no radiators leaked but the manifolds under M103 and M106 leaked. Dan Owen purchased good hose clamps to put on the manifolds. From now on any time a bottom Power Pan is out of a rack we will put hose clamps on all 4 connections to the manifolds. .............................................................................. Date: 24-SEP-1993 At: D0Hall Topics: Work on re-installing the Tier 2-3 Power Pans, Pull all of the G10 Shockless-System. Finished re-installing the Tier 2-3 Power Pans. This involved connecting the 5 connectors for +5 that are now on each Tier 2-3 Power Pan. This was a disaster. It took all day. One has to pull off paddle cards to get these on. Doing it once was "OK" but we can not do it every time that we change a Power Pan. We need to put a connector in this cable between the Tier 2-3 Power Pan and these 5 connectors for +5 and the 1 connector for -5.2 that go onto the backplane. Perhaps a DB25 type of connector could be used (5x4 + 1x4 = 24). The connections for the +5 volts on the Tier 3 backplane need to be looked at some more. This is probably the hardest one to do and I did it first. It can be reworked to give a better result. It needs to be looked at before it is run. Resistance checks of all Tier 2-3 Power Pans and Backplanes were OK. On next Monday or Tuesday there will be a pressure test of the cooling water system in the 1st MCH. Dan Owen knows about this test and he will be here. Today I pulled off all of the G10 shockless system so that the L1 radiators may be watched during the pressure test. .............................................................................. Date: 23-SEP-1993 At: Fermi Topics: Status of Cal Trig at blower slow down, re-install Tier 2-3 Power Pans, Install CalTrg4M MTG PROM, Install new HD PROM's and time how long it takes, make [PROM_Cooker] directory, Finish the wire wrap on the last 2 Tier 2 CTMBD's, Move Thermometers. The blower was slowed down again so that we could work on the HD PROM's, the new Term-Attn's and the radiator water leak clamps. As L1 Cal Trig was turned off all channels looked OK except: -20,25 HD reads 255, -17:-20,16 EM and HD all read zero. There had been no additional channels that lost DAC Ped control. The Tier 2-3 Power Pans were physically re-installed and wiring them up was started. The PROM #4 in the Cal Trig MTG was replaced by a new part, CalTrg4M. This new part includes the timing signals for the Large Tile cards. The new wire wrap for timing signals was added to the 2 "low eta" Tier 2 CTMBD's. Now all CTMBD's are ready for Large Tile Triggering. The HD PROM's were changed in the upper half of the M103 rack, i.e. 16 CTFE cards. This required: 19 minutes to pull the 16 cards, 30 minutes to swap parts on 8 cards, 34 minutes to swap parts on the other 8 cards, 10 min to clean the rack to get ready to re-install the cards, 40 minutes to re-install the cards. This is a total of 2 hr 15 min for one half of a rack. To prepair for PROM cooking at D0 Hall a [PROM_Cooker] sub directory was added to the root directory of the TrgUser account on the online cluster to make it like the MSU account. The [PROM_Cooker] files were moved from MSU to the Fermi system. The temperature sensors for 3 of the thermometers in rack M108 were moved. Before this all of these sensors were held together in free moving air near the very top of M108 at it air inlet side. Before they were moved a typical reading with all of Cal Trig off was: 57.7 57.0 56.7 58.0 58.0 57.6 Three of the sensors were moved to watch the air outlet from the CAT2 cards in the top of the upper Tier 1 crate in M108. The other three sensors are still in the top free air of M108 at the inlet side but they have been moved some what towards the back of this rack. The 6 sensors are arranged and read: inlet inlet outlet 60.3 59.0 58.1 inlet outlet outlet 60.2 59.2 58.6 All of these temperatures are with all of L1 Cal Trig turned off .............................................................................. Date: 21-SEP-1993 At: MSU Topics: Getting ready to replace Term-Attn's and HD Energy Lookup PROM's. Colors We will be installing new Terminator-Attenuator Networks in the eta ranges -16:-5 and +5:+16. Thus the Term-Attn's will be changed in 6 of the 10 racks of L1 Cal Trig. These "new" Term-Attn's are typically called the "May 1993" Term-Attn's. They are described in Maris's D0 Note #1707. They were actually assembled and installed in September and October of 1993. These Term-Attn's have their labels colored Yellow. The January 1992 have their labels colored Green. The original 1990 Term-Attn's have either Red labels or else unmarked white labels. All racks in the L1 Cal Trig will have all of their HD Energy Lookup PROM's changed for PROM's that are correct for use with the L1.5 Cal Trig (to read out the EM Et from the Total Et "port" on the CTFE cards. The value stored in page number 8 of the HD Energy PROM is selected to make the Zero Energy Response of the EM Et signal to be the same as the Zero Energy Response of the Total Et signal. These values are: |eta| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8 8 9 10 11 10 12 12 13 13 13 12 12 14 14 14 14 14 14 14 Zero Energy Response The PROM files for cooking these new HD parts are in the directory: MSUD01::DUA1:[BackUp.PROM_1_20_V10] The PROM's for the HD Energy Lookup are Cypress CY7C245A-25WC. We have 192 new unused parts of this type and 169 of these parts that have previously been programmed but are now erased. 361 total parts. 128 required per rack. .............................................................................. Date: 17-SEP-1993 At: Fermi Topics: Move the L0_to_L1_Box WPA from rack M109 to rack M111 The L0_to_L1_Box WPA card was moved from from rack M109 to slot 8 rack M111. All of the cables for this card were moved to enter through the hatch in rack M111. Some cables needed and extension (the cables for IMLRO readout and for sending L0 data to the And-Or Network Input Terms) and some cables were shortened (the cable from L0 and the cable to the Cal Trig MTG). Recall the connection of the cables on the paddle card for the L0_to_L1 Box. +--------------------------------------------------------------------------+ | +--------------+ +--------------+ +--------------+ +--------------+ | | | | | | | | | | | | +--------------+ +--------------+ +--------------+ +--------------+ | | | | +---------+ +--------------+ +-----------+ +--------+ | | | NC | | NC | | Sym & Good| | NC | | | +---------+ +--------------+ +-----------+ +--------+ | | +---------+ +--------------+ ^ +-----------+ +--------+ | | | From L0 | | Latch L0 Data| | | Sym Region| | Map Sel| | | +---------+ +--------------+ | +-----------+ +--------+ | +----------------------------------------------|---------------------------+ ^ ^ | ^ | | | | L0 to L1 | | | | Fast Vertex ----+ | L0 to L1 Box L0 to L1 Box from L0 | to AND-OR Net to Cal Trig L0 to L1 Box | Input Terms MTG to IMLRO Readout -+ Because this card has moved backplanes it address has changed. It was MBA = 209 and now it is MBA = 249. There is at least on reference to this card in the TRICS_Init_Auxi.Dat file. There may be other reference to it. .............................................................................. Date: 16-SEP-1993 At: FERMI Topics: Re-Stack M106 Tier 1, Work on LTCC Cables, More ideas about water leaks, I restacked the Tier 1 in M106. The resistance check looks OK. I have not run it yet. We were powered down most of the day becuse the online cluster was being worked on. Installed the LTCC cables into the front Panduit cable trays. Reinstalled the covers on the cable trays including the 4 highest eta racks which had never had their Panduit covers installed. Installed the LTCC paddle boards. This included a major rework of the cables behind Tier 3-4. The paddles boards were installed with the following differences compared to the 24-AUG-1993 edition of the file Large_Tile_Installation.txt 1. In rack M111 (the highest eta Tier 2 cardfile), the LTCC card is in slot 10 (not in slot 11) and the L0-L1 Box WPA is in slot 8 (not slot 9). This arrangement keeps the same backplane timing signal layout the same and eliminates the problem of a paddle card directly below a horizontal backplane stiffener bar 2. In rack M107 (the Tier 3-4 cardfile) the function of the 2 FMLN's is swapped compared to the installation instructions (i.e. slot 6 is really the Comparator FMLN and slot 7 can be the direct lookup FMLN. This is to keep things arranged the way the current cabling is setup and the way things ran in run 1a. 3. The Large_Tile_Instalation.Txt says that the special timing signal cables plug into the J6 connector on the C3PB card. I think that they plug into the J5 connector. I have them in the J5 connector on the C3PB. I need to check with Steve that these changes are OK and if they are OK then the rack layout files and the Large_Tile_Installation.txt file will need to be edited. Dan Owen worked on more ideas about clamping the ends of all of the radiator tubes. We pulled off some shockless system G10 to look at radiators. The idea is to install clamps at the same time as re-cooking HD Energy Lookup PROM's and installing new Term-Attn's (i.e. starting next week or the week after that). .............................................................................. Date: 15-SEP-1993 At: FERMI Topics: Repair the water leak damaged CTFE Channels, Repair bad CTFE Channels that Dan Owen discovered in his pulser run, Repair CTFE Channels that have out of control Pedestals, Get the L15 CT VME Power Supply order going. Worked on repairing the damage from the most recent water leak. This was the leak on 8-SEP-1993. This leak was discovered because the cooling system was losing 6 gallons a day so people started to look for a leak. They found water in front of M106. Dan Owen looked and it was the top most radiator between M105 and M106. Cal Trig has been off since this leak was discovered. This radiator has now been patched with a brass clamp. It appears that a number of application cards in M106 got wet and had power on them while wet. I do not think that anything in M105 got wet. I do not think that any backplanes, power bars, or Power Pans got wet. There was a lot of corrosion on some of our application cards especially around the power pins of the IC's, the power supply by pass caps and the power pins of resistor networks and other components. I washed the effected areas of the cards in warm tap water, rinsed with a lot of distilled water, and flooded areas that are hard to dry (e.g. the DIN connectors) with alcohol. All cards have been pulled out of the upper Tier 1 backplane in M106. Looking into the sockets of this backplane things look OK. The status of the cards from this backplane is as follows: Card Card This is for the UPPER Tier 1 Backplane M106 File Card Serial Slot Function Number Status when first examined; How-What cleaned ---- -------- ------- -------------------------------------------------------- 27 CAT2 HD 55 Lots of sever corrosion damage over a large central area about 1/3 of the card; all of this card was wet and scrubbed to clean it. 26 CAT2 +Py 61 The only corrosion damage was in the back left corner; only this corner was wet and scrubbed to clean it. 25 CAT2 +Px 127 Same initial status and cleaning as the card in slot 26. 24 CAT2 EM 49 Same initial status and cleaning as the card in slot 26. 23 CTFE 1 80 Same initial status and cleaning as the card in slot 27. 22 CTFE 2 49 Same initial status and cleaning as the card in slot 26. 21 CTFE 3 158 Same initial status and cleaning as the card in slot 26. 20 CTFE 4 92 Same initial status and cleaning as the card in slot 26. 19 CTFE 5 28 Same initial status and cleaning as the card in slot 26. 18 CTFE 6 40 Same initial status and cleaning as the card in slot 26. 17 CTFE 7 45 Same initial status and cleaning as the card in slot 26. 16 CTFE 8 50 Same initial status and cleaning as the card in slot 26. 15 CHTCR 1:8 20 Same initial status and cleaning as the card in slot 26. 14 CTMBD 30 Same initial status and cleaning as the card in slot 26. 13 CAT2 HD 88 Same initial status and cleaning as the card in slot 26. 12 CAT2 +Py 110 Same initial status and cleaning as the card in slot 26. 11 CAT2 -Px 39 Same initial status and cleaning as the card in slot 26. 10 CAT2 EM 66 Same initial status and cleaning as the card in slot 26. 9 CTFE 9 148 Same initial status and cleaning as the card in slot 26. 8 CTFE 10 77 Same initial status and cleaning as the card in slot 26. 7 CTFE 11 63 Same initial status and cleaning as the card in slot 26. 6 CTFE 12 128 Same initial status and cleaning as the card in slot 26. 5 CTFE 13 65 Same initial status and cleaning as the card in slot 26. 4 CTFE 14 51 No damage from the water leak. 3 CTFE 15 84 Same initial status and cleaning as the card in slot 26. 2 CTFE 16 107 No damage from the water leak. 1 CHTCR 9:16 19 No damage from the water leak. Card Card This is for the LOWER Tier 1 Backplane M106 File Card Serial Slot Function Number Status when first examined; How-What cleaned ---- -------- ------- -------------------------------------------------------- 27 CAT2 HD 87 Lots of sever corrosion damage over a large area near the front of the card about 1/3 of the card; all of this card was wet and scrubbed to clean it. 26 CAT2 -Py 23 Same initial status and cleaning as the card in slot 27 of this backplane. 8 CTFE 26 159 Lots of corrosion damage around the input Op-Amp for card channel #4 HD; a large area in the front of this card was wet and scrubbed to clean it. This card was giving a zero in TrgMon ADC Counts from its Ch #4. The rest of the cards in the LOWER Tier 1 Backplane of M106 did not appear to have gotten wet from the radiator leak. We need to find a way to quickly discover that we have a leak so that we can turn the power off. Getting wet is bad but being wet while power is on appears to be a lot worse. Can we spot the leak with a humidity meter in our racks? Dan Owen's analysis of last weeks pulser run found four bad CTFE channels. The initial problem and the repair of these 4 channels is listed below: eta,phi Card location Serial No Problem - Repair Action -------- ----------- ----------------------------------------------------- -18,18 EM CTFE SN 207 EM gives only 1/2 normal response; replace C340 with a 220 pf mica cap. A 15 pf cap had been mistakenly installed. -18,21 EM CTFE SN 240 EM gives only 1/2 normal response; C340 cold solder joint. -17,25 EM CTFE SN 186 EM gives only 1/2 normal response; C334 cold solder joint. -17,30 EM CTFE SN 311 EM gives only 3/4 normal response; C312 and C238 were installed in each other's location. A number of CTFE's were repaired that had lost control of their pedestals because of leaking - shorted 0.1 uFd capacitors in their DAC circuits. These cards in the following list were repaired: eta,phi EM Card Channel Reading location HD Serial No Before Repair -------- -- ----------- --------------- -19,30 HD 283 82 counts -14,22 HD 297 36 counts -11,10 HD 282 10 counts (DAC was set low to try to get 8) +20,32 HD 321 22 counts L15 CT VME Power Supplies The order for the power supplies for the four VME crates for the L15 Cal Trig was stuck because Power-One quit making the SPL400-5000. I called Don Rogus (x4177) and changed the order to four Power-One SPM2A6M6 supplies. This is on Fermi Requisition #16008. These are the same (or at least very similar) to the supplies that Mike Shea now uses. .............................................................................. Date: 14-SEP-1993 At: MSU Topics: Keeping the Master and Backup PROM and PAL disks current. Added to the master PROM disk: LTCCPROM.Dat PROM for the LTCC cards. CalTrg4M.Dat Cal Trig MTG PROM #4 with LTCC signals. ComCAD0F.Dat COMINT Card Address PROM for single COMINT with LTCC ComFAD0F.Dat COMINT Func Address PROM for single COMINT with LTCC ComMBA0F.Dat COMINT MB Address PROM for single COMINT with LTCC The new COMINT PROM's are for CBus 0 for use with single COMINT with the LTCC cards being readout. They come from August_1993_CBus_0.ASF This put the master PROM disk at 36 files 159744 free bytes. Added to the master PAL disk: PathSlP2.PDS Path Select P2 card for the L15 Cal Trig 16RA8 PathSlP2.JED Path Select P2 card for the L15 Cal Trig 16RA8 PathSlP2.JDC Path Select P2 card for the L15 Cal Trig 16RA8 This put the master PAL disk at 30 files 112640 free bytes. These new files are going to D0 Hall on a transfer disk to be put on the D0 Hall master PAL and PROM disks. .............................................................................. Date: 9-SEP-1993 At: MSU Topics: Set Cal Trig eta coverage to 1 tower Because L1 Cal Trig is back off, I edited Trics_Boot_Auxi.Dat to set the eta coverage to only one Trigger Tower. Copy this new Trics_Boot_Auxi.Dat file to MSU. By hand via Phat set TCC to limited Cal Trig eta coverage. .............................................................................. Date: 8-SEP-1993 At: MSU Topics: More Water Leaks, More bad CTFE Pedestals. Dan Owen calls to report that there is a new water leak. I think that he said that this leak is between M105 and M106. He said that it is once again in the radiator header pipe cap. He is going to get a pulser run, then shutoff the Cal Trig and plug the leak with a c-clamp for tonight and with an official brass clamp in the morning. The following CTFE channels have lost pedestal control since last week: What is going wrong? -19,30 HD @82 -14,22 HD @36 -11,10 HD @10 (This channel's DAC is cranked down.) +20,32 HD @22 -8,26 HD @0 (This could be something more than a bad cap.) .............................................................................. Date: 3-SEP-1993 At: Fermi Topics: Tier 2-3 CTMBD's, Status Talk, L1 Tier 1 running OK. I worked on the wire wrap wiring of the LTCC Timing Signals on the CTMBD's for Tier 2-3. Tier 3 is finished and the high eta Tier 2 is finished. The two low eta Tier 2 CTMBD's still need the LTCC timing signals added. Gave a talk in the Run Meeting about the status of the L1 and L15 projects. L1 Tier 1 Cal Trig continues running OK. Trigger Tower -11,10 HD has drifted up a couple of ADC counts since yesterday. Clearly it has a bad mono cap. As soon as Dan Owen makes some more pulser runs next week we can turn Tier 1 back off and slow down the blower to get ready to install the new Term-Attn's. Dan Owen gave me a copy of a note that explains about setting up Shea Console Parameter Pages. He has made Shea Console Parameter Pages for our L1 rack voltage monitoring. He tested them on his VAXstation running a remote Shea Console via a VAXstation in the control room from the d0tokensun. .............................................................................. Date: 2-SEP-1993 At: Fermi Topics: Pull power Pan PDM #17, repair CTFE cards, make a Find_DAC run, check for water leaks, remote voltage reading, verify that the Rack_Voltage_Monitor cables are OK. Give up and pull Power Pan PDM #17 from the lower Tier 1 in M112 and install Power Pan PDM #8. Also had to replace the fuses in the power contactor box for M112 lower Tier 1 receptacle before the new Power Pan would work. A number of CTFE cards had pedestals that had drifted out of control because of leaking monocaps. These were repaired in the now standard way of cutting out the old caps and soldering the looped leads of the new cap to the pads on the CTFE card without removing the solder from the PCB via with solder-wick. The cards repaired are: -14,6 HD CTFE SN #286 -14,22 EM CTFE SN #297 +17,23 HD CTFE SN #285 +17,23 EM CTFE SN #285 +18,18 HD CTFE SN #266 +19,32 EM CTFE SN #321 After all of the Tier 1 crates had been powered up and running for about two hours I started a Find_DAC run over the full eta range. This finished in about 50 minutes with a 6075 block file (which I left on TCC's disk). All channels were OK except for -11,10 HD. From the course data it looks like this channel needs a DAC value of 17 so I set this in the Init_DAC_Bytes.LSM file by hand. It looks like -11,10 HD is the next channel that will need a new capacitor (its old DAC value was 32). TRICS loaded the new file OK and I Initialize all Trig Towers. TrgMon ADC Counts looks fine. Copied Init_DAC_Bytes.LSM to MSU. Checked for water leaks and everything looks OK. No manifold leaks by M101 or M104 and no radiator leaks between M111-M112 or into M113. I need to get some hose clamps to properly fit the maniforlds and get a spare radiator clamp made. The following is a how to run a remote Shea Console to monitor the voltages in the Level 1 racks. "!" is used to start my comments. telnet d0tokensun ! i.e. telnet to the sun workstation that ! has the host name d0tokensun. login: operator ! The sun workstation prompts you for password: wasd0exp740 ! user id and password. d0tokensun% setenv DISPLAY node:0.0 ! d0tokensun% is the command ! line prompt from the sun. ! This line is case sensitive. ! node: is the host name where ! you want windows to start ! appearing. Note that there is ! only one ":". ! I believe 0.0 shows the ! X_server_num.screen_num. ! Use a TCP/IP host name, ! e.g. msuhe4.pa.msu.edu:0.0 ! or d0hs14:0.0 d0tokensun% xvindex ! This will cause a new window to appear on the ! machine that you specified in the preveious ! command as node:. ! You now have a window on node: with a bunch ! of "clickable" buttons in it. click on the OPT button ! This was cause a password prompt to ! appear. ! Use Mouse Button #1, i.e left button ! for normal right handed mouse setup) password: tiger ! A small window appears where you Enter ! the password in small characters, click on diagnosing_controls ! you now get a new window with a menu click on page_G_launch ! you now get a new window with a menu click on 74D ! This is the high order part of the ! address of our Shea monitor crate. ! You now will get a window that looks like a ! Shea monitor console. We do not have any ! parameter pages setup on the Shea Console yet ! so you need to enter the names of things that ! you want to see by hand. Have copies of ! TrgHard:[Rack_Voltage_Monitor] E360.DAT and ! Data_for_Hardware_Database.Txt available to ! read to get the "names" of this to enter in the ! left hand column of the Shea Console. Mike ! should be able to help with this part. ! When you are finished go back through the ! menus clicking on the quit buttons. ! 21-SEP-1993 UPDATE: first successful session on MSUHE4, the ! parameter pages are now setup. Typing in the window brings a ! menu with a list of page numbers to select from: use the up and ! down arrow keys and to select a different parameter page. ! ! Note that the Shea console window is running independently and ! that all the other xvindex windows can be closed (quit buttons) ! and the session on the sun can be closed (d0tokensun% logout). ! To exit the Shea console, type ! To make the xvindex program send its display on MSUHE4, the ! "Security" item of the "Session Manager" menu "Options" needs to ! be updated to allow ! Node: d0tokensun.fnal.gov ; username: * ; Transport: TCPIP ! Also the "lucida" fonts need to be aliased to a DECWindow font. ! $ COPY DECW$EXAMPLES:DECW$FONT_ALIAS_LUCIDA_100DPI.DAT - ! SYS$COMMON:[SYSFONT.DECW.USER_100DPI]DECW$FONT_ALIAS_FILENAMES.DAT ! $ COPY DECW$EXAMPLES:DECW$FONT_ALIAS_LUCIDA.DAT - ! SYS$COMMON:[SYSFONT.DECW.USER_75DPI]DECW$FONT_ALIAS_FILENAMES.DAT ! And the session needed to be restarted. As we turned on the 20 Tier 1 Power Pans Dan Owen watched from the McIntosh Parameter Pages that he make for L1. All of the Tier one supplies look OK in the rack voltage monitoring. Also the L1 FW and the L15 FW and the M114 supplies all look OK. Only the four Tier 2-3 pans have yet to be checked. .............................................................................. Date: 1-SEP-1993 At: Fermi Topics: Bring spare cards to Fermi, Bring power bricks to Fermi, CTFE channels that need work, LTCC cables, work on Tier 1 Power Pans. Bring to D-Zero Hall the following spare cards. I need to add these to the inventory last of spare cards at Fermi. CAT2's with T2 ECO SN #226 and SN #270 CAT3's with T3 Px Py sign extend ECO SN #15 and SN #19 To work on the Tier 1 Power Pans that need repair I brought to Fermi the following bricks: 5V 600A SN #5 4-OCT-1990 2V 250A SN #16 9-NOV-1988 The following CTFE channels need work: -14,6 HD reads 95 counts -14,22 EM reads 104 counts +17,23 HD reads 55 counts +17,23 EM reads 30 counts +18,18 HD reads 108 counts +19,32 EM reads 94 counts On Power Pan PDM #21 pull out the failed +5V 600A supply brick #15 and install brick #5. Now PDM #21 in the top Tier 1 of M108 appears to be working OK. On Power Pan PDM #17 pull out the failed -2V 250A supply brick #63 and install brick #16. -2V brick #16 is an old model PM2500A-2. It appears to have no soft start turn on delay. It appears to come on instantly. This appears to keep the +5V brick from every starting its inverters. Across the +5 test points there is about -0.3 or -0.4 Volts. I play around a lot turning things on and off and finally I blew the fuses in the power contactor box. Two of the three fuses blew. Turning the Power Pan back on before the thermistors had cooled down causes the fuses to blow. My only idea is to pull -2V brick #16 and swap it with the -2V brick at MSU test rack. Dress in the LTCC cables in the front of the racks. Recall that Large Tile Reference Sets 0:3 will come from the Py cards and LT Ref Sets 4:7 from Px. .............................................................................. Date: 26-AUG-1993 At: MSU Topics: Getting ready to install LTCC Timing Signals: A new Timing Specification File was made for the PROM #4 in the Cal Trig MTG. This new Timing Specification File has defined MTG Channels #30 and #31 for use with the Large Tile Trigger Cards. This new part is Revision M of this part. The old part was Rev L. The new file is: Cal_Trig_MTG_PROM_4_SN_4M.TSF this makes CalTrg4M.Dat This TSF was copied to D-Zero Hall. COMINT Address Specification Files: The TWO COMINT version of the Address Specification Files now include the full proper entries for the Large Tile Trigger Cards. Only the CBus 2 file needed to be edited today to include the LTCC cards. This involved changes on pages 32 and 33 of the CBus #2 file. These files are: July_1993_CBus_0_of_4.asf July_1993_CBus_1_of_4.asf July_1993_CBus_2_of_4.asf July_1993_Block_Structure.Txt No ".DAT" files were made. All of these files were copied to D-Zero Hall. Next the CBus 0 Address Specification File for ONE COMINT operation was modified to include the proper information for use with the LTCC cards. This involved changes to pages 107 and 108 of the file for CBus 0. The new file is: August_1993_CBus_0.ASF This was copied to D-Zero Hall. No ".DAT" files were made. .............................................................................. Date: 23-AUG-1993 At: MSU Topics: L1 Cal Trig problems. By doing TrgMon from MSU the following problems were discovered: The upper Tier 1 in M108 has a bad +5V brick. This brick causes the breaker on this power pan to trip off. This pan is turned off and will remain off. Note that this is in addition to the -2V problem in lower Tier 1 M112. The following single channels have problems: +18,18 HD shows 105 counts +17,23 HD shows 52 counts -14,6 HD shows 98 counts -14,22 EM shows 91 counts The rest of L1 Cal Trig looks OK. .............................................................................. Date: 19-AUG-1993 At: Fermi Topics: Turn on L1 Cal Trig Tier 1, Power Pan Problems, Water Leaks Turn on L1 Cal Trig Tier 1 The water leak under M101 appears to have been fixed by putting on hose clamps. A new water leak in M113 was found. This is a second leak directly from the copper end cap on the radiator. Dan Owen fixed it with a "C" clamp. John from the mechanical group made an official clamp for it like the clamp on the M111-M112 radiator. Christenson wants to pull the radiator and to dissect it. All of L1 Tier 1 turned on OK. After about one hour the -2V supply for eta -17:-20 phi 17:32 died. To keep things running I pulled out the CAT2 cards from this cell and all worked well for another couple of hours and then the -2V supply died completely. So for now the lower Tier 1 in M112 is turned off. This is Power Pan PDM#17. The -2V brick in this pan had trouble before when it was at Fermi but then the brick tested OK here at MSU so it was shipped back to Fermi. I think that I want to do a brick swap at Fermi. The CTMBD is pulled from this crate to keep the CBus running OK with this crate powered down. The Trics_Boot_Auxi.Dat file was changed so that at Init time Trics would wake up the full eta coverage -20:20. A pedestal run was make. Peds may have moved a lot because of all the BLS work. After loading the new Peds and then looking with TrgMon ADC Counts all looked OK. The VTC 68k was loaded with the version that transfers data from all eta's i.e. no zero energy response values are being forced into the data block. Both the all eta's and the eta only out through 3.2 version are still available in TrgCur: The Temp and Air Flow with the fan at full normal speed, all of Tier 1 on, all Tier 2-3 Power Pans pulled out looks like: Water Diff Air Lower Three Air Temp Pressure Thermometers Speed ---- -------- ------------------ ----- 55.2 1.29 59.2 59.0 58.9 310 .............................................................................. Date: 18-AUG-1993 At: Fermi Topics: Trigger Certification Board meeting, A Thought about L15 CT, L1 Water Leaks, Get ready to power up L1 CT Temp air flow measurements at low fan speed. At this morning Trigger Certification Board meeting Mike Fortner gave the estimates that run 1b would begin with 160 Hz from L1 and 3 Hz from L2. L15 CT is its processing speed deterministic? Long time an no Trig's, then a pure L1 fires plus an L1 that requires L15 CT for confirmation, then 15 usec later a L1 fires that again requires L15 CT for confirmation. The L15 CT will not start working on the time critical second event until it finishes the not time critical firist event. The elapse time from the L1 firing on the 2nd event until L15 CT finishes processing the second event is not deterministic because you do not know how long of a wait there will be from the firing of the 2nd L1 trig until L15 CT starts to work on it. It depends on the recent history. There water leak under the lower power pan in M104 was worked on today. The problem is the plug end of the manifold in M104 nearest to M105. I was able to tighten the plug at least 2 turns and it still dripps about one drip every couple of minutes. Before I tightened this plug it dripped one drip every 10 seconds or so. I'm going to turn things off, pull this pipe plug out, add more Permetex II and a pipe clamp around the manifold. The power bars in the bottom Tier 1 in M111 and M112 were reinstalled (two bars). The patch on the radiator between M111 and M112 looks fine. Blank panels were put where the Tier 2-3 Power Pans normally are. The Tier 2-3 AC and DC Power Pan cables were tied up out of the way. Resistance check all of the Tier 1 Power Pans. Glue the broken breaker handle on the upper Tier 1 Power Pan in M107 (this is PDM23). The epoxy did not hold. I need to order a spare breaker to bring to Fermi. Tagged off the Tier 2-3 plugs. Temp air flow measurements at Low fan speed, all of Cal Trig OFF, and all of the Tier 2-3 Power Pans pulled out. Water Diff Air Lower Three Air Temp Pressure Thermometers Speed ---- -------- ------------------ ----- 55.2 0.66 57.5 57.5 57.0 200 55.6 0.66 57.7 57.7 57.3 200 .............................................................................. Date: 6-AUG-1993 At: Fermi Topics: Re-meeting with Steve P (UCI), return items on FNAL loan agreement, measure avail. space in M124, Maris/Dan meet with Jim C re: money, order all off-the-shelf VME modules for 1 L15 CT Crate + 1 test/development system. The two Steves talked again today about technical issues (primarily the maximum timing skew we will guarantee between the "ERPB Controller" MTG and L1 CalTrig MTG cables. We also talked about the rack-to-rack skew, and the skew along one backplane. MSU will guarantee that the skew between the L1 Cal Trig MTG (as measured at the input to the CTMTG) and the ERPB Controller MTG (as measured at the input to the Distributor Cap) will be no more than 5 ns. Dan and Steve returned items which had been on loan to MSU from FNAL on agreements #201 and #205. After returning the below-mentioned items to PREP we asked Barb E (at D0) to have these items removed from their respective loan agreements. Items returned to PREP: Loan Agreement #201: ------------------- Manuf/Desc. Model S/N Prop. Number ----------- ----- --- ------------ BiRa IORFI SN001 P44106 Loan Agreement #205 ------------------- Manuf/Desc. Model S/N Prop. Number ----------- ----- --- ------------ Kinetic Systems F010-A03 SN0030 P07426 Kinetic Systems F011-A03 SN55 P07427 Fastbus Blower 8162 SN1864 P09267 Fastbus Crate 8159 SN2727 142A 45369 Fastbus Power Supply 8161C SN1817 45370 (includes 3 power 190455 P09427 supplies) 263943 P09426 190536 P09425 This should close Loan Agreement #201. One item remains on Loan Agreement #205: a DEC DRV-11J card (with FNAL property number P07777). This item is probably in one of the Trigger Control Computers but we do not know which one and do not wish to dismantle any of the working TCC's just to find out. The available space in Rack M124 is 66.5" x 19". To fully use this space, a new door-mounting mechanism must be used (this is not seen to be a problem, as we will probably want c-channels on the rack anyway, requiring new door- mounts). Dan and Maris met with Jim C about money. D0 Management wants us to: 1. Order as much as we can through Fermi Purchasing right now. 2. Get an Addendum to them for the money that will need to go to MSU for the L15 Cal Trig. 3. Work with Hugh Montgomery to understand the money situation at UCI and get an arrangement setup for the money that they will need for their work. 4. Take responsibility to monitor ALL purchases of material for the L15 Cal Trig to confirm that D0 is purchasing what is needed. 5. Help define and setup the arrangement where by UM tests cards designed and built at UCI. Dan ordered off-the-shelf VME modules for L15 CT through Fermi Purchasing: Qty Order #1 Items Qty Order #2 Items --- --------------------------- --- --------------------------- 4 MVME214 Memory Module 1 C40-ASM C40 Assembler PC 2 MVME135-001 CPU Module 1 C40-SIM C40 Simulator PC 2 MVME135BUG Monitor 1 AXDS-PCX C40 Debugger JTAG 1 HY2B-4-S1 Hydra II module Qty Order #3 Items Qty Order #4 Items --- --------------------------- --- --------------------------- 5 Ironics IV-1623 Dig IO 3 HY2B-4-S1 Hydra II module .............................................................................. Date: 5-AUG-1993 At: Fermi Topics: TUG Meeting, L15 CT Meetings with UCI and Linnemann, Replace Power Bricks in M114 Power Pan, CAT2 and CAT3 cards returned to MSU. In the M114 Power Pan the two brick that belong to the Fermi Prep Fast Bus Power Supply were removed. They were replaced by brick SN #50 for the +5V brick (near the back of this Power Pan) and brick SN #87 as the -5.2V brick (near the front of this Power Pan). After running for perhaps 5 minutes the voltages were checked: +5V is 5.076 Volts at the pan test points and is 5.032 at top of bars. -5.2V is -5.203 Volts at the pan test points and is -5.146 at top of bars. CAT cards are being returned to MSU (one CAT2 as a model to make two additional full ECO CAT2's and two CAT3's to receive the ECO for spare Tier 3 Px,Py CAT3's). Their Serial Numbers are: CAT2 SN#100 and CAT3's SN#15 and SN#19. Dan and Steve went with Maris to the Dan Owen TUG meeting at which we presented the "framework-y" parts of the L15 CT (i.e. Data Block, crate organization, COOR communication, algorithm-to-term mapping, etc.). Minutes of this meeting taken by Dan O and are released as D0 News. UCI people were at this meeting. Dan and Steve convened a smaller meeting with UCI people (Steve P and Andy), which Rich G also attended. Drew Baden was also around for the beginning of the meeting. Results of the meeting are summarized: 1. Everyone talked about the requirements for testing the ERPB cards. Drew B volunteered Maryland as the vendor for this testing. It was suggested by Dan and Steve that, although a CTFE card could be used as a "test driver", this would be difficult in practice. Use of "off-the-shelf" parts was recommended. Baden will talk more with UCI people re: testing. 2. MSU and UCI then talked about detailed design of ERPB. - Dan and Steve recommended that any programmable logic devices (i.e. Xilinx) parts not be run at 99% capacity (either logic cells or I/O's) to allow for future expansion. This was received well by Steve P. - Steve P will explore "dumb" double-buffering on the ERPB directly. - Steve P will explore the question "how many timing signals are enough?" It is hoped by all that 10 will suffice. - ERPB will have "data cable," daisy-chain cable, and "parallel" timing and control cable (from Distributor Cap). - MSU is contracted to build the "ERPB Controller" which will provide all timing and control signals needed by the ERPB. This can be just a MTG. If only 10 signals are needed then 1 MTG can make all 10, three times ( |ETA| 0..8, 9..16, 17..20). We will "match skew" with the existing TSS cables. - UCI is contracted to build the "Distributor Caps" which are intermediate fan-out device for the above-mentioned timing signals - MSU will explore the "input FIFO on CRC" question. Considerations: does it help? When things screw up is it impossible to recover? - Steve G will send all info he has on ECL drivers/receivers/convertors to Steve P. It is not yet decided what standard to use for the ERPB-to-CRC cables but differential ECL looks promising. We need to find "small-outline" TTL-to-ECL convertors for efficient space usage on ERPB - Current maximum ERPB depth is approx. 9". - Steve G will provide Steve P with better measurements, drawings, and photographs of a L1 CT Tier 1 crate. .............................................................................. Date: 30-JUL-1993 At: MSU Topics: Power Supply Bricks - Return FastBus To get ready to return the Fast Bus equipment that MSU had borrowed from Fermi Mike test three of our power supply bricks (one 2V brick and two 5V bricks). We need these bricks to replace the three bricks from the FastBus crate power supply that we are currently using in our L1 Trig equipment. The FastBus -2V brick is currently in the MSU Test Rack Cal Trig Test Cell Power Pan and the two 5V FastBus bricks are currently in the D0 Hall M114 Power Pan. I need to return these FastBus bricks along with their FastBus power supply because these FastBus bricks have Fermi Inventory Tags on them. Our brick SN #54, a 2V brick, was tested and then installed in the MSU Test Rack Cal Trig Test Cell Power Pan. The 2V FastBus brick was pulled out of this Power Pan and re-installed in the FastBus power Supply. Our brick SN #50 and our brick SN #87, both 5V bricks, were tested and SN #50 was set to 5.075 Volts and SN #87 was set to 5.200 Volts. These two bricks will go to Fermi to replace the two FastBus bricks that are currently in M114. .............................................................................. Date: 15-JUL-1993 At: DZero Topics: Current cards and status of M114 and Tier III, Current layout in M124, Air Blower pressure and vacuum, Install the Large Tile Cables I checked the current status of M114 and I found that in the lower backplane the lowest 4 slots have been cut free from the Specific Backplane CBus etch. The current cards are: UPPER M114 LOWER M114 ------------------------- ------------------------- Slot Card Slot Card ------ ---------------- ------ ---------------- 11:20 Bus Buffer Board 20 open 10 MTG Cal Trig 11:19 Foreign DBSC 9 Special I/O MTG 9:10 open 8 MBD 6:8 DBSC L15,States, 7 MTG Framework 5 CTMBD The front CBus cable 3:6 Bus Buffer Board has 5 connectors in front. 2 COMINT 4 AND-OR Buf Ref Set 1 open 1:3 open I checked the cards in the M107 Tier 3. They currently are the following: Tier 3 M107 ------------------------ Slot Card ------ -------------------------- 26:27 Px and Py CAT3's with ECO 23:25 open 22 HD1 0...3 CAT3 no Term 21 HD2 0...3 CAT3 20 EM2 0...3 CAT3 no Term 17:19 open 16 EM1 0...3 CAT3 8:15 Tower Count CAT2's 7 open 6 FMLN 4:5 open 3 Tot Et 1 0...3 CAT3 2 Tot Et 2 0...3 CAT3 1 CTMBD Large Tile Cables All of the Large Tile cables (Tier 2 and Tier 3) were installed through the back cable clamps and into the racks. The paddle cards are not yet installed and the cables have not been brought down the front of the racks. Air Blower When the new air blower was at full speed it showed 0.55" Vacuum and 0.70" pressure. Now running at the slower speed it shows 0.26" Vacuum and 0.40" pressure. The other difference is that all of the Tier 2 and Tier 3 Power Pans are currently pulled out for Large Tile modification. .............................................................................. Date: 14-JUL-1993 At: DZero Topics: TUG Meeting, Addendum to the Memorandum of Understanding, Plug in the Rack Voltage Monitor Cables, Order the 1st C40 Development equip. There was a TUG meeting today. The UCI people were not there. Mostly software people and Mike Tuts. Questions or points: 1. How to force the L15 framework to confirm an event that the L15 Cal Trigger has done a 1 of N mark and pass on?? Force the L15 Framework Terms to YES but report them differently in the L15 Data Block? Use a "special" L15 Framework Term? 2. Want more than the Edmunds-Gross 3 lines to select the "algorithm". They for rational reasons want 8 or 9 lines. I explained and they understand that "algorithm" can mean different L1 Tower selection, different Local algorithm, different Global algorithm; and that "algorithm" often means the "same algorithm" with different parameters e.g. threshold cuts or counts. These lines that wake up the "algorithms" need to be able to touch all levels; Local, Global, L1 Tower Select. 3. Does each "algorithm" have its own L15 Term? Are a subset of the 8 L15 Terms that belong to Cal Trig L15 permanently bound to one of the two L15 VME crates??? No we want either of the two crates to have access to all 8 of the Cal Trig L15 Terms. 4. Also from the point of view of COOR is a given L15 Term permanently bound to something like an L15 DSP executable? If not bound and if at down load time COOR can assign an one of the 8 Cal Trig L15 Terms to a given "algorithm" then how is this done; L15 Framework function?? 6. When Loading Parameters from COOR; how do we get a given parameter to its proper "algorithm" ?? When moving from COOR to TCC to parameters have: ID's, Addresses, and Values ?? 7. If for a given event a given L15 Cal Trig crate is to run 2 (or more) of its possible "algorithms" then they should know how to cooperate. If there are for example to count-energy cuts at the Global stage this is easy; do them in series. If there are 2 different cuts at the Local level e.g. two different ratio cuts on the electron 3-5 algorithm then it is stupid to run them in series; i.e. once the 3x3 of EM and the 5x5 of Total are calculated then make both ratio tests or make only the easier on to satisfy. The point is that these two Local "algorithms" should not run is series but should cooperate at execution time if for a given event they both need to run. Unlike in L2 these different "algorithms" are probably not separate "EXE's" but because they need to cooperate at execution time they are probably "one program". MONEY and ORDERING News. The $52k of upgrade money to build the Large Tile and the 350 Hz readout has been found at MSU in a different account number! Thus we are not $22k in the hole but we have just enough to make wages until Oct 1st. Today two Addendums (Addendi) to the Memorandum of Understading between MSU and Fermi were put through. One for $18,794 to cover overruns in the Large Tile project (the original MS for Large Tiles was only $4k and we have spent $20k on Large Tile parts so far). The second Addendum is for maintenance work for $26,206. This covers Rack Voltage Monitoring, new Term-Attns, and software maintenance (adding alarms). Today I ordered the first C40 card and software development tools through Fermi Purchasing. Today Mike plugged all of our Rack Voltage Monitor cables into the Shea 1553 rack monitor modules. So far all is OK. The readouts tested so far are OK. Mike is putting our data into the Frontend and Hardware databases. .............................................................................. Date: 13-JUL-1993 At: MSU Topics: Data Block Version Number for run Ib The Version Number is stored in longworkd #4 of the Data Block (cf. Note 967) The Version Number used during run Ia and still in use at the moment is 6. The Version Number that will be used during run Ib will be 9. The new release of L1SIM will use Version=9 when it does not build Jet Lists, and version=7 when it builds Jet Lists. Version=8 will be reserved as intermediate step for VTC if needed. Version Jet Lists Large Tile Pulser ------- --------- ---------- ------ 6 Y N Long Current 7 Y Y -- used in L1SIM when Jet Lists are created 8 N Y Long reserved for VTC if intermediate step is needed 9 N Y Short run Ib .............................................................................. Date: 9-JUL-1993 At: MSU Topics: Edit Rack Address Files, Backplane Description Files for M103 and M114, delete the obsolete backplane description files, list of thing to check on the next trip to D0 Hall. Dan, Steve, and Kelly edited all 13 Rack Address for Rack M1** files in TRGINTR to include LTCC and Pilot/Assistant COMINT and Kelly edited the InterGraph rack layout file which he will also plot. Dan and Steve edited the TRGHARD:[MISC] files describing the upper and lower backplanes for Rack M114 (RACK_M114_{UPPER/LOWER}_BACKPLANE.TXT) to show the proposed configuration for Run Ib including Pilot/Assistant COMINT. The following obsolete files were deleted from TrgHard:[Misc] both at MSU and at D0 Hall: OLD__FILE__M103_M114_BACKP.TXT RACKS_M103_M114_BACKPLANES.TXT RACK_M114_BACKPLANE_HACKS.TXT For information about the M114 backplanes see the above-mentioned M114 files in TrgHard:[Misc] and in TrgIntr:. For information about the M103 backplane see the files in TrgExp: for the IMLRO Readout section and see the files MSUTRGROOT:[D0_TEXT.LEVEL_15.FRAMEWORK] for the details of the Level 1.5 Framework section of the backplane. On the next trip to Fermi Dan will check the following: What CAT's are actually installed in Tier 3. Check the lower few slots of the lower M114 backplane to see if the specific backplane CBus is connected to these slots. Check the upper and lower M114 backplanes to see where the And-Or buffer cards are installed and where the Special I/O MTG card is installed. What DBSC are actually installed in the lower M114 card file. .............................................................................. Date: 8-JUL-1993 At: MSU Topics: Deliver the LTCC Heathkit to Mitech, coordination meeting with Steve and Philippe. Mike and Kelly delivered the LTCC Heathkit to Mitech. Meeting with Philippe and Steve about this summer's projects: 1. Tentatively select Ariel Hydra II vs Sonitech Spirit-40 VME Dual TMS320C40 6 COM Ports per DSP vs Spectrum CV2 Dual TMS320C40 4 COM Ports per DSP Letter to Ariel Start orders with Ariel 2. Tier III - Tier IV - IMLRO readout - FMLN - Decide that Mon Pool Options Refresh and VTC will Conflicts vs LTCC cards slots, T&SS pull 50 counts from Selection for run 1b EM & HD, 1st & 2nd LU. 3. Considerations before Philippe's exit (what can we do to help while he is gone?): LTCC code new uVAX code Two COMINT code New HD PROM's (how to get EM out of CTFE Tot Et spigot Define L15 Cal Trig: COOR to L15 Cal Trig Params In L15 Data Block Out 4. Coordination with Steve (Philippe too): CAT Paddles for LTCC (can Kelly set this up?) Rack Layout Text Files and Rack Layout Blue Print Intergraph File (work with Kelly): Add LTCC cards ReNumber the CBusses (Pilot COMINT 0:1, Assistant COMINT 2:3) Add 2nd COMINT and labels Pilot and Assistant Confirm/Add the AND-OR Card to "buffer" the Large Tile Ref Set Rework the M114 upper BACKPLANE description text file. Work on the definition L15 Cal Trig control logic flow so that work can start on the Ironix I/O P2 cards with Jim Linnemann student Rich Genik. .............................................................................. Date: 30-JUN-1993 At: D0 Topics: TUG Meeting, water leaks, Tier 2-3 Power Pans, Cable Bridge, Spare belt, Fan specs, L1 is running There was a TUG meeting and various pre-TUG meetings. Uli-Meena do not want to manage the L15 CT or build any hardware. Dan Owen will be the L15 CT manager. No work was done on the M101 water leak. The M111-M112 leak had the clamp patch installed. It had not been tested by the time that we left. Tier 2-3 power pans from M106 and M108 were removed and brought back to MSU to receive their new +5 Volt bricks. These are SN MM1 and MM7. Note Tier 2-3 Power Pan serial number MM5 and MM6 do not exist; MM1, MM2, MM3, MM4, MM7, MM8 exist and are now all at MSU. A BX53 belt was left at D0 Hall. It is not clear if we need to install it or not. Even with the new smaller motor pulley at its largest diameter the fan is not very noisy. During normal full speed fan operation it requires a BX 56 belt. Our new fan is: AEROVENT Fan Model: 25T734 TTABD - 1786 5 Subsidiary of FLAKT Type: TTABD 1 Aerovent Drive Serial No: 4098180 19040-TVW48 Piqua, Ohio 45356 The cable bridge for the Voltage Monitoring Cables and the L15 Cal Trig Cables was installed. The L1 Framework, Framework Expansion, and M114 are now running again after the shutdown for Stony Brook and the power reduction. L1 Cal Trg is OFF. .............................................................................. Date: 22/23-JUN-1993 At: D0 Topics: Dan and Mike at D0 Hall; Install the Voltage Monitor Cables, Pull Tier 2-3 Power Pans, Slow down the Blower, Fix the cable tray, Talk with Fred Borcherding about the setup of M124. All of the Voltage Monitor cables were installed into our racks. The only problem is the +5V and -5.2V connection to the Tier 2-3 backplanes. We will make these 8 connections on the next trip using AMP crimp contacts and housings. All of the Voltage Monitor cables were left up on top of our racks in coils except for the cable to M114 which has been run over to M124. M124 has its new hatch cover installed with the cable clamps. The two junction boxes are installed on top of this cover. We pulled the Tier 2-3 Power Pans from racks M112 and M110. We also brought back to MSU the last spare Tier 2-3 Power Pan. The only Tier 2-3 Power Pans left at D0 are in racks M108 and M106. There are now 4 Tier 2-3 Power Pans at at MSU. The Tier 2-3 Power Pans that we brought back to MSU are: MM2, MM3, and MM4. The Tier 2-3 Power Pan that was already at MSU is: MM8. The blower was slowed down. Some funny set of parts had been purchased to do this (including a new smaller pulley for the blower shaft). Only the motor pulley was changed. The belt that they had was too long to adjust the new motor pulley to its smallest diameter. To get things running with this too long belt the new smaller motor pulley was adjusted to its biggest diameter. John M (from Dell's group) kept the old parts. I told him that we will need them again in September. They had moved the HV racks (including M114) in toward the center by 2" by the time that we got there. The cable tray that crosses the aisle at the West end was hung up on the front build out on M114 and pushed the cable trays along the back of our racks out 2". This was quite obvious from the bent 1/2" threaded hanger rods. Talked with Fred Borcherding about the setup of M124 and the cable bridge. He will have Don Emery work on the setup of M124 (rmi,1553,power box, water, radiators, air). We both thought that a bridge from M106 to M121 was OK. .............................................................................. Date: 22-JUN-1993 At: MSU Topics: Make directories and move files from MSU to D-Zero Hall. At D-Zero Hall I made the subdirectories, TrgHard:[Rack_Voltage_Monitor] and [Prog_Dev.LTCC]. I copied all of the files from MSU into these new subdirectories at D-Zero. I also copied from MSU to D-Zero Hall all of the files for TrgHard:[LTCC]. The TrgHard:[LTCC] subdirectory already existed. .............................................................................. Date: 20-JUN-1993 At: MSU Topics: Stony Brook Workshop, L1 Readout Rate Upgrade, Present the DSP based L15 Cal Trig, Visit to Ariel On 13-June-93 Philippe and Dan went to the Stony Brook Workshop. The presentation of the DSP based L15 Cal Trig was given on the morning of the 14th. On the 15th we found out from Dean that sometime in the past couple of weeks that the decision had been taken to ask L1 to speed up its readout rate (but no one ever told us). On the afternoon of the 16th we visited Ariel in Highland Park, NJ. We came back to MSU on the night of the 16th. .............................................................................. Date: 19-MAY-1993 At: D0Hall Topics: May-1993 Term-Attn Resistor Order, Move out of the house, Inventory of spare boards at Fermi, L15 Cal Trig parts thoughts. May Term-Attn Resistors The data from D0 Note 1707 was converted into resistor values. All of this is in DEPT:[Edmunds.Term_Attn_Networks.Al_Networks________MAY_1993] It is not in the Trigger account at MSU or Fermi. Moved out of 18A Sauk. Maris will ask Bekey to remove the 18A Sauk phone number from the call list. From now on if we are here in a dorm room or at the Best Western then the initial call will most likely go to Lansing. The person in Lansing who answers will need to tell the D0 Control Room to call Best Western or the Fermi Housing Office (Communication Office) to find the person down here. Inventory of the Spare Cards at Fermi on 19-MAY-1993 This is in the new file TrgBook:D0_Hall_Spare_Parts_Inventory.LBK I copied this to MSU where the master will be kept. This file should be (will be) maintained. L15 Cal Trig thoughts 1. What are the best DRIVER and RECEIVER IC's to use to go from the paddle-driver cards, CTPD, to the IDT mezzanine memory cards, CTMM. 2. What are the best CABLES and CONNECTORS to use to go from the paddle-driver cards to the IDT mezzanine memory cards. High density cables, 20 mil pitch or 2 mm pitch, the small SCSI stuff, or surface mount stuff, or ... 3. The "standard" connector setup to go from a VME card to a mezannine level on the card is called SCIM for Standard Computer Interface Module bus. I do not know if this is a physical or electrical (or both) specification. I'm certain that there are specialized mezannine layer boards (e.g. for some processors boards) that are not SCIM standard. 4. Is there an IEEE DSP magazine or some other DSP magazine? We need to make a complete survey of who is building what in DSP land. 5. What is the company "Quick Logic"? Are they another company that makes programmable stuff of the type that we will need for the CTPD ? ............................................................................. Date: 18-MAY-1993 At: D0Hall Topics: Initial talk at the TUG meeting about the MSU L15 Cal Trig, Talk with Marvin Johnson about rack space TUG Meeting At the Tuesday TUG meeting we gave the initial presentation of the MSU L15 Cal Trigger. Hugh Montgomery was not there (he left the room before the meeting started in order to go to a different meeting). Jim Christenson did come in time for our talk. The file that I gave is VWORK1:L15_CAL_TRIG_TALK_18MAY93.TXT I will copy this to MSU VWORK1:. We do not yet have a L15 Cal Trig sub-directory because this is not yet an official project. When anyone asked anything about money the number that I used is $250k (recall this is 180 cards and a year of SWF, in fact $250k is probably too small). The description of this L15 scheme was, I think, well received. I'm afraid that Meenakshi Narain and Uli Heintz may feel bad that their hardware solution is no longer the center of discussion. Because these two people have worked to think up algorithms, tested them against data, and because they understand the L2 filter system and the L2 filter tools that will need to be modified to take advantage of an L15 Cal Trig we need to get them interested in our plan (get them to "take ownership" in the DSP based L15 Cal Trig plan). Marvin Johnson Talked with Marvin about rack space in 1st floor MCH for the L15 Cal Trig equipment. There is space in racks M120 (about 1/2 rack), and almost all of rack M124 is empty. I sent a mail message to Marvin and Hugh. M124 is directly across from M103 (i.e. eta +1:+4), M120 is across from M107 (i.e. eta +9:+12) i.e. the center of L1 Cal Trig. .............................................................................. Date: 7-MAY-1993 At: D0Hall Topics: Work on some CTFE Cards, Edit TRICS_Init_Auxi.Dat file I worked on the following 3 CTFE cards. They were checked with the pulser last week; see notes from 29-APR-93 +15,11 HD CTFE SN#361 R102 the HD- input resistor was a 1.0k ohm instead of a 1.5 k ohm. +16,16 EM CTFE SN#378 C353 the EM+ input 220 pf cap had a lead that was not soldered. The fluke said there was no electrical connection. -16,16 EM CTFE SN#211 R111 the EM- input resistor was a 3.0k ohm instead of a 1.5k ohm. Work on the CTFE from +14,7 EM that gave trouble with its pedestal on the 4th of May. This is CTFE SN#333. I pulled it and could see nothing wrong with it. To try to make certain that it does not cause trouble again I replaced both the 33 ufd tantalum cap and the 0.1 ufd cap that AC ground the DAC ped voltage. I did not replace the 1 nfd cap because I have not seen them go bad. I did soldering iron heat test the 1 nfd cap and it did not show any leakage. See notes from 4-MAY-93. As per the note from 9-APR-1993, I edited the Trics_Init_Auxi file to remove the special initialization of the Front-End Busy MTG channels #1 and #31 (all of the channel specific initialization is now taken care of by the internal TRICS initialization). Old version goes to D0 [Trg_Current. Obsolete]. New version to TCC, D0 TrgCur: and MSU [Trg_Current.DZero]. .............................................................................. Date: 6-MAY-1993 At: D0Hall Topics: Setup the Foreign Scalers to count the Active Main Ring Veto Signals, Review the wiring of the Bagby Rack (i.e. M122) to the AND-OR Network Input Term wiring and to the M114 Foreign Scalers wiring, Pull some cards from NWA, Setup Foreign Scalers for the new Active MR Veto signals Use Foreign Scalers #36 through #33 to count the number of Beam Crossings spent in the new Active MR Veto state. Connect them as follows: Foreign RCP Name in the Begin-End NIM-ECL Module to M114 Scaler Number Run Files and TrgMon Name Scalers in Bagby Rack M122 ------------------- --------------------------- -------------------------- Foreign Scaler #36 BX_Counts_of_MR_Veto_Cal_Low 9th Lemo from the top Foreign Scaler #35 BX_Counts_of_MR_Veto_Muon_Low 10th Lemo from the top Foreign Scaler #34 BX_Counts_of_MR_Veto_Cal_High 11th Lemo from the top Foreign Scaler #33 BX_Counts_of_MR_Veto_Muon_High 12th Lemo from the top The DBSC installed in slot 11 CA=32 for Foreign Scalers 36:33 is DBSC SN#06 from NWA. All 4 clock inputs are strapped together on the card. There is a 110 ohm resistor across each Gate A input. There is no resistor across any clock inputs. This DBSC will receive a copy of the DBSC Increment Clock signal from the DBSC in slot 12 above it. The DBSC Increment Clock signal is terminated coming out of this DBSC for Foreign 36:33 on the AMP hosing plugged into the backplane. To setup the TCC to put this new Foreign Scaler data into the Begin-End Run Files I did the following: Verified that the D0 TrgCur: copy of Trics_Boot_Auxi.dat was the same as the D0HTCC:: copy of this file. Copied the D0 TrgCur: Trics_Boot_Auxi.dat file to [Trg_Current.Obsolete]. Edited D0 TrgCur: Trics_Boot_Auxi.dat to include the lines: PHAT BER_DBSC 0 106 32 0 ! BX_Counts_of_MR_Veto_Cal_Low PHAT BER_DBSC 0 106 32 1 ! BX_Counts_of_MR_Veto_Muon_Low PHAT BER_DBSC 0 106 32 2 ! BX_Counts_of_MR_Veto_Cal_High PHAT BER_DBSC 0 106 32 3 ! BX_Counts_of_MR_Veto_Muon_High I also inverted the order of the Modification Notices at the top of this file to put the most recent notice at the top of the list. Copied Trics_Boot_Auxi.dat from D0 TrgCur to D0HTCC::DUA0:[Trigger] and also to MSUHEP::[Trg_Current.DZERO]. To setup TrgMon to display these new Foreign Scalers I did the following: In D0::TrgMgr::HTrgMon: I edited TrgMon_FS.RCP to include the new lines 36 ' BX_Counts_of_MR_Veto_Cal_Low' 35 ' BX_Counts_of_MR_Veto_Muon_Low' 34 ' BX_Counts_of_MR_Veto_Cal_High' 33 ' BX_Counts_of_MR_Veto_Muon_High' When exiting eve, eve must have called something special because this is and RCP file to change a number in the the \SIZE line near the very top of this file. I will copy this new TrgMon_FS.RCP from D0::HTrgMon to MSUHEP::Trigger::HTrgMon: and to D0:User1:[TrgUser.TrgMon] I "updated" the scaler documentation to include information about these new Foreign Scalers 36:33 I edited the following two files: at D0: [D0_Text.Scalers] Framework_Scalers_Non_FSTD_Cell.txt and Scaler_Assignments.Txt from the same directory. These 2 files were then copied to MSUHEP:: [D0_Text.Scalers] and the old versions of these files were deleted at both locations. Review the wiring from the M122 Bagby rack NIM to ECL to M114 scalers module. Recall that the Lemo on the Module to pair number on the 17 pair twist and flat is the following: Top Lemo is pair #17, the bottom Lemo is pair #2 and pair #1 is not used. NIM to ECL Pair on Module Lemo the 17 Connector Pair Cable What signal is it. Where does it go. ------------- ----------- ------------------------------------------------- top 17 Reset BX Count into MR 29 cycle to Foreign #4. 2nd from top 16 L0 Fast Z Good to our scalers. 3rd from top 15 Not connected to any of our stuff. Mod Ch in use. 4th from top 14 Not connected to any of our stuff. Mod Ch in use. 5th from top 13 Qty #3 to the per Bunch Luminosity Scalers. 6th from top 12 MRBS_Loss signal to Foreign Scale #1 Gate A. 7th from top 11 MicroBlank signal to Foreign Scaler #2 Gate A. 8th from top 10 MRBS_Loss .or. uBlank to Foreign Scaler#29 Gate A. 9th from top 9 MR_Veto_Cal_Low to Foreign Scaler #36 Gate A. 10th from top 8 MR_Veto_Muon_Low to Foreign Scaler #35 Gate A. 11th from top 7 MR_Veto_Cal_High to Foreign Scaler #34 Gate A. 12th from top 6 MR_Veto_Muon_High to Foreign Scaler #33 Gate A. 13th from top 5 NC 14th from top 4 NC 15th from top 3 NC 16th from top 2 NC Review the wiring of the Bagby M122 Main Ring Veto signals to the And-Or Network Input Terms: NIM to ECL Pair on Module Lemo the 17 And-Or Term Current Connector Pair Cable Number And-Or Term Name ------------- ----------- ----------- ----------------------------- top 17 120 MR_CAL_LOW 2nd from top 16 121 MR_MUON_LOW 3rd from top 15 122 MR_CAL_HIGH 4th from top 14 123 MR_MUON_HIGH 5th from top 13 124 MRBS_LOSS 6th from top 12 125 MICRO_BLANK 7th from top 11 126 MIN_BIAS 8th from top 10 127 LV0_HALOP 9th from top 9 116 MR_PERMIT 10th from top 8 117 MR_SPARE_10 11th from top 7 118 LV0_HALOPB 12th from top 6 119 MR_SPARE_12 13th from top 5 Not Connected 14th from top 4 Not Connected 15th from top 3 Not Connected 16th from top 2 Not Connected Pull some cards from NWA: We needed a DBSC card some I pulled some useful cards from NWA and made an inventory of what is there. I took the following: Card Type SN Destination New Use Old Use and Location ------- ---- ----------- ------------------ ------------------------ DBSC 02 D0 Hall Foreign Scaler Raw Trig CA47 10th slot DBSC 01 D0 Hall Spare DBSC Trig Out CA49 12th slot DBSC 06 D0 Hall Spare DBSC Trg # ? CA44 14th slot COMINT 06 Rev B MSU Full ECO'd COMINT Next to the bottom slot On 31-JULY-1992 I had taken and IMLRO from the 8th slot from the top. I also took from NWA and old Rev A COMINT for Philippe's wall and two old CTFE Test Cards for the scrap box at MSU. This leaves at NWA: 1x Rev A BBB, 3x MBD's (MBA 132, 135, and ?), 1x MTG, 8x TLM, 2x FSTD. .............................................................................. Date: 6-MAY-1993 At: MSU Topics: TCC_RECOVER_RUN for DAQEXP Philippe: - A new command file has been made for Jan G. So that the DAQEXP (after COOR dies or looses run control) can ask TCC to write a Begin/End/Pause/Resume Run/Store file. She also has a file from Stu to let Norm's luminosity server know about the file. USER1:[TRGUSER.DIRECT_TO_TCC]TCC_RECOVER_RUN.COM .............................................................................. Date: 5-MAY-1993 At: MSU Topics: change INIT_DAC_BYTES.LSM Philippe: - Today was accelerator study day. TCC was rebooted to pick up new system with fix in ITC (for "recovered" channels and "truncated" flag) and increased system parameter (Ports, after Fritz' advice). - TRICS refused the DAC_BYTES file including values for the towers above eta 16, and did NOT load them. The symptoms where a large negative EM Et and HD Et in TRGMON. The ADC dump showed 0,1, or 2 in all towers. reading a couple DAC registers showed 10 which is the default value. The file was edited to remove the DAC_BYTES for eta 17..20. .............................................................................. Date: 4-MAY-1993 At: MSU Topics: Note from Joan, Trouble with +14,7 EM During the night while Joan was on Calorimeter shift she saw the pedestal of +14,7 EM go up to 2 GeV and for a while to 3 GeV. She said that it then returned to normal. In the mornig by the time that I looked it was OK. She had made some dumps of the Trig Towers during the night and +14,7 EM was showing lots of 16, some 17, and some 20. During the afternoon of the 4th I saw it go up to a pedestal count of 16. Loading 4 into its DAC instead of its current normal 28 brought this back to normal. After about 1/2 hour its zero energy responce returned to normal. Its DAC is at CBus=0, MBA=202, CA=45, FA=2. .............................................................................. Date: 29-APR-1993 At: D0Hall Topics: TUG meeting, check some CTFE's Had a major meeting of the TUG. Lots of ramdom talk. Almost no one understands Linnemann's point about any processor still needing fast access to the data. Idea of not using 640 cables but rather perhaps 10, perhaps multi-port memories. Use the test pulser and a scope to check some CTFE channels that Dan Owen says read a little off in his pulser runs. He has found not BLS problem. +15,11 HD HD- and HD+ are both bigger than they should be by perhaps 20%, HD- is 10% bigger than HD+, Fluke resistance looking into the Term-Attn is OK. +16,16 EM EM+ is only 20% of normal. -16,16 EM Both EM's are low, EM- is only 75% of EM+ .............................................................................. Date: 28-APR-1993 At: D0Hall Topics: Mark Fitzpatrick and VESDA, Repair the broken scalers, Test our VESDA Our L1 VESDA dies. Its failure light is on on the control panel on the roof of MCH. It is the head that dies. Mark Fitzpatrick has a brain dead fire tech replace the head while our equipment is running. It was an accelerator study all Wednesday today. They could have called us like the sign on the rack says. But NO, they just stood there with the door open. I wrote a note to Fitzpatrick and CCed to Abolins and Owen. The Spec Trig Fired DBSC scalers for Spec Trig's 8:11 have been running at BX rate for the last couple of days. I shut L1 off and find the problem to be the 10101 at the back of the Spec Trig 8:11 FSTD. It has lost its pin #16 connection to the GND Plain. The soldering is OK, the via has become disconnected from the plane. I repair it with jumper wires to other GND pins. This is FSTD SN#12. I turned off the L1 to do the above work via doing a VESDA trip test with the canned test smoke. It took a couple of shots, and I was not able to watch the control head but it did trip OK. I assume that they did not change the delay settings when they worked on it today. .............................................................................. Date: 27-APR-1993 At: MSU Topics: The 3rd and final (?) Abolins resistor meeting. We have the 3rd resistor meeting with Abolins showing his most recent 10% changes. Thus far we have fixed at least: include the highest eta HD, dynamic range match to 248 / 255, go for the correct Z calibration, recall the North and South eta's 5:8 currently have different Term-Attns, use the proper eta for the high eta regions (i.e. not just TT Index multiplied by 2 but for example TT 20 eta = 4.274, TT 21 eta = 4.825, and I forget whatever else. The most recent request for the values of the old (Jan 1992) Term-Attn's was on 20-APR-93. .............................................................................. Date: 26-APR-1993 Trouble at D0Hall Topics: water leak The lower radiator between M111 and M112 springs a leak. Owen powers down. Instead of just valving off this set of radiators and shutting off the high eta M112 and M113 people get excited and cut the hoses to this radiator. This is John Cornell under Owen management. We will continue to run with the 2 high eta racks powered off. See the text and drawing on page 69 of the Trig #1 logbook. .............................................................................. Date: 9-APR-1993 At: MSU Topics: Review of TRICS 4.0 new features, need to edit Trics_Init_Auxi, need to correct the Reset_L15 command. Steve and Dan reviewed with Philippe the features of the new TRICS ver 4.0 When at D0 Hall Dan will edit the Trics_Init_Auxi file to remove the special initialization of the Front-End Busy MTG channels #1 and #31 (all of this is now coded in the internal TRICS initialization). The Reset_L15 command that the DAQ Expert can execute needs to be modified to leave (return) the Hold Transfer special control channel of the L15 Control MTG to the state where it make a tick every BX cycle plus doing its special stuff during a L15 decision cycle. Right now the Reset_L15 was leaving this MTG channel in the old setup that did not make a tick every BX. Philippe will do this work. The DAQ Expert will continue to run a com file but the com file will now call Express_to_TCC instead of a private exe. Philippe will also look at the interrupt handling in the ReSync the pipes routine. 12-APR-1993 RESET_L15 done, converted to EXPRESS_TO_TCC style with added banner to ask the DAQEXP to send us MAIL .............................................................................. Date: 8-APR-1993 At: D0Hall Topics: Repair BLS Cables, The MRBS_LOSS signal is moved from And-Or Network Term #121 to term #124 Repaired the L1 end of BLS Cables for: -17,16 -17,26 -18,17. I went to the Neutrino experiment Lab E to look for some more old PQD power supplies. Lab E is gone. There were some of the thyratron pulsers sitting in the rain. I gave the diamond cutting tool to Delmar Miller. Mike Fortner and Fred Borcherding moved the MRBS_LOSS signal from And-Or Network Term #121 to term #124 to make a contiguous block of 4 signals in the NIM-ECL module for the new active MR veto setup. .............................................................................. Date: 7-APR-1993 At: D0Hall Topics: Install the cables for L15 Veto between the L15 Framework Patch Panel and the FSTD's for Spec Trig's 9:15, Remove the 10H101's from the FSTD's for Spec Trig's 0:7, Finally install the COMINT CBus 0 FA PROM that reads the 3rd hardware Spec Trigs Fired IMLRO section, Version 4.0 of TRICS, Initial discussion about 700 Hz L1 readout Installed the cables for Spec Trig's 8:15 that run between the L15 Patch Panel and the FSTD cards. Tested running L15 on Spec Trig's 9 and 10, all was OK. Removed the 10H101's from the FSTD card for Spec Trig's 0:3 (FSTD SN# 15) and from the FSTD card for Spec Trig's 4:7 (FSTD SN# 10). Finally installed the "updated" version of the COMINT PROM for CBus 0 FA's. This is still called Rev E PROM. This is the March 26th cut. The only difference in this new part is that at the very end where there is the error check read of the Spec Trig's Fired IMLRO; now it reads the 3rd hardware section of this IMLRO (it used to have the FA's for the 1st section of this IMLRO in this error check read at the very end). Now all COMINT PROM's are up to date Ver E parts; both the ASF files and all of the actual hardware parts are the same and are up to date. Booted D0HTCC to load Philippe's TRICS Ver 4.0 Worked with Ken Johns. They have a muon L15 problem in their newest stuff. They thought that the L15 Framework always waited for ALL of the DONES; even the DONES from L15 Terms that are associated with Spec Trig's that did not fire for the given event. Whenever there is the requirement for any muon L15 trigger activity, then they cycle all of there L15 sections (even those sectons of their L15 muon trig that produce only L15 Input Terms that are associated with L1 Spec Trig's that did NOT fire). They were counting on us to wait for the DONES from sections of their stuff in which we are not interested in the ANSWER for this L15 Decision Cycle. They needed us to do this in order to keep all of their sections of their stuff looking at data from the proper beam crossing (when events are buffered). Talked with Dean about the 700 Hz readout upgrade. He says that he thinks that the Muon Mode of the VBD does what we want (i.e. it is just like the Calo Mode except that the VBD does not stick into the data stream the Word Count Words). But he is not certain. He suggests mailing a message to ZRL. Is it better to move the garbage collection Vertical reads completely out of the L1 crate-VBD and into a crate-VBD of its own? .............................................................................. Date: 3-APR-1993 At: D0Hall Topics: Find the problem in the VTC program that caused it to appear that it required > 1.16 msec to find a VBD Buffer. TrgMon has been showing that it takes greater than 1.16 msec to find a free VBD buffer. I knew that this was not right but were is the problem? VTC was starting the VBD running its DMA list and then executing the instruction to the Ironics I/O module to clear the state SearchVBD. But the VBD has the VME bus tied up so the instruction to the Ironics had to wait and the state scaler kept on counting. The routine Find_Start_VBD_1.Src was corrected and the new version of the VTC program was installed in TrgCur: .............................................................................. Date: 2-APR-1993 At: D0Hall Topics: Work on L15, Test of Pedal-to-the- Metal with new L2 Super CPU, Stuck in L15, Replace the TLM card that drives the 4 L15 Spec Trig DIGIMEM's, Program COMINT PROM CBus 0 FA, Fix the 3rd floor Power Pan Cabinet. Replace the L15 TLM Card. I replaced the TLM card that receives signals from the L15 Receiver-Mux MTG and drives the L15 Term Spec Trig DIGIMEM's. I pulled out TLM SN #7 which is an un-coppered H style TLM. I installed TLM SN #12 which has copper and 10nonH101's. The only problem is that all of the ECOed TLM's are setup to be "Latched" style TLM's and that the front CBus cable in the L15 cardfile does have a signal on TSS #G. (TSS #G is not a TLM Latch signal but is wired on the CTMBD to drive something interesting on the CTMBD's #G Lemo). To make this TLM always "Transparent" I did two things. U63 Pin 14 is the source of the clock to the TLM's 10H133 input latches. U63 is socketed. I bent up U63 Pin 14 and tied a 1N914 diode between socket U63 pin 14 and GND. The cathode of the 1N914 goes to socket U63 pin 14 and the anode goes to Gnd. This holds the clock drive to the 10H133 input latches at a High ECL level which makes the 10H133's transparent. To return this TLM to Latched operation just unplug the cathode of the 1N914 from pin 14 of socket U63 and plug all of I.C. U63 pins into its socket. The second step that I took was not to plug in the front CBus connector to the TLM. This infact was probably enough to keep this TLM Transparent. RESET L15: During a global Physics run with nothing being changed I saw all (or at least most) of central go FE-Busy. TRICS was not able to force a Data Block. We were Running-Stale. TRICS was resetting the COMINT Card. I did not look at the lights which show the state of the L15 Control MTG. The DAQEXP did a RESET L15 and it fixed the problem. When TRICS does a Reset_COMINT should it also do a Reset_L15 ?? Work on the L15: OK at a minumum the trouble that muon was having on the 24-MAR-1993 was that only Spec Trig's 0:7 have their And_Or cards connected to the L15 Framework. I still do not know why this would make the Framework do a TimeOut which is what we were seeing on the 24th. To play trying to watch the input to the L15 Term Spec Trig DIGIMEM's, I turned on the Latch- Shift Clk to the L15 IMLRO Answer and Done sections. (Load data=12 at CBus=0, MBA=57, CA=4, FA=19 and 20 normal data is 4). As yesterday the L15 Terms #9 and #12 show Done=T and Answer=T. Playing with the L15 Receiver-Mux MTG (move these 2 channels from the L15 mode to the force LOW mode and then back to the L15 mode) clears up these two L15 Terms. Pulling the 32 pair cable from the from of the TLM that drives the L15 Term Spec Trig DIGIMEM's causes the display of the L15 Term Answers and Dones to show all T's (as it should). Cook PROM's for the COMINT: Tonight I finally cooked the NEW version of the COMFAD0E PROM for the COMINT. This is the new version of the CBus 0 FA Rev E part that reads the 3rd section of the Spec Trig's Fired IMLRO in the error check read at the very end of the PROM. The original version of Rev E read the 1st section of this IMLRO. The Address Specification Files at MSU and D0 are all current and have this new version. The floppy disk file is called COMFAD0E.M26 for March 26th instead of just .DAT Because this was the first time that I transfered a VAX binary file via PathWorks to an IBM/PC and because the length of this PathWorks created binary file is different than the KERMIT created binary file I did lots of checks when cooking these parts. 1. Pull the old Rev E CBus 0 FA PROM from the spare COMINT and load the COMFAD0E.DAT file into the UniSite. Verify this PROM OK Sumcheck is 000CD453 2. Load the COMFAD0E.M26 file and verify this old Rev E PROM. See the following errors: UniSite PROM Address Data Data --------- ------ ------ $1529 88 80 $152A 89 81 $152B 8A 82 $152C 8B 83 3. This is exactly the error you would expect to see; thus the COMFAD0E.M26 file is good. 4. Cook 2 new CBus 0 FA new Rev E PROMs from this file. Their SumCheck is 000CD473 which is exactly what you expect, i.e. difference in FA address from the 1st section of the IMLRO to the 3rd section is 8 and there are 4 locations in the new Rev E FA PROM that should be bigger by 8. 5. As of now the only trace of the old Rev E CBus 0 FA PROM is the part that is in the running COMINT. Power Pan Storage Cabinet: I finished strengthening the Power Pan Storage Cabinet up on the 3rd floor. The Fermi mechanical people had put unistrut under the shelves and tonight I bolted the shelves to the walls. The repaired T1 Power Pan from last week is now in there, i.e. once again we have 2 spare T1 and 2 spare T2-T3 Power Pans at Fermi. I verified that the key worked in the lock and put the lock on the cabinet. This is the same key number lock as is on the Spare Card Storage Cabinet on the first floor by our desks. These are the locks that Steve purchased. One key for these locks is on the tag under our keyboard along with the Tool Cabinet key and the second key is in the Tool Cabinet. The spare RPSS controller box is also in the 3rd floor cabinet. .............................................................................. Date: 1-APR-1993 At: D0Hall Topics: Find-DAC run, start to look at the problem with some Level 15 Terms or Spec Triggers, Test of VTC program with no 1's and 0's, Directory Space. Made a run with Find-DAC. 9 towers incremented by -2, 6 towers incremented by +2, 1 tower incremented by +3. All other towers incremented by 0 or +-1. Loaded the new values, waiting for an Initialize. Look at the trouble with Level 15. For a description of this possible problem see the log entry for 24-MAR-1993. Look at TrgMon with nothing going on. Term Done Answer ------ ------ -------- 0 T F 9 T T 12 T T 1:8,10,11,13:19 F x Test of VTC: Because of the long amount of time that VTC spends in the state VTC Waiting for a Free VBD Buffer I made a special test version of the standard VTC program that does not put the 1's and 0's on the VTC console. This made no difference. TrgMon shows that VTC spends 1.16 ms min (when running 0.57 Hz Test Trigger) and 1.24 to 1.30 ms typical (when running with 100 Hz beam) in this state. I do not know why it should be in this state so long, this test was to verify that it was not waiting the 1 msec for the 0 or 1 character to be sent. When running only the Monitor Data Only Trig #31 then there is zero time in this state (because the Find_Start_VBD routine is never called) and when L2 starts to hang then this number gets big so I think that the scaler is OK. Disk Space: At D0 only I did a $ PL [D0_text...]*.* This freed up about 450 blocks. Philippe deleted some stuff that freed up a lot of space. We should all look at TrgIntr:Data_Block_Index_of_Text_Files.Txt to see which of the text files that try to describe the L1 Data Block can now be deleted. I expect that we only need Note 967 and the Address_Specification_Files for the COMINT PROM's. .............................................................................. Date: 31-MAR-1993 At: D0Hall Topics: TCC program, Edit files, Note sent to order the new TCC's, Visit from Dario Crosetto. Install in TrgCur: a new version of the VTC program that swaps the DBSC scallers that are used by the StateWaitSvRdy and the StateWaitStJet states. Update the [D0_Text.VME]Two_VME_Buffers.Txt description of the VTC States. Finally added the COMINT ECO to fix the once every 20 minute problem to the file [.COMINT]COMINT_ECO_Rev_B.Txt. Added the "before 8" and "After 8" lists to the TrgBook:Current_D0_Hall_Work_List.txt file. Sent the note to Hugh Montgomery asking him to transfer the money for the new TCC's. Visit from Dario Crosetto. .............................................................................. Date: 27-MAR-1993 At: D0Hall Topics: Replace a CAT2 card. Sometime last night after the store ended we must have lost the CAT2 card that serves the negative Py eta 9:16 It is the next to the top slot in the Tier II in M109. It is CBus 0 MBA 209 CA 56. At the Initialize at 4:30 this morning all of its FA's failed. All FA's 16:25 read back with either the value 54 or 62. The Final Sum Output of this CAT2 was actually wrong; its LED's were wrong. I tried to reload it from TRICS but it would not reload. It is SN 100. I pulled it out. I put in CAT2 SN 129 and Initialized the L1. All looks OK. Is this the card that sometime shows errors at the first Initialize after a Power Up??? I need to check the logs. We have only one more CAT2 here that has the ECO for Tier 2. Need to bring anothe spare. .............................................................................. Date: 26-MAR-1993 At: D0Hall Topics: Replace a Power Pan, Logic Analyzer traces of Level 15, Small change in the Rev E COMINT PROM's, Find the cause of the no-stretch on the COMINT FE_Busy, New VTC code. The the begining of store (about 5:36) the lower T1 Power Pan in M107 dies (it lost it -4.5 Volt brick). The dead Power Pan is PDM-22. It is replaces with PDM-20. Dean was captain at the time and the Cal Trig had been all right until they had just finished scraping the store. Logic Analyzer work: In full beam running I made some logic analyzer traces of L15 accept and L15 rejects. These are in the files Norm_Bem.L15 L16 L17 i.e. Normal Beam Level 15. These are on disk Trig #4. These have an interesting set of signal including the stretch. Rev E COMINT PROM's I'm changing the final read in the Rev E COMINT PROM's where the hardware list of Spec Trig's Fired is read for a second time for error checking in the VTC from reading the IMLRO's 1st copy of the this data to reading the IMLRO's 3rd copy of this data. This will change only the CBus 0 FA PROM. Because the only copies of this PROM are at Fermi I'm going to stay at Rev E. I have gotten as far as editing the master Address Specification File for CBus 0 and running the COMADRS program on it and copying the file to floppy. I have NOT cooked or installed new parts yet. The file on floppy is called COMFAD0E.M26 (for March 26). All of the master Address Specification files have been copied to both MSU and DO. OK the problem with COMINT FE-Busy Stretch: Geographic Section #1 uses FE-Busy MTG Ch #2 not Ch#31. I have checked the files in the [.Timing_and_Control] directory and they are correct and Steve's master L1 Framework layout drawing is correct. On October 1st 1992 when this was first installed I'm must have just been a sleep. I finally found it when I tried some of the other "Modes" in the PAL; like force high. This caused one of Dean's Geo Sections to go FE-Busy. For now I have stuck the FEBzGS01 PAL into Ch#2 and hand wired its ROM_IN pin to the proper pin on the PROM. As currently setup the PROM makes its only tick on Ch #7 i.e. it was setup to drive Ch #31. I will need to redo the Timing Specification File [PROG_DEV.MTG.TIMING_SPECIFICATION_FILES] FE_BUSY_MTG_PROM_4_SN_4A.TSF I have not started this yet. The FEBUSY4A.DAT file on the floppy is also junk. I had to edit TrgCur: Trics_Init_Auxi.Dat so that it set the special value of 0 in the FE-Busy MTG Ch #2 instead of Ch #31. I'm also loading the standard value of 10 decinal into Ch #31 because it did not look like TRICS was setting it up (it used to be written by the Init_Auxi so main TRICS probably did not bother it write a 10 into it to start with). The old version of Trics_Init_Auxi has been saved in [.Obsolete] and the new file is on D0HTCC::DAU0:[Trigger] and at MSUHEP::TrgCur:[DZero]. Philipe Because the special PAL in the FE-MTG has moved , does the knowledge that TRICS has about the number of read/write bits in a register need to change? This is MBA 135 CA 41 FA 1 was 5 bits read/write and now it is 2 bits. FA 30 was 2 bits and now is 5 bits. New Version of VTC code is now standard running: A version of VTC code that checks the following has been make the standard running version at D0: 1. BX Num read near the begining of the PROM's matches the BX Num read at the very end of the PROM's. This is a compare on the low order 2 bytes. 2. The Current BX Num is equal to 1 plus the Previous BX Num. This is a compare on the low order 4 bytes. 3. The List of Spec Trig's Fired read near the begining of the PROM's from the 1st section of the IMLRO matches the List of Spec Trig's Fired read near the very end of the PROM's from the 3rd section of the IMLRO. This last feature (i.e. using the 3rd section of the IMLRO for the final error checking read) needs the new Rev E COMINT PROM for CBus 0 FA and this has not been installed yet so right now it is making its final error check read from the 1st section of the IMLRO. The old version is in [.Obsolete] RunMe68020.source_removed_26MAR93 .............................................................................. Date: 25-MAR-1993 At: D0Hall Topics: Make a "TSF" file for the Front-End Busy MTG, look with the Logic Analyz during real beam running, Use the Terminal area PC to move files on DEC PathWorks. Because the Front-End Busy MTG is going to been pulled out and because the timing "tick" in the PROM for the COMINT FE Busy "Stretch PAL" needs to be changed now is a good time to make an official "Timing Specification File" for this part. The current part is a hand coded job. Make the file: FE_Busy_MTG_PROM_4_SN_4A.TAS in [Prog_Dev.MTG.Timing_Specification_files] The Timing "Tick" for this new part goes up at 21 and comes down at 25 on our timgin chart (decimal). I moved it both later and lengthened it from 2 counts to 4 counts. The FEBusy4A.Dat result of this file was moved via to a floopy via DEC Pathworks. I checked that the Hex data in the UniSite matched what is in the TSF file. On the Data I/O Unisite the FEBusy4A.Dat had a "Partial Set SumCheck" of 00000A00 i.e. (6 Bnch + 4 Bnch) x 4 x $40 Also cooked a FEBzGS01.JDC it had a "Data Sum" of 74D6 and an Xmit Sum of F467. To use the IBM/PC in the terminal area to move files do the following: Boot the PC Start DECnet (Y/N) answer Y C: Logon D0HSA UserName * Paaword: pw Use ! This shows the disks e.g. M: !When finished C:\DECnet\StopNet.Bat Logic Analyzer work: In full beam running we get a logic anal trigger about once every 15 or 20 seconds. Some of these are in the files: RR_SR_FE.CT%, RR_SR_FE.FW% i.e. Regurlar Running Short Front End Busy with either Cal Trig Latch-Shift or else Framework Latch Shift. These are on disk Trig #4. .............................................................................. Date: 24-MAR-1993 At: D0Hall Topics: Trouble with L15 Framework, Looking for the cause of "No Candidates in Jet List", Final Notes about Last weeks work, L15 Framework Problem: The muon people were running more L15 Trig's tonight and there was trouble. A L15 trig built on Spec Trig 8 using L15 Term 3 always timeed out although its Done signal was looking OK. A L15 trigger built on Spec Trig #10 using L15 Term #4 did the same thing. The logic analyzer said that the Dones were comming in time (typically 3.5 to 14 usec) and TrgMon said that the Dones were true but the cycle almost always timed out. See the logic analyzer file L15_Error.TO1 Is it a L15 Term problem or a Spec Trig related problem?? It must be Term related. Some final notes about last weeks work: The lists of Spec Trigs fired that required a Jet Trigger but had an empty jet list never included the muon jet triggers, i.e. Spec Trigs #5, #7, #10, #11. Was the just because I did not look at enough examples of the error or is it really showing us something?? From the logic analyzer for of normal 100 Hz beam running look at the average time between when the Data Block Builder finishes on Data Block and when it starts up again on an event that is queued up in the COMINT, i.e. COMINT had been FE-Busy. Sometimes are: 26.4 usec, 27.9 usec, 28.4 usec, 29.9 usec, 30.0 usec, 53.0 usec, 90.3 usec. Looking for the cause of the "No Candidates in Jet List": Make a special temporary version of the VTC program which can trigger the Philips logic analyzer. Also add to its error checking routine a test to look for: Current BX Num = Previous BX Num + 1. If this test or any of the other tests in the Error_Checking routine fails then it will trigger the logic analyzer. It has taken over the StateWaitStJetList state bit for this. Run on Cosmics and spot the problem. COMINT Front-End Busy as seen on the Trig-Acq-Sync cable from COMINT is going low for short periods of time i.e. very close to 2.0 usec. It should never be able to do this. The falling edge of Front-End Busy coming from COMINT is "Stretched" on the Front-End Busy MTG board before it goes to the Front-End Busy DIGIMEM's. We should NOT be able to trigger on the crossing following the crossing when COMINT drops FE Busy on its Trig-Acq-Sync cable. Quit using the slow VTC based trigger for the logic analyzer and trigger on Front-End Busy from COMINT low for less than 3.2 usec. This works fine. We trigger about once every 20 sec. This also lets the logic analyzer record some of the high speed signals e.g. IML Clk, FW Ltch-Shft, CT Ltch-Shft. The files are in a number of groups: VTC_Trap.V%% VTC based trigger IML Clock signal turned off VTC_Trap.F%% a "Focus In on the Problem" extracted from above file Short_FE.Vr% Short LOW signal on COMINT FE Busy Trigger with IML Clk Short_FE.FW% Short Low signal on COMINT FE Busy Trig with FrmWrk LTch-Shft Short_FE.CT% Short Low signal on COMINT FE Busy Trig with CalTrg LTch-Shft This is the logic analyzer setup: Read A/B from Pod #1 Ch #0 from M101 bottom CTMBD Lemo "N". Write A/B from Pod #1 Ch #1 from M101 bottom CTMBD Lemo "M". VTC Trig from Pod #2 Ch #4 from ECL-Box #2 Ch B1 from pair #3 on M101-M114 cable #1. Spec Trig Fired Strobe from Pod #2 Ch #5 from ECL-Box #2 Ch B2 from M102 Spec Trig Fired patch panel pair #17 on a #2 cable. Spec Trig #3 Fired from Pod #2 Ch #6 from ECL-Box #2 Ch B3 from M102 Spec Trig Fired patch panel pair #4 on a #1 cable. L15 Stretch from Pod #2 Ch #7 from ECL-Box #2 Ch B4 Hi_Z input from M103 L15 Control MTG patch panel Ch #12. Data Block Builder Running from Pod #1 Ch #0 from ECL-Box #1 Ch A1 Hi_Z input from pair #1 on M101-M114 cable #1. Start Digitize from Pod #1 Ch #1 from ECL-Box #1 Ch A2 Hi_Z input from COMINT Trig-Acq-Sync cable pair #17. Front-End Busy from Pod #1 Ch #2 from ECL-Box #1 Ch A3 Hi_Z input from COMINT Trig-Acq-Sync cable pair #18. Clear Most Recent Trigger from Pod #1 Ch #3 from ECL-Box #1 Ch A4 Hi_Z input from COMINT Trig-Acq-Sync cable pair #19. Skip 2 from Pod #1 Ch #6 from M101 bottom CTMBD Lemo "R". DBSC/Bch Clk from Pod #1 Ch #8 from M101 bottom CTMBD Lemo "G". IML Clock from Pod #1 Ch #15 from M102 Start Digit CTMBD Lemo "F". or FE Ltch-Shft from Pod #1 Ch #15 from M102 Start Digit CTMBD Lemo "B". or CT Ltch-Shft from Pod #1 Ch #15 from M104 lower Tier 1 CTMBD Lemo "B". .............................................................................. Date: 18-MAR-1993 At: D0Hall Topics: New COMINT PROM's installed, Latch-Shift Re-Sync errors, Fuses for new style Power Contactor Boxes OK, the Rev E COMINT PROM's are finally installed and the VTC code is running that will look for all three types of problems: BX# .NE. BX#, Spec_Trig_ Fired_List .NE. Spec_Trig_Fired_List, Jet List empty by a Spec Trig fired that depended on a Tot Et Jet Trig. Shot setup is under way. The spare un-tested COMINT CMT-09 also has the Rev E parts in it. I cooked them here on the Data I/O UniSite Model 48. The SumChecks are: PROM SumCheck PROM SumCheck -------- -------- -------- -------- ComFAD0E 000CD453 ComFAD1E 000AA320 ComCAD0E 000283A2 ComCAD1E 00160080 ComMBA0e 000D11D0 ComMBA1e 000A7D60 Latch-Shift Re-Sync errors: I have spotted a couple more Latch Shift Re-Sync errors with the logic analyzer. This is the once per 10 hours of 100 Hz running problem. They all appear to be the following sequence: DBB is running and it has another event queued up, It is FE Busy. DBB finishes the 1st event, FE Busy drops At the point in time where the DBB would startup again to process the 2nd event (the one that had been queued) we have a 1 BX L15 reject. DBB does startup to build the 2nd event but it did not do the reject rather it queued up a 3rd event. One can see this because our FE went and stayed Busy (it should have only pulsed Busy during the L15 decision cycle. One can also tell this because the DBB on completion of the 2nd event starts right back up on a 3rd event (the one that it should have rejected) and now for this 3rd event the pipes are wrong and it is Latch-Shifting inot the read pipe. Note that this is just a one or twice in 10 hours of 100 Hz running that one sees this problem. During this period there appear to typically be 10 or 20 sequencer errors from other crates doing Token Count Exceeded. This is not the cause of No Candidates in Jet List once every 2 minutes. The Philips Logic Analyzer files from this look are on D0 Trig Disk #4 and have names of the form: Ltch_Err.Vr% Watching VTC Error Messages: I have watched another 1/2 hour at 100 Hz of VTC console. I have seen the following error messages. Only the JT messages were seen. There were no BX or TL messages i.e. there was no indication of overwritten data i.e. the same as what the logic analyzer says. List of Spec Tot Et Jet List of Spec Tot Et Jet Trig Fired Trig's Fired Trig Fired Trig's Fired ------------ --------------- ------------ --------------- 0000 2000 #13 L 0020 0000 #21 M 1190 0000 #20, #28 HM 0000 2000 #13 L 0020 0000 #21 M 0000 2000 #13 L 1780 0000 #28 M 1180 0000 #28 M 0680 2000 #13 L 17A0 0000 #21, #28 MM 0000 2000 #13 L 0020 0000 #21 M 1180 4000 #14, #28 MM 0020 0000 #21 M 1180 0000 #28 M 1780 0000 #28 M This is a somewhat different mix of trig's than yesterdays but right now it is very high Luminosity and yesterday was during low luminosity running and the prescales are different. But once again it is a mix of triggers, and a mix of Jet Thresholds, and a mix of Tower Counts over threshold Thoughts: It must be that there is a CHTCR that has trouble or else a CTMBD that has trouble (i.e. bad signals on the backplane). It could be 10HHH101's on the CTMBD. A problem is that even if we look at all of the CTMBD Lemo's we are not really looking at the signals on the backplane. e.g. on the TSS signals there is a 10HHH101 between where the Lemo looks and the actual backplane signals. The backplane could ring and the Lemo would not see it. It may be best to ask L2 Filter people to dump a couple of events and we look for ADC counts that are big enough that a Trig Tower should be over threshold but in the Mask of Jet Patterns we do not see it. The problem with this is that if the CTMBD is really singing then the CTFE data may be lost too. I think that this problem is too rare to have much chance finding it with Random Cell test. It is also too rare to show up in the Examine distribution. I have looked at the eta phi distribution of Jet Trig's and it look flat in phi and tappers smoothly in eta. Bring FUSES for the new style Power Contactor Boxes. .............................................................................. Date: 17-MAR-1993 At: Fermi Topics: WARNING about the MSU Test Rack, ------- Log files from VTC, VTC sees Trigs with No Jet List Candidates that should have Candidates. On Monday I took the PROM's out of the COMINT card in the MSU Test Rack so that I could make some Rev E COMINT PROM's to bring to Fermi. Thus right now there are no PROM's in the MSU Test Rack's COMINT card. If it ever starts building a data block then I think that its Data Block Builder engine may run forever i.e. it will never get the "end of Data Block tick" from the MSB of the Card Address PROM for CBus 1. I need to purchase about 10 more CY7C265's. VTC can make log files !! Besides its serial port that is connected to the VTC console it also has a serial port back to the VAX. Through this port back to the VAX it could do things like: Copy/Append TT: [TrgUser.VTC_Logs]VTC_Log_File.Txt text of the log message Control Z VTC knows what time it is so it can time stamp its messages (it already has a routine to make an ASCII character time string. The Version_Limit could be set on the VTC_Log_File.Txt VTC sees the events with No Jet List Candidates: The error checking routine is in VTC to look for events where Spec Trig's fired that depended on Tot Et Jet Trig but the Tot Et Jet List is empty. It does find them at what appears to be the same rate as the L2 filter. The VTC console displays the List of Spec Trig's fired when ever it sees this error. The following is a list of about 30 minutes of errors: List of Spec Tot Et Jet List of Spec Tot Et Jet Trig Fired Trig's Fired Trig Fired Trig's Fired ------------ --------------- ------------ --------------- $1780 0000 #28 M $1180 0000 #28 M $0031 0000 #16, #20, #21 MHM $1FB0 C000 #14, #15, #20, #21, #28 $0800 C000 #14, #15 MH $0613 0000 #16, #17, #20 MMH $0003 0000 #16, #17 MM $0030 0000 #20, #21 HM $0800 8000 #15 M $0001 0000 #16 M $11A8 0000 #19, #21, #28 HMM From this it does not look like the No Candidates in Jet List problem is associated with a single or a few Spec Trig's. .............................................................................. Date: 16-MAR-1993 At: Fermi Topics: Testing the Data Block with VTC, Looking with the logic analyzer. To attack the "No Candidates in Jet List" problem, work will start on the VTC error detection. Things that can be checked are: Does the BX Number that is read near the front of the COMINT PROM's match the BX Number that is read at the end of the PROM's. Does the List of Spec Trig's Fired that is read near the begining of the COMINT PROM's match the List of Spec Trig's Fired that is read at the end of the COMINT PROM's. Make a mask of those Spec Trig's that are known to require a Total Et Jet in order to trigger. Verify that if any of these Spec Trig's have fired that the Jet List is non-zero. Philipe reminds me that it would be best to verify the BX Number that is read at the very end of the COMINT PROM's with a BX number that is read at the very front of the PROM's. Ideas: Can we use Item 0?? We could read the BX Number where currently the first DBSC for a Spec Trig is being read, and then read the Spec Trig's DBSC later and have the VTC patch it up before transfering to VBD. Note that all of our erros come from the Jet Filter at L2 and non from the Electron Filter but this is just because the Electron Filter does not do any error checking. The Logic Analyzer is on tonight looking for Both pipes the same (either both high or both low) and the Data Block Builder Busy and a positive edge on the Cal Trig Latch Shift signal. .............................................................................. Date: 15-MAR-1993 At: MSU Topics: Work on the "No Candidates in Jet List" problem, Check the COMINT PROM's, make Rev E of the COMINT PROM's Is COMINT Reading the Right Stuff:?? The problem with the "No Candidates in Jet List", could have been that one of the CHTCR cards was not being read out into the Data Block. The CHTCR could have still caused the trigger it would just not be read out if the COMINT PROM's were wrong. I hand checked all 4 Ref Sets in section "Mask of Jet Patterns" for both CBus 0 and 1. All of this looks OK. Start the Setup for VTC to do some checking: In preparation for setting up the VTC to do some checking of the Data Block, a new version of coming PROM's was made. This will be called the 15-MAR-1993 Rev E COMINT PROM's. This is a set for both CBus 0 and CBus 1. Note that Rev D was skipped for the CBus 0 parts (I thought it best to give them all a uniform Rev Number because all 6 parts were being replaced). The new source files are March_1993_CBus_0.ASF and March_1993_CBus_1.ASF in the directory [PROG_DEV.COMINT.ADDRESS_SPECIFICATION_FILES]. I have saved the old files JUNE_1992_CBUS_0.ASF and NOV_1992_CBUS_1.ASF because it is not clear that the new MARCH-15th files are official yet. All files have been copied to Fermi. These new Rev E COMINT PROM's for CBus 0 readout at the very end (after all of the stuff for 967 has been read) the 4 bytes in the List of Spec Trig's Fired and the 2 LSBytes of the Beam Crossing number. Thus the VTC could verify that these items were not overwritten during the readout of the bulk of the data block. These items are first read near the begining of the PROM's (right after the DBSC's for the Spec Trigs). It is data from the first read of these items that goes into the L1 Data Block. The second read of these quantities is only used for error detection by VTC. There are also 2 blank items that separate the last of the "real" reads from the second read of these 2 items for VTC testing. These 2 blank items just look like the normal skipping for save a place for an Intermediate Word Count. The new Rev E COMINT PROM's for CBus 1 have changed only in the addresses where the "ticks" for "Stop the Data Block Builder" and "Start the Jet List" are stored. These were just moved 8 addresses later to account for the 8 new items that are read on CBus 0. .............................................................................. Date: 14-MAR-1993 At: MSU Topics: Look at and extract interesting parts of the Logic Analyzer files, what to do next about the "No Candidates in Jet List" errors". I extracted the interesting parts of some of the logic analyzer files from last week's work into new files on disk #3. I did not look at the raw files of the "errors" that occured after the ECO but before beam running (i.e. I have not yet looked at the "Another.It%" files). The files on disk #3 are: ALL of this stuff is after the ECO. File name What is in the file on Disk #3 -------------- ----------------------------------------------------------- Real_Run.ER1 This is the one error that occured during 9 hours of beam running. This extracted part starts before the error. Latch shift is not recorded. Norm_Run.WOL With Out Latch-Shift being recorded, about 30 trigs of normal nothing special running. The next 9 files have Latch-Shift recorded. Norm_Run.FL1 L15 Reject in 2 BX while DBB is running. Norm_Run.FL2 L1 Trig while DBB is running FE goes Busy. Norm_Rn2.FL2 DBB completes one cycle and starts up another queued cycle. Norm_Run.FL3 DBB completes one cycle and starts up another queued cycle. Norm_Run.FL4 L1 Trig while DBB is running FE goes Busy. Norm_Run.FL5 Nothing extracted from Norm_Run.WL5 It has 3 L15 rejects. Norm_Run.FL6 2 L15 rejects close together while DBB is running. Norm_Run.FL7 L15 reject while DBB is running. Norm_Run.FL8 L15 reject with an L15 decision cycle of 104 usec while DBB is running. From looking at the above files it is not clear to me that there is any trouble with the gating of the Cal Trig 29525 Latch-Shift during FE Busy of L15 cycles. What to do next: Get some dump files and look at them for something funny, Setup the VTC to verify that all 4 hardware copies of the Spec Trig Fired List are the same, Setup the COMINT PROM's and the VTC to read for a 2nd time something at the very end of the DBB cycle and verify it against the first time that it was read at the front of the DBB cycle, Setup the Philipps Logic Analyzer to look for something that would indicate over written data. Get the error message from L2 to indicate the list of Specific Trigs that it though fired i.e. is this always associated with one "noisy" Spec Trig? Setup VTC to verify that when ever the Mask of Spec Trig Fired includes any Spec Trig that required a "JET" that the Jet List is not empty. Can this be because we do not "correct" the list of Spec Trigs fired the ones that fail L15?? .............................................................................. Date: 13-MAR-1993 At: Fermi Topics: First beam running with the latest COMINT ECO Logic Analyzer files, No Jet List Candidates errors Repair of more BLS cables. We have now had about 5 1/2 hours of beam running with the latest ECO for the COMINT installed. The Sequencer console showed one error at about 4 AM and we just got another one now at about 9:50. The Sequencer console showed no additional crate $B token count exceeded errors. The one from 9:50 is in the Philips logic analyzer in the file Real_Run.It1 If I find more errors with the logic analyzer during real running they will be in files Real_Run.It% There are a number of files during the past day and 1/2 since the COMINT ECO was installed where the analyzer caught something but we were not beam running at the time so I'm not certain that it is real for true bad stuff. These are Another.It1 through Another.It4 In the run 62293 from 4:11 to 8:21 there were 124 "No Candidates in Jet List" errors and 124 "No candidates in reconstructed Jet List" errors i.e. perhaps one every 2 minutes. By 14:20 no more global runs have ended so I have no more sort error summaries. By 13:24 there were no more re-sync, anal trig, Sequencer crate $B errors; thus we saw only 1 of these in about 9 hours of beam running. At this point I recorded some analyzer traces of normal operation in beam running with the COMINT ECO installed. The files are: Norm_Run_WOL (without Latch-Shift) and Norm_Run.WL1 through Norm_Run .WL8 These were all done at L1 rates of about 180 --> 75 Hz. Note: the 3 1/2 disk was in the SAFE position but it did record these files. Is the Philips getting sick (the screen still flashes). One of the Norm_Run.WL files has a 108 usec L15 Decision Cycle. Repaired BLS Cables for Trig Towers -18,17 -19,17 -20,17. All of these had been worked on by someone before. As found -19,17 and -20,17 had the signal and ground correct vesa vis the index and locking tabs. -18,17 had signal and ground incorrect wrt the tabs but the tabs had been filled off to plug this connector in. .............................................................................. Date: 12-MAR-1993 At: FERMI Topics: BLS Resistors on Noisy Channels, New Long TimeOut PAL for L15 Control MTG, Official distribution of VTC software for 2 VME Buffers, Understanding Latch-Shift signals. The "HV Spark" noise on Trigger Tower -4,21 HD was/is coming from Calorimeter element: Crate 7, ADC 9, BLS 3, Tower 2, Depth 9. Today Joan cut the BLS resistor for this element. We checked with the scope on the CTFE Monitor output for -4,21 HD before and after the cut and the noise problem DID go away when this resistor was cut. We will leave this resistor cut. The Trigger Tower that has had a resistor cut for some months is +1,24 EM. We checked it with a scope looking at the CTFE Monitor output by plugging in a BLS with all resistors installed. With this BLS we saw noise. With the normal BLS for this Trigger Tower (i.e. a BLS with the resistor for Calorimeter element: Crate 18, ADC 0, BLS 0, Tower 2, Depth 6 cut) there is no noise except for the normal base peak switching noise. We put back the BLS with the cut resistor i.e. we will leave this resistor cut. Long TimeOut PAL for L15 Control MTG: Two weeks ago the Muon People asked for a longer timeout for L15. After checking with Front-End People it was decided that about 250 usec was as long as we could wait without looking at things very carefully. So it was time to make a PAL that times out after 71 beam crossings. This new part is in the Official L15 MTG Programmable Device directory and it is called LongOut.PDS. This part is a copy of Steve's TimeOut>PDS but it gives out its Long/Short mode registers to have 2 more stages in the ripple counter. Steve did lots of work to remove the block edit errors and then made the JDC file which had 163 vectors. On vector #5 the Data I/O UniSite and the PAL ASYM do not agree about the state of the counter outputs. 1 1 1 5 9 3 7 Vector #5 1XXX 0XXX 1N0H LLLL LLHN ! PAL ASYM IBM/PC Vector #5 1XXX 0XXX 1N0H HHHH HHHN ! Data I/O UniSite The Data Sum for this part is 7EA8, the X-Sum for this part is 8BFB Two parts of this LongOut type were cooked and one was installed in the L15 Control MTG channel #29. During this process the Fermi copy of PROM files on a 3 1/2" low density disk was found to be bad (munged track number 0). This disk was OK last night while I cooked the Rev 1D parts for the spare COMINT. I need to make a new 3 1/2 disk (low density 720kb). In fact if all the files are moved to 3 1/2 disk then we can run the Data I/O from a terminal instead of from a terminal. This new LongOut PAL was installed in channels #29 and #30 of the L15 Control MTG. It looked like there are two sockets on the MTG without PAL's but I was stupid and did not write down the channel numbers. This would have been a good chance to do an inventory check of what is currently plugged in where on the L15 Control MTG but I did not do it, Note that the new LongOut part has no control registers and that it put no output connections onto the 6 bit data bus that runs to the PAL's. Thus I expect it to read back high but who known. TRICS is currently trying to write a value of 1 to the old 1 bit wide control register in channel #29. Official distribution of VTC software for 2 VME Buffers: The 2 VME buffer looks like it is going to stay in so make the official distribution of the VTC software for it and remove the old stuff from the Trigger and TrgMgr accounts. See page 136 of the Edmunds notebook. Understanding Latch-Shift signals: There are at least 3 different Latch-Shift signals: Framework MTG Ch #4 29520 Latch-Shift Cal Trig MTG Ch #5 29525 Latch-Shift Cal Trig MTG Ch #29 Cal IMLRO readout 29520 Latch-Shift Both the Framework and the IMLRO readout Latch-Shifts are under control of both the Front-End Busy and the Clear-Most-Recent Trigger signals. This is because During a L1 trig that requires a L15 decision and that forces the Front-End Busy the busy drops before the Write pipe has switched back from pointing at the Read pipe and a Latch-Shift goes by that needs to be covered and stopped by the Clear-Most-Recent. Why does not the Cal Trig MTG 29525 Latch-Shift need this?? .............................................................................. Date: 11-MAR-1993 At: Fermi Topics: Notes about the PROM for the Front- End Busy MTG for Geo Section #1 i.e. COMINT, Locks & Keys, COMINT status and ECO ??, Missing Jet List in Level 2 filter. I worked on the COMINT cards to include the latest idea about how to cuer the once per 20 min problem of loosing pipe synchronization. The ECO is to cut the DBB_NOT_BUSY signal from pin 9 of U106 and to Ground this pin. I have done this ECO to both the running and the spare COMINT's at D0 Hall. So far we have had no beam but we have run a couple of hours of cosmic muon L15 trigger 50 to 70 Hz with about 75% L15 reject. So far no loss of pipe synchronization and the logic analyzer has not triggered and no Token Loop Count overflows on crate $B. As found the two COMINT cards were set up as follows: Running Spare --------- ---------- CMT-08 CMT-09 CDBE-06 CDBE-05 CAD0C CAD0C MBA0C MBA0C FAD0C FAD0C MBA1C MBA1B FAD1C FAD1B CAD1D CAD1B The workmanship on the white wire ECO's on the spare COMINT i.e. CMT-09 is not very good. I have cooked a new current set of CBus 1 PROM's for the spare COMINT. Note these are now called Rev 1D parts but MBA1C = MBA1D and FAD1C = FAD1D only the CAD1 parts changed between Rev C and D (i.e. it picked up the Start Jet List mark). The Rev 1D parts are from November 1992. The file [Prog_Dev.COMINT.Dev_Data]Current_COMINT_PROM_Revision.Txt is up to data and correct both at D0 and MSU. I cooked the 1D parts on the Data I/O UniSite Model 48 and all went well. ComCAD1D had a sum check of 00160280 ComFAD1D had a sum check of 000AA320 ComMBA1D had a sum check of 000A7D60 See pages #28 and #30 of the Framework Logbook #2 for more information about this and instructions about using the UniSite with IBM/PC "binary" files. Empty Jet List: Jim Linnemann was on Global Monitor shift today and we had about two hours of good high luminosity global physics running. The "new" version of the L2 code is in which has some more diagnostics messages. We had 104 of both the error that says that "L1 Data Block had zero candidates in the Jet List and some were expected" and the error that said that "Philippe's rebuild Jet List code was run and found zero Jet List candidates when some were expected". There were zero errors from GZfind about the L1 crate or else the TRGR bank having any trouble. There were no error messages about no candidates in the EM "Jet List" but this is because the electron filter does not check to see if there are zero candidates. The 104 errors in 2 hours is about one per minute. We need to understand and fix this. Is there any chance that the COMINT ECO will fix it?? Another possibility is that there should be zero candidates e.g. the List of Specific Triggers Fired is in error. VTC could be setup to verify that all 4 hardware versions of the Spec Trig Fired list are the same. We (i.e. Rich or Jim) can set break points and get us some more events. LOCKS: The lock for the L1 Tool Cabinet is key number: Master P391 The lock for the L1 Spare Card Cabinet is key number: Master 0500 The lock for the L1 Spare Power Pan Cabinet is Key number: Master 0500 Front-End Busy MTG PROM and single signal setup: From the Level 1 Framework Logbook #2, 1-OCT-1992 page 20 The FEBZGS01 PROM for the Front-End Busy MTG has the following data in it. Recall that we start at PROM Address decimal 100 for the 6x6 pattern. BX Starting Signal Starts Signal Is Asserted Decimal Address at Decimal Address During Hex Addresses --------------- ------------------ -------------------- 100 108 $6c $6d 192 200 $c8 $c9 284 292 $124 $125 376 384 $180 $181 468 476 $1dc $1dd 560 568 $238 $239 The signal is asserted for 2 time ticks (PROM Addresses) during each Beam Crossing. The data is $40 i.e. the next to the MSB. Recall that MTG Ch #1 is Geo Sect #31 and MTG Ch #32 is Geo Sect #0; thus the COMINT i.e. Geo Sect #1 is PROM #4 MTG Ch#25:32 the next to the MSB. This is the only PROM in the Front-End Busy MTG. This part has a Sum Check of 300 in the UniSite Prom Programmer. The Tick Timing was picked to give a change in the Front-End Busy (as caused by an edge on the COMINT Clock the maximum time to setup in the FEBZGS01 PAL before this PAL received its PROM signal tick. From the Level 1 Framework Logbook #2, 8-OCT-1992 page 23 Recall that the COMINT FE Busy goes to a number of places e.g. internal COMINT control, FE-Busy DIGIMEM's, Gated BX Scaler control gate, And-Or Input Term The FE-Busy signal on the Trig-Acq-Sync cable from the COMINT first reaches the FE-Busy MTG. On the FE-Busy MTG this signal is stretched and then goes to the FE-Busy TLM. On the FE-Busy TLM this stretched COMINT FE-Busy signal drives both DIGIMEM's and has a special outputs for driving the And-Or Input Term and the Gated BX Scaler control gate. Thus the stretched version of COMINT FE-Busy goes only to the DIGIMEM's, the AND-Or Term, and the Gated BX Scaler; which is exactly where we need the stretched version to go. .............................................................................. Date: 6-MAR-1993 At: FERMI Topics: Philips Logic Analyzer work looking for the once every 20 min problem, March_1993_Cal_Trig_Timing_Check The relative time among the TRICS, Philips, and the Accelerator is about: TRICS Philips Accelerator --------- ----------- ----------- 10:44:00 11:41 10:44:00 10:45:28 11:42 10:45:20 10:56:18 11:53 10:56:00 10:58:08 11:55 10:57:57 The Philips is on Eastern time and about 3 minutes late. Trigger for the logic analyzer is setup to look for both read and write pipes the same (i.e. either both read and write are hi or else they are both low) while Data Block Builder is running, and the Front-End Busy is low (i.e. Latch-Shifts are flowing). I captured the files named Got_It.Vr1 through Got_It.Vr8. The first 4 files do not have the Latch-Shift signal recorded and they cover a long period of time with many triggers. The last 4 files have the Calorimeter Trigger Latch-Shift signal recorded and cover a shorter period of time. Of each type there are 2 files requiring both pipes to be high and 2 files requiring both pipes to be low (i.e. verify that it is not just a proplem with one set of pipes selected. On all files I'm almost certain that at the time that the logic analyzer triggered both the VTC console and the TRICS console put up messages (No Spec Trig's Fired and ReSync) except for the last file. When the analyzer triggered for the last file I did not see a message on either the VTC or TRICS. March_1993_Cal_Trig_Timing_Check: The data from the Timing Check work done by Kelly, Mike and myself is in the file TrgMisc: Cal_Trig_Timing_Check_mar_1993.txt This shows for real Calo signals and for Pulser signals the arrival time at the 1st floor MCH with respect to a T0 marker. This was done with a "Tap" cable on the BLS cable. We also check the CTFE Monitor outputs and the CTFE clock monitor outputs. The raw data is on pages 54 through 68 of the Dan Owen Cal-Trig Log #1 4-10-92- hard cover logbook. .............................................................................. Date: 4&5-MAR-1993 At: Fermi Topics: Storage Cabinet for the Power Pans, VTC console keyboard holder, Timing measurements of Calo and Pulser signals, Logic Analyzer looking for 1 in 20 min problem, Measure BLS cable electrical length We get a storage cabinet up in high bay. I loaded the 4 spare Power Pans into it. The shelves bent. I sent a note to Pete Simon. They will brace the shelves. Made an access on Friday morning to measure the electrical length of the BLS cables. Bob and Dave made a holder for the VTC console keyboard. Mike Holder and Kelly Page work on the measuring the arrival time of the Calo and Pulser signals. I measured some of the Pulsers signals and measured with Calo signals the relation of BLS cable signal, CTFE monitor signal, and CTFE ADC Clock. Send a note to Sando, Kotcher, Owen about signal times. Use the Philips Logic Analyzer to look for the 1 event in 20 min problem. Isolated CMR Never see this. The one example that I have must be from a redefinition of triggers error. Isolated Start Digitize I did not check this yet. Short CMR I check and we never have this. Short Start Digitize I check and we never have this. Long CMR I did not check this yet. Long Start Digitize I check and we never have this. Ideas to try: Setup the VTC to stop when it see no Spec Trig's Fired. Setup the logic analyzer to be an out of sync detector. One can get the Data Block Builder Busy signal from the copy that is set to the state scalers at the patch panel on the top of rack M101. Use bridge ECL box. Proposed error sequence: COMINT gets out of sync via some unspecified method and it over writes the buffer that is currently being read. The list of Spec Trig's Fired is over written with data from a random beam crossing which is most likely all zeros. The VTC does not transfer and event with no Spec Trig's Fired. The sequencer has to Token Loop Overflow at crate $B because there is no new data block. Try to recall and understand the various types of coax in the BLS ribbon cables: New:Old, Blue:Gray, Foam:Air, Astro:NewEnglandWire, Zo = 78 ohm or 80 ohm, Vp = 0.659, 0.707, 0.80 Ed Podschweit thinks that he recalls: Blue = Foam = 80 ohm Gray = Air = 78 ohm .............................................................................. Date: 3-MAR-1993 At: Fermi Topics: Relpace TLM's, work on FSTD H101's, See "No Spec Trig in the event" message from VTC console and ReSync message from TRICS, reroute the 115 VAC RPSS power. Replace the "bussed TLM" and the two Transparent TLM's that fan out the Spec Trig Fired Strobe and the List of Specific Triggers Fired i.e. slot #13 and the top two TLM's in M102. The top slot was TLM sn#22 and "de H'ed" TLM sn#23 was installed. The next to the top slot was TLM sn#21 and "de H'ed" TLM sn#8 was installed. Slot #13 was bussed TLM sn#18 and bussed TLM sn#17 was installed. Note that bussed TLM sn#18 was also bussed incorrectly as far as I can tell and that it needs to be repaired. Work on replacing the 10H101's in the FSTD cards. Repair cards for Spec Trig's 8:31. We did not get the two lowest FSTD's in M101 i.e. Spec Trig's 0:7 before we were asked to turn back on. Work on Timing Studies. Use a "tap cable" that when installed with the white tape mark up and the Lemo end near the BLS cable then it has the following setup: #1 = EM+, #2 = EM-, #3 = HD+, #4 = HD-. Mike and Kelly made a text file about the results so far. While watching VTC console and the TRICS console at the same time I saw both the "No Spec Trig's Fired in event" message and the TRICS ReSync pipes message at the same time. This was after todays work on the FSTD's and the TLM's. Reroute the non-switch 115 V AC for the RPSS out of the flat cable clamp and through the strain relief in the top of M113. .............................................................................. Date: 27-FEB-1993 At: Fermi Topics: Logic Analyzer on the Trig-Acq_Sync cable to COMINT Connect the Philips Logic Analyzer to the Geo Sect #1 cable. Remember that this has a different Start Digitization signal. Find one trace where we have only an isolated L15 CMR. .............................................................................. Date: 26-FEB-1993 At: Fermi Topics: Run Find_DAC, "TAP" on the Geo Sect #1 COMINT Trig-ACQ-Sync cable, No Spec Trig's Fired Events, ORed Spec Trig List VTC code, card storage rack, shallow storage cabinet. Made a full run of Find-DAC over all |eta's| 1:20. It found Pedestal values for all 2560 towers. They were all quite close to the previos values. It took almost exactly 50 minutes to run. The grinder log file is 6133 blocks. It would be fun to have Compare-DAC-Bytes print out the average value. Installed a "tap" connector on the Trig-Acq-Sync cable to Geo Sect #1 COMINT. While watching the VTC Console I see the error message "Event with no Spec Trigs Fired, not transfered." In the old version of the VTC program this would not have been flagged as an error. The old version would just have thought that this was a Monitor Data Only event and not transfered it. In both cases (old VTC and current 350 Hz VTC) the event would not have been transfered. My guess is that the IMLRO that reads out the Spec Trig's Fired is seeing ringing signals from 10H101 in the FSTD's. But there are 4 copies of the Spec Trigs Fired i.e. D0 Note 967 Items 449:452, 453:456, 457:460, 461:464. I will make a version of the VTC program that has modified the Spec_Trig_Prog_Fired_1.Src routine to "OR" together all 4 copies of the IMLRO's Spec Trigs Fired. This "ORed" list built by this routine is used to: decide if this is a Monitor Only Event, built into the header of the L1 Data Block, used to make the per Ref Set lists of Spec Trigs fired; it is not used as the hardware version that is sent upstairs to L2. OK, I make the "ORed" List of Spec Trig Fired. It goes in at about 20:00 Friday night and a new beam run starts-continues at about 20:17. One burp at about 20:32. No more by 21:02 when I quit looking; but there have been some (20 or 3) "No Candidates in Jet List in TRGR bank" messages so these empty jet list messages must not be directly connected with the burps. Later this night I do see some more Token Overflow Crate B error messages so it is still doing it. I'm confident that it is not more often than once every 20 min. I get the spare card storage rack cleaned up and put together and put our current cards in it. This rack needs a hasp and lock for the door. We were assigned a storage cabinet up on 3rd today but it is too shallow for 19" power pans; need a different one. Bob made the cover for the last section of 24" cable tray. .............................................................................. Date: 25-FEB-1993 At: Fermi Topics: Install 350 Hz readout, TrgCur: RunMe68020 files, Init_DAC_Bytes file change, Move files into {D0_text.VME] Installed the 350 Hz readout. So far it looks OK. There are a number of displays captured in a TrgMon dump file. Why is FE Busy still so high?? Recall that the TrgMon Special Diagnostics display needs lines renamed. There are now 3 RunMe68020 files in TrgCur: The proper one must be copied into TrgCur:RunMe68020.abs i.e. the standard load file for VTC. RUNME68020.ABS;2 RUNME68020.ABS_350HZ_ETA44;1 RUNME68020.ABS_FOR_ETA_32;1 RUNME68020.ABS_FOR_ETA_44;1 The file RunMe68020.abs_for_eta_44 had been the standard file before the 350 Hz hardware was installed. Now the standard file is RunMe68020.abs_350Hz_Eta_44. To switch back to the old file requires returning to the old hardware setup. Joan Guida told me the TT +3,3 EM has looked a little hot in her Examine. I looked with TrgMon ADC_Counts display and it showed mostly 10's. By hand I lowered it DAC value by 6 counts in the Trics_Init_DAC_Bytes.LSM Trics_Init_DAC_Bytes.LSM now has the update messages with the MOST RECENT at the TOP. Dan Owen worked on BLS cables in -17:-20 I have a number of additional cables to repair at the L1 end. Copy the following files from my private DEPT:[Edmunds] VME area into the Trigger account [D0_Text.VME] DESCRIPTION_OF_68K_JET_LIST_BUILDING.TXT;1 FORMAT_OF_CALO_ICD_PULSER_CETEC.TXT;1 JET_LIST_68K.TXT;1 TWO_VME_BUFERS.TXT;16 VME_ADRS_WITH_VMX_MDA01_INVERTED.TXT;1 .............................................................................. Date: 24-FEB-1993 At: Fermi Topics: New System, L15Hold Transfer Control, Lookup.ZEB file Load the new (11-FEB-1993) system into D0HTCC. This is the fix to the Begin End Run file Syncro problem with COOR and it has 5x the virtual address space. After a test with muon L15 Edit the Trics_Init_Auxi so that Ch #32 of the L15 Control MTG loads the PAL with data 14 instead of the old data 6. This should give the Hold Transfer Control line a blip once every BX plus the L15 Stretch during a L15 decision cycle. (i.e. enable "Computer Enable"). Rework the Trics_init_Auxi.dat file so that the most recent revision notice is on the TOP of the list; not on the bottom. Copy the new version of Trics_Init_Auxi.dat to MSUHEP::TrgCur[.DZero]. Rename the old (i.e. pre 5-FEB-93) Lookup_System_Manager.ZEB from TrgCur: into [Trg_Current.Obsolete]. Also delete this old version from D0HTCC::. To save disk space delete some very old versions of Lookup_System_Manager.ZEB from TrgCur:[.Obsolete]. Need to bring fuses here for the good new power contactor boxes. Ken Johns wants to change the L15 timeout to 250 usec. .............................................................................. Date: 21-FEB-1993 At: MSU Topics: List of work and parts for next trip to Fermi. On the next trip to Fermi I want to: 1. Get the keyboard for the 68k console hung on the front of rack M113. Can Delmar Miller work on this ?? 2. Get a rack setup for secure spare card storage (and perhaps spare Power Pan storage. Can Delmar Miller work on this ?? 3. Change burned out Power Pan lamps for the 155 V lamps. 4. Install the last section of 24" cable tray. Then can Delmar Miller make a top cover ?? 5. Take the 350 Hz readout to Fermi. Install it ?? 6. Take spare tested cards to Fermi and store them there. IML 7. Install 4 more repaired tested TLM's (i.e. L15, Spec Trig Fired fan-out, Bused TLM for Spec Trig Fired Strobe). 8. Work on the hung Geo Section problem when defining more L15 Trig's (i.e. let the Hold Transfer Control L15 MTG signal blip every BXing). 9. Take the Philips logic analyzer and check the Start Digitize time. 10. Re-work the un-switched 110 Volt Ac power into rack M113 (the RPSS power) to run through the groment at the top of M113 and not through the flat cable clamp in M111. 11. Get a copy of the D0 hypercard stack and the hypercard program. 12. Test run spare uVAX and order batteries for TOY clock. 13. Load new TRICS code; Begin-End Run fix. 14. Bring smoke test can back. .............................................................................. Date: 12,13 FEB 1993 At: Fermi Topics: TLM's in M101 and M101, CTMBD+CCCP in M102, Skip 1 BX PAL, M114 BBB CBus TSS Bus cables, Philips logic analyzer traces, measured timing. Replaced some TLM cards with TLM's that have all of the 10H101's removed and replaced with 10101's. The replacement TLM's also have the full modifications for "Latched" operation and their ground planes have been augmented with copper foil. In rack M102 pull the "Start Digitize" TLM SN#12 and replace it with TLM SN#5. Pull TLM SN#8, which fans out the output of the Start Digitize DIGIMEM's and replace it with TLM SN#24. TLM SN#24 is fully modified for "latched" operation but is used only in transparent mode. Also in M102 pull the MBD card that drives the Start Digitize DIGIMEM backplane; this was MBD SN#15. Install CTMBD SN#? and a CCCP card as a replacement for this MBD. This CCCP (SN#?) has its header for the front CBus cable installed so that a normal 64 conductor cable with 2 female connectors and a "feed through" adapter can be used to connect the CCCP to the existing Front CBus cable. It would have required just one section of Steve's specially selected twist and flat for this extension except that with only one section there is not enough slack cable to gain access to the Lemo connectors on the front of the CTMBD; so two sections of twist and flat were used. Remember that when replacing a MBD card with a CTMBD+CCCP that you need to move the TSS Bus and CBus cables on the backplane. In rack M101 pull the TLM that drives the Busy DIGIMEM cards. This is TLM SN#23. Replace it with the fully modified TLM SN#01. But the Busy TLM requires even more special modifications. The special modification to the Busy TLM is to obtain extra copies of the Geographic Section #1 Front-End Busy signal, i.e. extra copies of the COMINT Front-End Busy. This modification is shown in the TLM print set at D0 Hall but it is not yet mentioned in the TLM description text file. Basically it involves using the un-latched global output on the front of the TLM to send out two more copies of the Front-End Busy signal from Geographic Section #1. The Front-End Busy signal from Geo Section #1 is picked of from a via on the trace to U33 Pin 7 and is connected through a 270 ohm 1/8 watt resistor to U64 Pins 4,7. The existing un-latch global signal is disconnected from U64 Pins 4,7. See page 23 of the L1 - L1.5 Framework Logbook #2 (8-OCT-92) for a discussion about these extra copies of the COMINT Front-End Busy. On the Framework Main Timing MTG replace the Skip 1 BX PAL with a Skip 2 BX PAL. This is because with the Skip 1 BX PAL the Skip 1 BX signal in the And-Or Network become true on the beam crossing immediately after a L1.5 reject. I need to write a section about what CBus cables and TSS Bus cables are actually plugged into which BBB card in M114 in the Top Cal Trig CBus 1 section. There is some criss crossing of cables. It was originally caused by epoxy on backplane pins. All epoxy that we can find has been removed but the existing cables were left as they were when eta 17:20 coverage was installed just to make certain that nothing was broken in eta range 1:16. More logic analyzer traces were made I need to put together an over all file about measured timing at D0 Hall. The measurements will be made WRT the center of the timing "blip" that we receive on the 32 nsec Timing Verification cable from the 2nd floor Master Clock. From 22-OCT-92, page #24 of the L1 and L15 Framework Logbook #2 we have Beam Crossing to the falling edge of the CTFE ADC Clock signal is between 780-785 nsec From 30-APR-92, page #132 of the D0 Trigger Logbook #1 we see that the Start_Digitization signals go high about 930 nsec before beam crossing or about 2565 nsec after beam crossing. This measurement was made with a scope and not with the Philips logic analyzer. From logic analyzer traces taken on 12 and 13 Feb 93 we can see that the IML Clock rising edge is about 2280 nsec after beam crossing. Now cross check this: 2565 nsec - 2280 nsec is 285 nsec and 285 nsec divided by 37.66 nsec per tick gives 7.57 ticks. The timing charts show there are 9 ticks between the rising edge of IML Clock and the rising edge of Start Digitize. So things need to be checked. Has Init_Auxi moved anything since 30-APR-92 ?? I need to take to D0 Hall: The orange cord for 110 V power in M113, a holder for the VTC console keyboard, the last 12 1/4" section of 24" cable tray, spare light bulbs for the Power Pans,