MSU TESTRACK CONFIGURATION LOGBOOK see end of file for current rack layout -------------------------------------- This file was started on 11-MAR-1992, to document the changes in the MSU Testrack. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 28-JAN-1994 Philippe - loop COMINT clock signal from TSS #22 through TSS #25 and #26 as ext bits. ch #25 is the clock for the Assistant COMINT ch #26 is the clock for the Pilot COMINT ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 25-JAN-1994 Philippe To return to single comint mode. - cbus wring in the back - remove "CBUS 0" cable from pilot COMINT - move "CBUS 2" cable from assistant to pilot COMINT - remove terminator pack on "CBUS 2" and add a short section of cable to extend it to "CBUS 0" - Update BOOT_AUXI for mod_hdb on mtg - Update INIT_AUXI for Cbus addresses of MTGs - change COMINT address PROMs TRICS Code - Modify MOD011_COMMON_HARD_IO.PAS and recompile shrink field "cbus" of record "cbus_param_list" from 2 to 1-bit field (the assignment of card CBUS address to IO parameters truncates to bit) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 20-21-JAN-1994 Philippe The Framework MTG was moved from MBA 135 to MBA 68 (with CT MTG) The MBD at address 154 and 65 were moved up by one slot to free up the slot directly above the COMINT to make room for a second COMINT. The MBD at address 135 was moved up with the other MBDs to help backplane wiring swap the order of the lower 2 IMLRO Caltrig Readout. Following is the list of PALs/PROMs in Test Rack MTGs also see file [D0_TEXT.TIMING_AND_CONTROL]MSU_TEST_RACK_MTGS.TXT Framework MTG (address 0/68/35) ------------- all Channels have bit 2 PAls except for ch#3 is bit 7 Read A/B ch#5 is bit 9 Write A/B ch#12 is bit 8 Global Specific Trigger Fired all PROMs are "k" CalTrig MTG (address 0/68/53) ----------- all Channels have bit 2 PAls except for ch #9, 10, 11, 12, 13, 14 have Map Select Pal all PROMs are "k" Caltrig Readout MBD (MBA 154) ----------------------------- Receives Caltrig MTG TSS TSS Mapping 6 -> A write a/b 16 -> B Tier #3 Count CAT2 Latch, for IMLRO (EM Et and Tot Et Twr Cnt) and IMLRO (EM L2, HD L2, Tot L2, Tot Et) 4 -> C read a/b 26 -> D Tier #2 Momentum CAT2, for IMLRO (EM Et, HD Et, Px, Py) a different signal must be picked when we have a Tier #2 with Special Pickoff on the front of the card 21 -> H Tier #4 Tot Et CAT 3 Latch (Turn LEDs on) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 14-JAN-1994 Philippe: MSU - modify the Dilog SQ706 SCSI/MSCP controller to hold 2 SCSI disks. DUA0: 600 Mb DUA1: 1.2 Gb Problem I had to solve: I could not invoke the setup program while I had two 8Mb memory boards. Solution: I removed the top board and the front cable and plugged the SQ706 in Qbus slot #2 now open (I probably could have just unplugged the front cable and left the controller in its slot). I still had the video card in, and I typed the OTC console commands on the video port, but the configuration program displayed on the RS232 port. Also remember: The Emulex SCSI controller does not work with ELN (the Boot ROM grabs the system off the disk, but ELN can not mount it) Modify the SCSI unit mapping: Setup # Host Unit Node / Logical Unit# (LUN) already had 00 00 00 00 I added 01 01 01 00 ^ ^ ^ ^ my understanding: Entry MSCP unit #n SCSI SCSI sub unit Number as in DUAn: address when applies ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13-DEC-1993 Philippe: MSU second TCC VAXstation 4000 M60 KA46-A V1.3-387-V4.1 ! note the different reviosion number 08-00-2B-3E-3C-50 24MB >>> Show Device same as first 4000 >>> Show Config same as first 4000 with LCG V1.2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11-12-NOV-1993 Philippe: MSU - The 127Mb disk was initialized using EENV:INIT_DISK.DAT_4000M60. allcoates 10,000 headers - create directories [SYS0.SYSEXE] for SYSBOOT.EXE [TRIGGER] with TRICS_BOOT_AUXI.DAT TRICS_INIT_AUXI.DAT LOOKUP_SYSTEM_MANAGER.ZEB BEG_END_RUN.DAT TRICS_FORCE_BUF_UPDATE.DAT TRICS_L1_OBEY_L15.DAT TRICS_RESET_DIRECTIVES.DAT - New device addresses Pilot was %O764160 in uVAXII (i.e. %X0003E870) now %X38400870 mapped through pQBA Assist was %O764140 in uVAXII (i.e. %X0003E860) now %X38400860 mapped through pQBA add device PQBA /vector=%X3F4 /noautoload To access SCSI disk, add a DUA device with vector %X3FC, and autoload file ELN$:PKCDRIVER add volume DUA0 in system characteristic for automatic mounting at boot time - 4000 hardware notes: ------------------- The switch S3 behind the front bottom right panel door of the 4000M60 enclosure needs to be in the UP position to use the serial line for operator console port. Otherwise the video card will be used. This only affects the Boot ROM output, whether the video screen or the console port is used by the system depends on EBUILD and the DECWindow server menu characteristics, the existence of a device TTA, "terminals" TTA0 and TTA1 for the mouse and keyboard, and the description in the console menu. The console should then be attached to the "printer/communication port" which has an icon showing in THIS ORDER, a printer, a slash, and two horizontal arrows pointing in opposite directions. This is an RS 232 modular 6 wire MMJ connector port. Do not mistake this port for the "Printer/Communication port" which is an RS423 25 pin connector port. The Halt CPU button is also behind the front door. Note that halts the CPU on the serial port, but does not work thru the video screen. The Ethernet address of this box is 08-00-2B-34-EA-E5 About 10 seconds after power up, the following message appears, KA46-A V1.2-343-V4.0 08-00-2B-34-EA-E5 24MB with some kind of bargraph trying to show the progress of the power-up self-tests. This takes about 60 seconds. A short harmonic sound signal denotes the end of the test. Then the tube displays a warning ?? 048 13 UNK 0014 which "acknowledges" the existence of ZRL's hardware During Power-up self tests, proper Ethernet connections or dummy termination must be present on both types of port. In particular, the BNC thinwire connector wants to see TWO 50 Ohms terminators, otherwise it reports a code 9 NI error ?? 001 9 NI 0172 A switch between the thin and thick wire ethernet selects the network connection. For Booting, use >>> B ES or >>> B ESA0 is the command to request a downline loading >>> B or >>> B DK to use the disk While the CPU is probing a source for boot information, it displays which sourrce it is trying eg. -DKA0 I did (only once) >>> SET BOOT DKA000, ESA0 (i.e. try disk boot first, network next) (was DKA300, ES) >>> SET HALT 2 (i.e. default recovery = halt + reboot) (was 3, i.e. halt and console prompt) Console level information and configuration display: >>> SHOW CONFIG KA46-A V1.2-343-V4.0 08-00-2B-34-EA-E5 24MB Dev Dev Info Number Name ------ ---- ----- 1 NVR OK Nonvolatile RAM 2 LCG OK Low-Cost graphics coprocessor HR - 4 PLN FB -V1. 3 DZ OK Serial line controller 4 CACHE OK High-speed memory 5 MEM OK Memory 24MB = SY=8MB, S0/1=8MB, S2/3=8MB, S4/5=0MB 6 FPU OK Floating point unit 7 IT OK Interval timer 8 SYS OK Misc system board hardware 9 NI OK Network interface 10 SCSI OK SCSI controller 0-ELS127S 6-INITR 11 AUD OK Sound chip 13 UNK ?? 048 0014 Unknown i.e. ZRL >>> SHOW DEVICE ESA0 08-00-2B-34-EA-E5 DKA0 A/0/0 DISK 128.03MB FX ELS127S 4.07 ..Host ID.. A/6 INITR A regular TRICS system then looks like Job 2, program ESDRIVER, priority 1 is waiting. Ethernet Controller Job 3, program DZSDRIVER, priority 2 is waiting. Serial line Job 4, program EDEBUGREM, priority 3 is running. Edebug Remote Job 5, program PKCDRIVER, priority 4 is waiting. SCSI disk Cnt Job 7, program FALSERVER, priority 16 is waiting. File Access Listener Job 8, program TRICS_V52, priority 16 is waiting. TRICS Job 9, program MAIL_SERVER, priority 16 is waiting. Mail Server Job 10, program MPOOL_SERVER, priority 16 is waiting. Monit Server Job 11, program LOG_SERVER, priority 16 is waiting. Logfile server Job 12, program RTDRIVER, priority 16 is waiting. [SET HOST MSUD03] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 12-MAR-1992 Steve/Philippe: Decide MTG channel #12 is OK in D0 Hall style PROMs. Pulse is earlier than in MSU-style PROMs but still captures the Trigger as it overlaps the And-Or Strobe by 70 ns. PAL logic is OK, too. Replace PROMs: old new channel 1-8 MTG13 (10-89) FMWRK1K (1-92) channel 9-16 MTG15 (??-89) FMWRK2K (1-92) channel 17-24 MTGROM16 FMWRK3K (1-92) channel 25-32 MTGROM17 STRTDG4K (1-92) No PALs were changed. PALs are as listed below: channel 3 MTGBIT7 channel 5 MTGBIT9 channel 12 MTGBIT8 all others MTGBIT2 Move COMINT CLOCK signal from channel 15 to channel 22 to match D0 Hall. Move Start Digitize for COMINT from channel 14 to channel 31. Connect FWMTG XTAL Monitor output to FWMTG Accel Clock input and to CTMTG Accel Clock input. Connect FWMTG Reset output (INVERTED) to CTMTG Beam Crossing input. Connect FWMTG Channel #3 output (Read A/B) to CTMTG Channel #4 EXTBIT input (Read A/B). Connect FWMTG Channel #5 output (Write A/B) to CTMTG Channel #6 EXTBIT input (Write A/B). Program FWMTG to use External Clock, Internal Reset (in AUXI_INIT). Program CTMTG to use External Clock, either Internal or External Reset (in AUXI_INIT). Program FWMTG Channel 12 for special PAL (to memorize trigger). Program FWMTG Channel 31 for ROM Gated to make S.D. for COMINT. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ prior to 11-MAR-1992: Dan installed "D0 Hall"-style PROMs in the Cal Trig MTG TRICS_INIT_AUXI was modified to support this change "Special" MSU-only PROMs were left in the FWMTG TRICS_INIT_AUXI was not appropriate for these PROMs, but instead wanted "D0 Hall"-style FWMTG PROMs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11-MAR-1992 Steve/Philippe: Remove COMINT S/N ____ and install COMINT S/N ____ to test. Explore ideas for making Framework run again. Decide to try installing D0 Hall style PROMs in the FWMTG. List changes needed in FW cabling, INIT_AUXI, etc. to support D0 Hall style FWMTG PROMs. Question about MTG channel #12 (MSU only: memorize trigger for comint), signal is different in D0 Hall PROMs. -------------------------------------------------------------------------------- TESTRACK SETUP 21-JAN-1994 ~~~~~~~~~~~~~~ TLM BACKPLANE 10 IMLRO Counts 68,12 NO VERTICAL BUS 9 IMLRO E EM, E HD 68,11 8 IMLRO Et EM, Et HD, Px, Py 68,10 7 DBSC BEAM X 135,45 6 DBSC TRIG NUM 135,43 5 MBD CalTrig Readout 154 4 MBD ANDOR 65 3 MBD MTG-DBSC 135 2 COMINT Assist 1 COMINT Pilot ANDOR BACKPLANE 10 AUX IMLRO 135,51 9 DGM F-END BUSY 16-19 135,17 8 IMLRO F-END BUSY 135,50 7 6 IMLRO SP TRG 16-31 65,50 5 AOC HIGH SPTRG 19 65, 4 (removed) 4 AOC HIGH SPTRG 18 65, 3 (removed) 3 AOC HIGH SPTRG 17 65, 2 2 AOC HIGH SPTRG 16 65, 1 1 IML HIGH SPTRG 16-31 65,45 (removed) AUXILIARY BACKPLANE 10 SBSC SPTRG 16-19 68,20 VERTICAL BUS 9 DBSC SPTRG 16-17 68,19 8 DBSC SPTRG 18-19 68,18 7 FSTD SPTRG 16-19 68,17 6 SBSC AOFIRED 0-31 68,55 5 MTG Framework TSS 68,35 4 3 MTG CalTrig TSS 68,53 2 1 MBD 68 ANDOR BACKPLANE 10 9 8 7 6 5 4 3 2 1 CALORIMETER TRIGGER 27 CAT2 TIER #1 : EM SUM 169,16 FRONT-END 26 CAT2 TIER #1 : +PX SUM 169,20 BACKPLANE 25 CAT2 TIER #1 : +PY SUM 169,24 24 CAT2 TIER #1 : HD SUM 169,28 23 CTFE PHI = 1 ; ETA = [1,4] 169,32-33 22 CTFE PHI = 2 ; ETA = [1,4] 169,34-35 21 CTFE PHI = 3 ; ETA = [1,4] 169,36-37 20 CTFE PHI = 4 ; ETA = [1,4] 169,38-39 19 CTFE PHI = 5 ; ETA = [1,4] 169,40-41 18 CTFE PHI = 6 ; ETA = [1,4] 169,42-43 17 CTFE PHI = 7 ; ETA = [1,4] 169,44-45 16 CTFE PHI = 8 ; ETA = [1,4] 169,46-47 15 CHTCR 169, 2-3 14 MBD 169 13 12 11 10 9 8 7 6 5 4 3 2 1