Rack M103 Backplane and Details --------------------------------- Rev. 16-JUNE-1992 Layout of the Framework Expansion Backplane in Rack M103 Solder Side View ------------------------------------------------------------------------------ J4 J3 J2 J1 -------------------------------------------- 20. | ======== ======== ======== ======== | TLM CA=__ L1.5 Fanout | |||||||| //////// //////// //////// | 19. | ======== ======== ======== ======== | DGM CA=__ L1.5 ST 12..15 | |||||||| //////// //////// //////// | 18. | ======== ======== ======== ======== | DGM CA=__ L1.5 ST 8..11 | |||||||| //////// //////// //////// | 17. | ======== ======== ======== ======== | DGM CA=__ L1.5 ST 4..7 | |||||||| //////// //////// //////// | 16. | ======== ======== ======== ======== | DGM CA=__ L1.5 ST 0..3 | |||||||| //////// | 15. | ==TERM== ==TERM== ==TERM== ==TERM== | IMLRO CA=__ Lv 1.5 | xxxxxxxx | 14. | ==TERM== ======== ======== ======== | MTG CA=__ L1.5 MUX/Ltch | |||||||| | 13. | ======== ======== ======== ======== | MTG CA=__ L1.5 Veto/Conf | |||||||| | 12. | ======== ======== ======== ======== | MTG CA=__ L1.5 Control | |||||||| | 11. | ======== ======== ======== ======== | spare | |||||||| | 10. | ======== ======== ======== ======== | MBD MBA=57,CBUS=0,FWTSS | | 9. | ======== ======== ======== ======== | DGM CA=__ L1.5 Control1 | | 8. | ======== ======== ======== ======== | DGM CA=__ L1.5 Control2 | | 7. | ======== ======== ======== ======== | | | 6. | ======== ======== ======== ======== | | | 5. | ======== ======== ======== ======== | IMLRO CA=9 L0-L1,MPt,Aux | | 4. | ======== ======== ======== ======== | IMLRO CA=12 Cal Trg Counts | | 3. | ======NO VCC===== ======NO VCC===== | CTMBD CA=154,CBUS=0,CTTSS | | 2. | ======== ======== ======== ======== | IMLRO CA=11 TEt,L2:EM/HD/T | | 1. | ======== ======== ======== ======== | IMLRO CA=10 EtEM,EtHD,Px,Py |__________________________________________| J4 J3 J2 J1 Rear "Solder Side" View Terminator is on: S14J4. Connections to the inputs of the IMLRO cards in M103 that are used to readout the Calorimeter Trigger Final Sums. ---------------------------------------------------------------- Recall how the IMLRO is addressed: The IMLRO can handle up to 128 bits numbered IML0 through IML127. IML0 ... IML7 are read at Function Address 0 as data bits Data1...Data8 IML120...IML127 are read at Function Address 15 as data bits Data1...Data8 The Cal Trig "Final Sum IMLRO's" are connected in the following way: Card Address 12 is the "CHTCR Counts IMLRO" EM Ref Set 0 final count is connected to IMLRO bits 0 through 15 which are readout at FA's 0 and 1 with FA 1 being the MSByte. EM Ref Set 1 final count is connected to IMLRO bits 16 through 31 which are readout at FA's 2 and 3 with FA 3 being the MSByte. EM Ref Set 2 final count is connected to IMLRO bits 32 through 47 which are readout at FA's 4 and 5 with FA 5 being the MSByte. EM Ref Set 3 final count is connected to IMLRO bits 48 through 63 which are readout at FA's 6 and 7 with FA 7 being the MSByte. TOT Ref Set 0 final count is connected to IMLRO bits 64 through 79 which are readout at FA's 8 and 9 with FA 9 being the MSByte. TOT Ref Set 1 final count is connected to IMLRO bits 80 through 95 which are readout at FA's 10 and 11 with FA 11 being the MSByte. TOT Ref Set 2 final count is connected to IMLRO bits 96 through 111 which are readout at FA's 12 and 13 with FA 13 being the MSByte. TOT Ref Set 3 final count is connected to IMLRO bits 112 through 127 which are readout at FA's 14 and 15 with FA 15 being the MSByte. Card Address 11 is the "Total Et, L2 EM, L2 HD, L2 Total Final Sums IMLRO" Lookup 2 EM final sum is connected to IMLRO bits 0 through 23 which are readout at FA's 0, 1, and 2 with FA 2 being the MSByte. No Connection to IMLRO bits 24...31 read at FA=3. Lookup 2 HD final sum is connected to IMLRO bits 32 through 55 which are readout at FA's 4, 5, and 6 with FA 6 being the MSByte. No Connection to IMLRO bits 56...63 read at FA=7. Total Et final sum is connected to IMLRO bits 64 through 87 which are readout at FA's 8, 9, and 10 with FA 10 being the MSByte. No Connection to IMLRO bits 88...95 read at FA=11. Lookup 2 Total final sum is connected to IMLRO bits 96 through 119 which are readout at FA's 12, 13, and 14 with FA 14 being the MSByte. No Connection to IMLRO bits 120...127 read at FA=15. Card Address 10 is the "EM Et, HD Et, Px, Py Final Sum IMLRO" EM Et final sum is connected to IMLRO bits 0 through 23 which are readout at FA's 0, 1, and 2 with FA 2 being the MSByte. No Connection to IMLRO bits 24...31 read at FA=3. HD Et final sum is connected to IMLRO bits 32 through 55 which are readout at FA's 4, 5, and 6 with FA 6 being the MSByte. No Connection to IMLRO bits 56...63 read at FA=7. Px final sum is connected to IMLRO bits 64 through 87 which are readout at FA's 8, 9, and 10 with FA 10 being the MSByte. No Connection to IMLRO bits 88...95 read at FA=11. Py final sum is connected to IMLRO bits 96 through 119 which are readout at FA's 12, 13, and 14 with FA 14 being the MSByte. No Connection to IMLRO bits 120...127 read at FA=15. Card Address 9 is the "L0-L1, MPt, Auxiliary IMLRO" L0 to L1 is connected to IMLRO bits 0 through 31 which are readout at FA's 0, 1, 2, and 3. The information for D0 note 967 Item 525 is connected to IMLRO bits 0 through 7 (FA=0). The L0 Vertex information connected to IMLRO bits 8 through 31 is not defined. IMLRO bits 8:15 is FA=1 is Item 526, IMLRO bits 16:23 is FA=2 is Item 527, and IMLRO bits 24:31 is FA=3 is Item 526, Missing Pt information is connected to bits 32 through 39 which is FA = 4 and is D0 Note 967 Item 497. Items 498 and 499 will be programmed to readout bits 40:47 and 48:55. These are FA's 5 and 6. FA=7 IMLRO bits 56:63 are not being read out into the data block. IMLRO bits 64:71, 72:79, 80:87, 88:95 i.e. FA's 8, 9, 10, 11 are being readout as items 529 through 532. These are used for the Level 1.5 Control MTG Begin Status. IMLRO bits 96:103, 104:111, 112:119, 120:127 i.e. FA's 12, 13 14, 15 are being read out as D0 Note 967 Items 490 through 493. Recall the Layout of some of the Cards Used in Rack M103 Framework Expansion Calorimeter Trigger Readout and Level 1.5 Trigger -------------------------------------------------------- MTG Card MBD Card BACK TSS TSS CBUS PLANE OUTPUT CBUS IN IN CBUS _____________________________ _____________________________ ||___| |___| |___| |___| | ||___| |___| |___| |___| | | | | | | | | ^ | | ^ ^ | | v v v | | v | | | -->---+ | | | | ---->----->----->---+ | | ^ | | ^ | | | | | v | | __________ | | ___ | || | | | | | | ----------------------------- ----------------------------- EXT INPUT CBUS Front Top View Front Top View IMLRO Card CTMBD Card BACK BITS BITS BITS BITS CBUS TSS LOGIC PLANE 0-31 32-63 64-95 96-127 IN IN PROBE CBUS _____________________________ _____________________________ ||___| |___| |___| |___| | ||___| |___| |___| |___| | | | | | | | | | | v ^ | | v v v v | | v v v | | | | | --->----->---+ | | ^ | | | | | | v | | ---->----->----->--- | | | | | | | ___ | | | | | | | | | ----------------------------- ----------------------------- CBUS Front Top View Front Top View