*************************************** * * * Level 1.5 Calorimeter Trigger * * * * Cable Receiver Card * * * *************************************** 29-MAR-1994 ------------------- GENERAL DESCRIPTION ------------------- The Cable Receiver Card (CRC) takes part in the transportation of the Trigger Tower EM Et and Total Et data from the CTFE cards to the COM ports of the DSP chips. It lives logically between the Energy Readout Paddle Boards (ERPBs) and the Hydra II DSP boards, and physically in a "special" backplane in the rack containing the VME crates with the Hydra II cards. Recall that 10 "channels" of the Cable Receiver function are required (one channel for each of the 10 Level 1 Calorimeter Trigger racks). Each channel of a CRC performs the following main functions: 1) It receives and latches the differential ECL signals from the ERPBs. Recall that each Level 1 Calorimeter Trigger rack is serviced by 8 ERPBs, and that the EM Et and Total Et (accompanied by a Strobe) for each Trigger Tower are transmitted serially on a 40-conductor cable. See the ERPB description for more details on the operation of the ERPB. This latching is provided to "clean up" (de-skew) the signals coming from the ERPBs. 2) It drives 2 copies each of the Trigger Tower EM Et and Total Et data to COM ports on the Hydra II DSP boards. Thus each channel of a CRC drives 4 COM ports on 2 DSP chips (1 EM Et and 1 Total Et per each of 2 DSP chips). 3) It handles the handshaking (Strobe and Reply) for each of the COM ports separately (as described in TMS320 DSP Designers Notebook Number 17). The Strobe from the ERPBs is used (with the appropriate delay for setup) to initate the handshaking with a COM port (i.e. it drives the Strobe to a COM port), while the Reply from the COM port is used to complete the handshake (by forcing the Strobe to the COM port to its inactive level). Both the delayed strobe and the appropriate reply are processed on the CRC by the "Strobe Clipper" type 16RA8 PAL (see also "CRCSTROB.PDS" file in the PROG_DEV.CRC directory). 4) It "grabs" the token from each of the 4 COM ports, forcing the COM ports into "receive-only" mode (note that the "grabber" must first determine whether the COM port has the token). The token "grabbing" is performed on the CRC by the "Token Grabber" type 16RA8 PAL (see also "CRCTOKEN.PDS" in the PROG_DEV.CRC directory). 5) It provides appropriate termination for the input and output signals. Parallel termination is required on the receive end of the differential ECL input wires from the ERPBs, while series termination is required at the source end of the TTL output wires to the COM ports. One CRC can provide 5 "channels" of CRC functionality (i.e. one CRC can service 5 Level 1 Calorimeter Trigger racks). Therefore 2 CRC's will be required to service the 10 Level 1 Calorimeter Trigger racks. ------------------------------------------ DESCRIPTION OF LED'S ------------------------------------------ There are three Power ON LED's, one for each power level. These LED's are placed such that they can be seen as on or off from either the front of the card or the rear, where the Power connector (J6) is located. There are sets of LED's which indicate when each channel is "Ready-To-Transfer" or "Transfer-In-Progress." These are taken as the NAND of each channels 4 /CRDY signals and then driven to an LED for "Tranfer-In-Progress" or inverted for "Ready-To-Transfer." Thus for a given channel, if any of the /CRDY signals are LOW (NOT ready), then that channel's "Transfer-In-Progress" LED is on and it's corresponding "Ready-To-Transfer" LED is off. Only when all 4 /CRDY signals for a channel are asserted will the "Ready-To-Transfer" LED for that channel be on, and therefore it's "Transfer-In-Progress" LED be off. There is an "All-Tokens-Grabbed" LED for each channel. This is taken as the logical OR of a channel's 4 /CREQ signals from the DSP and then inverted. Thus if any of the channel's /CREQ signals are high then the "All-Tokens-Grabbed" for that LED is off. ------------------------------------------ CONSIDERATIONS FOR ECO'S ------------------------------------------ Consideration for possible future modification (ECO's) of this card was given. The control signals for many components were brought out to vias and connected to thier appropriate power level using a cosmetic trace and appropriate labeling. This will allow easy modification of functionality of these components. Where possible, unused pins an PALs where brought to vias. Extra F100324 (TTL to Differential ECL converters) were placed near the input connectors (from ERPB) to allow the possibility of sending ECL signals from the CRC to the ERPB on the SPARE channels of the 40 conductors cables. All control signals to and from the DSP's have extra traces brought to vias located near connections to VCC and Ground which will allow these signals to be permanently tied to +5V or Ground, should the need arise. Connections for pull-up/pull-down resistors were placed to allow for this possibility. The body outline of these initially unused resistors are marked with a silk screened "X". ------------------------------------------ CONCEPTUAL SCHEMATIC OF ONE CHANNEL OF CRC ------------------------------------------ |\ EM Et Data to .-/--| )-^v-/-> DSP 'n' Port 'A' | 8 |/ 8 Data 0..7 .----------. .-----. | -----*--| | |latch| | |\ EM Et Data to EM Z | diff |-/-----|D Q|--/--=-/--| )-^v-/-> DSP 'm' Port 'B' Z | to | 8 .-|> | 8 8 |/ 8 Data 0..7 -/8--*--| single- | | `-----' diff | ended | | | convertor| | .-----. -----*--| | | |latch| |\ Total Et Data to Tot Z | |-/-----|D Q|--/--=-/--| )-^v-/-> DSP 'n' Port 'C' Z | | 8 *-|> | 8 | 8 |/ 8 -/8--*--| | | `-----' | diff | | | | |\ Total Et Data to | | | `-/--| )-^v-/-> DSP 'm' Port 'D' Stb | | | 8 |/ 8 ----/---| |-----* 1 | | | diff | | | .-----. _____ | | *-------|clip-|-^v---> DSP 'n' Port 'A' CSTRB Spare | | | | per | ____ -----/--| | | .---| |---< From DSP 'n' Port 'A' CRDY 3 | | | | `-----' diff | | | | | | | | .-----. _____ `----------' *-------|clip-|-^v---> DSP 'm' Port 'B' CSTRB | | | per | ____ | *---| |---< From DSP 'm' Port 'B' CRDY Z = parallel | | `-----' termination | | | | .-----. _____ ^v = series *-------|clip-|-^v---> DSP 'n' Port 'C' CSTRB termination | | | per | ____ | *---| |---< From DSP 'n' Port 'C' CRDY > = signal flow | | `-----' < | | | | .-----. _____ `-------|clip-|-^v---> DSP 'm' Port 'D' CSTRB | | per | ____ *---| |---< From DSP 'm' Port 'D' CRDY | `-----' | | .-----. ____ VME_RESET -------*---*---|grab-|-^v---> DSP 'n' Port 'A' CACK | | ber | ____ | | |---< From DSP 'n' Port 'A' CREQ | `-----' | | .-----. ____ *-------|grab-|-^v---> DSP 'm' Port 'B' CACK | | ber | ____ | | |---< From DSP 'm' Port 'B' CREQ | `-----' | | .-----. ____ *-------|grab-|-^v---> DSP 'n' Port 'C' CACK | | ber | ____ | | |---< From DSP 'n' Port 'C' CREQ | `-----' | | .-----. ____ `-------|grab-|-^v---> DSP 'm' Port 'D' CACK | ber | ____ | |---< From DSP 'm' Port 'D' CREQ `-----' ------------------------- CONNECTOR PIN ASSIGNMENTS ------------------------- The CRC should have 25 signal connectors: J1-J5: Connectors from ERPBs (via DCs) these are 40-pin 0.1" x 0.1" AMP-style connectors J6: Symmetric power connector J3[0-4][0-3]: Connectors to Hydras (via 6/10 Port Paddleboards) these are 24-pin 0.1" x 0.1" AMP-style connectors ------------------------------------------------------------------------ J1: 40-pin connector from ERPB for Channel #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #1 EM Et Bit 7 (MSB) NINV Input N1E7IN 2 Ch. #1 EM Et Bit 7 (MSB) INV Input I1E7IN 3 Ch. #1 EM Et Bit 6 NINV Input N1E6IN 4 Ch. #1 EM Et Bit 6 INV Input I1E6IN 5 Ch. #1 EM Et Bit 5 NINV Input N1E5IN 6 Ch. #1 EM Et Bit 5 INV Input I1E5IN 7 Ch. #1 EM Et Bit 4 NINV Input N1E4IN 8 Ch. #1 EM Et Bit 4 INV Input I1E4IN 9 Ch. #1 EM Et Bit 3 NINV Input N1E3IN 10 Ch. #1 EM Et Bit 3 INV Input I1E3IN 11 Ch. #1 EM Et Bit 2 NINV Input N1E2IN 12 Ch. #1 EM Et Bit 2 INV Input I1E2IN 13 Ch. #1 EM Et Bit 1 NINV Input N1E1IN 14 Ch. #1 EM Et Bit 1 INV Input I1E1IN 15 Ch. #1 EM Et Bit 0 (LSB) NINV Input N1E0IN 16 Ch. #1 EM Et Bit 0 (LSB) INV Input I1E0IN 17 Ch. #1 Total Et Bit 7 (MSB) NINV Input N1T7IN 18 Ch. #1 Total Et Bit 7 (MSB) INV Input I1T7IN 19 Ch. #1 Total Et Bit 6 NINV Input N1T6IN 20 Ch. #1 Total Et Bit 6 INV Input I1T6IN 21 Ch. #1 Total Et Bit 5 NINV Input N1T5IN 22 Ch. #1 Total Et Bit 5 INV Input I1T5IN 23 Ch. #1 Total Et Bit 4 NINV Input N1T4IN 24 Ch. #1 Total Et Bit 4 INV Input I1T4IN 25 Ch. #1 Total Et Bit 3 NINV Input N1T3IN 26 Ch. #1 Total Et Bit 3 INV Input I1T3IN 27 Ch. #1 Total Et Bit 2 NINV Input N1T2IN 28 Ch. #1 Total Et Bit 2 INV Input I1T2IN 29 Ch. #1 Total Et Bit 1 NINV Input N1T1IN 30 Ch. #1 Total Et Bit 1 INV Input I1T1IN 31 Ch. #1 Total Et Bit 0 (LSB) NINV Input N1T0IN 32 Ch. #1 Total Et Bit 0 (LSB) INV Input I1T0IN 33 Ch. #1 Strobe NINV Input N1STIN 34 Ch. #1 Strobe INV Input I1STIN 35 Ch. #1 Spare Signal #1 NINV I/O N1SP1 36 Ch. #1 Spare Signal #1 INV I/O I1SP1 37 Ch. #1 Spare Signal #2 NINV I/O N1SP2 38 Ch. #1 Spare Signal #2 INV I/O I1SP2 39 Ch. #1 Spare Signal #3 NINV I/O N1SP3 40 Ch. #1 Spare Signal #3 INV I/O I1SP3 ------------------------------------------------------------------------ J2: 40-pin connector from ERPB for Channel #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #2 EM Et Bit 7 (MSB) NINV Input N2E7IN 2 Ch. #2 EM Et Bit 7 (MSB) INV Input I2E7IN 3 Ch. #2 EM Et Bit 6 NINV Input N2E6IN 4 Ch. #2 EM Et Bit 6 INV Input I2E6IN 5 Ch. #2 EM Et Bit 5 NINV Input N2E5IN 6 Ch. #2 EM Et Bit 5 INV Input I2E5IN 7 Ch. #2 EM Et Bit 4 NINV Input N2E4IN 8 Ch. #2 EM Et Bit 4 INV Input I2E4IN 9 Ch. #2 EM Et Bit 3 NINV Input N2E3IN 10 Ch. #2 EM Et Bit 3 INV Input I2E3IN 11 Ch. #2 EM Et Bit 2 NINV Input N2E2IN 12 Ch. #2 EM Et Bit 2 INV Input I2E2IN 13 Ch. #2 EM Et Bit 1 NINV Input N2E1IN 14 Ch. #2 EM Et Bit 1 INV Input I2E1IN 15 Ch. #2 EM Et Bit 0 (LSB) NINV Input N2E0IN 16 Ch. #2 EM Et Bit 0 (LSB) INV Input I2E0IN 17 Ch. #2 Total Et Bit 7 (MSB) NINV Input N2T7IN 18 Ch. #2 Total Et Bit 7 (MSB) INV Input I2T7IN 19 Ch. #2 Total Et Bit 6 NINV Input N2T6IN 20 Ch. #2 Total Et Bit 6 INV Input I2T6IN 21 Ch. #2 Total Et Bit 5 NINV Input N2T5IN 22 Ch. #2 Total Et Bit 5 INV Input I2T5IN 23 Ch. #2 Total Et Bit 4 NINV Input N2T4IN 24 Ch. #2 Total Et Bit 4 INV Input I2T4IN 25 Ch. #2 Total Et Bit 3 NINV Input N2T3IN 26 Ch. #2 Total Et Bit 3 INV Input I2T3IN 27 Ch. #2 Total Et Bit 2 NINV Input N2T2IN 28 Ch. #2 Total Et Bit 2 INV Input I2T2IN 29 Ch. #2 Total Et Bit 1 NINV Input N2T1IN 30 Ch. #2 Total Et Bit 1 INV Input I2T1IN 31 Ch. #2 Total Et Bit 0 (LSB) NINV Input N2T0IN 32 Ch. #2 Total Et Bit 0 (LSB) INV Input I2T0IN 33 Ch. #2 Strobe NINV Input N2STIN 34 Ch. #2 Strobe INV Input I2STIN 35 Ch. #2 Spare Signal #1 NINV I/O N2SP1 36 Ch. #2 Spare Signal #1 INV I/O I2SP1 37 Ch. #2 Spare Signal #2 NINV I/O N2SP2 38 Ch. #2 Spare Signal #2 INV I/O I2SP2 39 Ch. #2 Spare Signal #3 NINV I/O N2SP3 40 Ch. #2 Spare Signal #3 INV I/O I2SP3 ------------------------------------------------------------------------ J3: 40-pin connector from ERPB for Channel #3 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #3 EM Et Bit 7 (MSB) NINV Input N3E7IN 2 Ch. #3 EM Et Bit 7 (MSB) INV Input I3E7IN 3 Ch. #3 EM Et Bit 6 NINV Input N3E6IN 4 Ch. #3 EM Et Bit 6 INV Input I3E6IN 5 Ch. #3 EM Et Bit 5 NINV Input N3E5IN 6 Ch. #3 EM Et Bit 5 INV Input I3E5IN 7 Ch. #3 EM Et Bit 4 NINV Input N3E4IN 8 Ch. #3 EM Et Bit 4 INV Input I3E4IN 9 Ch. #3 EM Et Bit 3 NINV Input N3E3IN 10 Ch. #3 EM Et Bit 3 INV Input I3E3IN 11 Ch. #3 EM Et Bit 2 NINV Input N3E2IN 12 Ch. #3 EM Et Bit 2 INV Input I3E2IN 13 Ch. #3 EM Et Bit 1 NINV Input N3E1IN 14 Ch. #3 EM Et Bit 1 INV Input I3E1IN 15 Ch. #3 EM Et Bit 0 (LSB) NINV Input N3E0IN 16 Ch. #3 EM Et Bit 0 (LSB) INV Input I3E0IN 17 Ch. #3 Total Et Bit 7 (MSB) NINV Input N3T7IN 18 Ch. #3 Total Et Bit 7 (MSB) INV Input I3T7IN 19 Ch. #3 Total Et Bit 6 NINV Input N3T6IN 20 Ch. #3 Total Et Bit 6 INV Input I3T6IN 21 Ch. #3 Total Et Bit 5 NINV Input N3T5IN 22 Ch. #3 Total Et Bit 5 INV Input I3T5IN 23 Ch. #3 Total Et Bit 4 NINV Input N3T4IN 24 Ch. #3 Total Et Bit 4 INV Input I3T4IN 25 Ch. #3 Total Et Bit 3 NINV Input N3T3IN 26 Ch. #3 Total Et Bit 3 INV Input I3T3IN 27 Ch. #3 Total Et Bit 2 NINV Input N3T2IN 28 Ch. #3 Total Et Bit 2 INV Input I3T2IN 29 Ch. #3 Total Et Bit 1 NINV Input N3T1IN 30 Ch. #3 Total Et Bit 1 INV Input I3T1IN 31 Ch. #3 Total Et Bit 0 (LSB) NINV Input N3T0IN 32 Ch. #3 Total Et Bit 0 (LSB) INV Input I3T0IN 33 Ch. #3 Strobe NINV Input N3STIN 34 Ch. #3 Strobe INV Input I3STIN 35 Ch. #3 Spare Signal #1 NINV I/O N3SP1 36 Ch. #3 Spare Signal #1 INV I/O I3SP1 37 Ch. #3 Spare Signal #2 NINV I/O N3SP2 38 Ch. #3 Spare Signal #2 INV I/O I3SP2 39 Ch. #3 Spare Signal #3 NINV I/O N3SP3 40 Ch. #3 Spare Signal #3 INV I/O I3SP3 ------------------------------------------------------------------------ J4: 40-pin connector from ERPB for Channel #4 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #4 EM Et Bit 7 (MSB) NINV Input N4E7IN 2 Ch. #4 EM Et Bit 7 (MSB) INV Input I4E7IN 3 Ch. #4 EM Et Bit 6 NINV Input N4E6IN 4 Ch. #4 EM Et Bit 6 INV Input I4E6IN 5 Ch. #4 EM Et Bit 5 NINV Input N4E5IN 6 Ch. #4 EM Et Bit 5 INV Input I4E5IN 7 Ch. #4 EM Et Bit 4 NINV Input N4E4IN 8 Ch. #4 EM Et Bit 4 INV Input I4E4IN 9 Ch. #4 EM Et Bit 3 NINV Input N4E3IN 10 Ch. #4 EM Et Bit 3 INV Input I4E3IN 11 Ch. #4 EM Et Bit 2 NINV Input N4E2IN 12 Ch. #4 EM Et Bit 2 INV Input I4E2IN 13 Ch. #4 EM Et Bit 1 NINV Input N4E1IN 14 Ch. #4 EM Et Bit 1 INV Input I4E1IN 15 Ch. #4 EM Et Bit 0 (LSB) NINV Input N4E0IN 16 Ch. #4 EM Et Bit 0 (LSB) INV Input I4E0IN 17 Ch. #4 Total Et Bit 7 (MSB) NINV Input N4T7IN 18 Ch. #4 Total Et Bit 7 (MSB) INV Input I4T7IN 19 Ch. #4 Total Et Bit 6 NINV Input N4T6IN 20 Ch. #4 Total Et Bit 6 INV Input I4T6IN 21 Ch. #4 Total Et Bit 5 NINV Input N4T5IN 22 Ch. #4 Total Et Bit 5 INV Input I4T5IN 23 Ch. #4 Total Et Bit 4 NINV Input N4T4IN 24 Ch. #4 Total Et Bit 4 INV Input I4T4IN 25 Ch. #4 Total Et Bit 3 NINV Input N4T3IN 26 Ch. #4 Total Et Bit 3 INV Input I4T3IN 27 Ch. #4 Total Et Bit 2 NINV Input N4T2IN 28 Ch. #4 Total Et Bit 2 INV Input I4T2IN 29 Ch. #4 Total Et Bit 1 NINV Input N4T1IN 30 Ch. #4 Total Et Bit 1 INV Input I4T1IN 31 Ch. #4 Total Et Bit 0 (LSB) NINV Input N4T0IN 32 Ch. #4 Total Et Bit 0 (LSB) INV Input I4T0IN 33 Ch. #4 Strobe NINV Input N4STIN 34 Ch. #4 Strobe INV Input I4STIN 35 Ch. #4 Spare Signal #1 NINV I/O N4SP1 36 Ch. #4 Spare Signal #1 INV I/O I4SP1 37 Ch. #4 Spare Signal #2 NINV I/O N4SP2 38 Ch. #4 Spare Signal #2 INV I/O I4SP2 39 Ch. #4 Spare Signal #3 NINV I/O N4SP3 40 Ch. #4 Spare Signal #3 INV I/O I4SP3 ------------------------------------------------------------------------ J5: 40-pin connector from ERPB for Channel #5 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #5 EM Et Bit 7 (MSB) NINV Input N5E7IN 2 Ch. #5 EM Et Bit 7 (MSB) INV Input I5E7IN 3 Ch. #5 EM Et Bit 6 NINV Input N5E6IN 4 Ch. #5 EM Et Bit 6 INV Input I5E6IN 5 Ch. #5 EM Et Bit 5 NINV Input N5E5IN 6 Ch. #5 EM Et Bit 5 INV Input I5E5IN 7 Ch. #5 EM Et Bit 4 NINV Input N5E4IN 8 Ch. #5 EM Et Bit 4 INV Input I5E4IN 9 Ch. #5 EM Et Bit 3 NINV Input N5E3IN 10 Ch. #5 EM Et Bit 3 INV Input I5E3IN 11 Ch. #5 EM Et Bit 2 NINV Input N5E2IN 12 Ch. #5 EM Et Bit 2 INV Input I5E2IN 13 Ch. #5 EM Et Bit 1 NINV Input N5E1IN 14 Ch. #5 EM Et Bit 1 INV Input I5E1IN 15 Ch. #5 EM Et Bit 0 (LSB) NINV Input N5E0IN 16 Ch. #5 EM Et Bit 0 (LSB) INV Input I5E0IN 17 Ch. #5 Total Et Bit 7 (MSB) NINV Input N5T7IN 18 Ch. #5 Total Et Bit 7 (MSB) INV Input I5T7IN 19 Ch. #5 Total Et Bit 6 NINV Input N5T6IN 20 Ch. #5 Total Et Bit 6 INV Input I5T6IN 21 Ch. #5 Total Et Bit 5 NINV Input N5T5IN 22 Ch. #5 Total Et Bit 5 INV Input I5T5IN 23 Ch. #5 Total Et Bit 4 NINV Input N5T4IN 24 Ch. #5 Total Et Bit 4 INV Input I5T4IN 25 Ch. #5 Total Et Bit 3 NINV Input N5T3IN 26 Ch. #5 Total Et Bit 3 INV Input I5T3IN 27 Ch. #5 Total Et Bit 2 NINV Input N5T2IN 28 Ch. #5 Total Et Bit 2 INV Input I5T2IN 29 Ch. #5 Total Et Bit 1 NINV Input N5T1IN 30 Ch. #5 Total Et Bit 1 INV Input I5T1IN 31 Ch. #5 Total Et Bit 0 (LSB) NINV Input N5T0IN 32 Ch. #5 Total Et Bit 0 (LSB) INV Input I5T0IN 33 Ch. #5 Strobe NINV Input N5STIN 34 Ch. #5 Strobe INV Input I5STIN 35 Ch. #5 Spare Signal #1 NINV I/O N5SP1 36 Ch. #5 Spare Signal #1 INV I/O I5SP1 37 Ch. #5 Spare Signal #2 NINV I/O N5SP2 38 Ch. #5 Spare Signal #2 INV I/O I5SP2 39 Ch. #5 Spare Signal #3 NINV I/O N5SP3 40 Ch. #5 Spare Signal #3 INV I/O I5SP3 ------------------------------------------------------------------------ J6: 50-pin connector for Power ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 VCC, +5 Volts VCC 2 VCC, +5 Volts VCC 3 VCC, +5 Volts VCC 4 VCC, +5 Volts VCC 5 VCC, +5 Volts VCC 6 VCC, +5 Volts VCC 7 Unused 8 Unused 9 VTT, -2 Volts VTT 10 VTT, -2 Volts VTT 11 VTT, -2 Volts VTT 12 VTT, -2 Volts VTT 13 Unused 14 Unused 15 VEE, -5 Volts VEE 16 VEE, -5 Volts VEE 17 VEE, -5 Volts VEE 18 VEE, -5 Volts VEE 19 Unused 20 Unused 21 Ground GND 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Unused 32 Unused 33 VEE, -5 Volts VEE 34 VEE, -5 Volts VEE 35 VEE, -5 Volts VEE 36 VEE, -5 Volts VEE 37 Unused 38 Unused 39 VTT, -2 Volts VTT 40 VTT, -2 Volts VTT 41 VTT, -2 Volts VTT 42 VTT, -2 Volts VTT 43 Unused 44 Unused 45 VCC, +5 Volts VCC 46 VCC, +5 Volts VCC 47 VCC, +5 Volts VCC 48 VCC, +5 Volts VCC 49 VCC, +5 Volts VCC 50 VCC, +5 Volts VCC ------------------------------------------------------------------------ J164: Coaxial LEMO Connector for CH 1 EM /CRDY 1 (TO DSP) MONITORING ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch 1 EM Et CRDY* Output 11ERDY ------------------------------------------------------------------------ J165: Coaxial LEMO Connector for CH 1 EM /CSTR 1 (TO DSP) MONITORING ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch 1 EM Et CSTR* Output 11ESTB ------------------------------------------------------------------------ J164: Coaxial LEMO Connector for CH 1 STROBE TTL (FROM ERPB) MONITORING ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch 1 TTL STROBE FROM ERPB Output T1STRO ------------------------------------------------------------------------ J300: 24-pin connector to Paddleboard for Channel #1 EM Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #1-1 EM Et CREQ* [DxyC10] In/Out 11EREQ 2 Ground GND 3 Ch. #1-1 EM Et CSTRB* [DxyC8] Output 11ESTB 4 Ground GND 5 Ch. #1-1 EM Et CACK* [DxyC11] In/Out 11EACK 6 Ground GND 7 Ch. #1-1 EM Et CRDY* [DxyC9] Input 11ERDY 8 Ground GND 9 Ch. #1-1 EM Et Bit 0 [DxyC0] Output 11E0 10 Ground GND 11 Ch. #1-1 EM Et Bit 1 [DxyC1] Output 11E1 12 Ground GND 13 Ch. #1-1 EM Et Bit 2 [DxyC2] Output 11E2 14 Ground GND 15 Ch. #1-1 EM Et Bit 3 [DxyC3] Output 11E3 16 Ground GND 17 Ch. #1-1 EM Et Bit 4 [DxyC4] Output 11E4 18 Ground GND 19 Ch. #1-1 EM Et Bit 5 [DxyC5] Output 11E5 20 Ground GND 21 Ch. #1-1 EM Et Bit 6 [DxyC6] Output 11E6 22 Ground GND 23 Ch. #1-1 EM Et Bit 7 [DxyC7] Output 11E7 24 Ground GND ------------------------------------------------------------------------ J301: 24-pin connector to Paddleboard for Channel #1 EM Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #1-2 EM Et CREQ* [DxyC10] In/Out 12EREQ 2 Ground GND 3 Ch. #1-2 EM Et CSTRB* [DxyC8] Output 12ESTB 4 Ground GND 5 Ch. #1-2 EM Et CACK* [DxyC11] In/Out 12EACK 6 Ground GND 7 Ch. #1-2 EM Et CRDY* [DxyC9] Input 12ERDY 8 Ground GND 9 Ch. #1-2 EM Et Bit 0 [DxyC0] Output 12E0 10 Ground GND 11 Ch. #1-2 EM Et Bit 1 [DxyC1] Output 12E1 12 Ground GND 13 Ch. #1-2 EM Et Bit 2 [DxyC2] Output 12E2 14 Ground GND 15 Ch. #1-2 EM Et Bit 3 [DxyC3] Output 12E3 16 Ground GND 17 Ch. #1-2 EM Et Bit 4 [DxyC4] Output 12E4 18 Ground GND 19 Ch. #1-2 EM Et Bit 5 [DxyC5] Output 12E5 20 Ground GND 21 Ch. #1-2 EM Et Bit 6 [DxyC6] Output 12E6 22 Ground GND 23 Ch. #1-2 EM Et Bit 7 [DxyC7] Output 12E7 24 Ground GND ------------------------------------------------------------------------ J302: 24-pin connector to Paddleboard for Channel #1 Total Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #1-1 Total Et CREQ* [DxyC10] In/Out 11TREQ 2 Ground GND 3 Ch. #1-1 Total Et CSTRB* [DxyC8] Output 11TSTB 4 Ground GND 5 Ch. #1-1 Total Et CACK* [DxyC11] In/Out 11TACK 6 Ground GND 7 Ch. #1-1 Total Et CRDY* [DxyC9] Input 11TRDY 8 Ground GND 9 Ch. #1-1 Total Et Bit 0 [DxyC0] Output 11T0 10 Ground GND 11 Ch. #1-1 Total Et Bit 1 [DxyC1] Output 11T1 12 Ground GND 13 Ch. #1-1 Total Et Bit 2 [DxyC2] Output 11T2 14 Ground GND 15 Ch. #1-1 Total Et Bit 3 [DxyC3] Output 11T3 16 Ground GND 17 Ch. #1-1 Total Et Bit 4 [DxyC4] Output 11T4 18 Ground GND 19 Ch. #1-1 Total Et Bit 5 [DxyC5] Output 11T5 20 Ground GND 21 Ch. #1-1 Total Et Bit 6 [DxyC6] Output 11T6 22 Ground GND 23 Ch. #1-1 Total Et Bit 7 [DxyC7] Output 11T7 24 Ground GND ------------------------------------------------------------------------ J303: 24-pin connector to Paddleboard for Channel #1 Total Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #1-2 Total Et CREQ* [DxyC10] In/Out 12TREQ 2 Ground GND 3 Ch. #1-2 Total Et CSTRB* [DxyC8] Output 12TSTB 4 Ground GND 5 Ch. #1-2 Total Et CACK* [DxyC11] In/Out 12TACK 6 Ground GND 7 Ch. #1-2 Total Et CRDY* [DxyC9] Input 12TRDY 8 Ground GND 9 Ch. #1-2 Total Et Bit 0 [DxyC0] Output 12T0 10 Ground GND 11 Ch. #1-2 Total Et Bit 1 [DxyC1] Output 12T1 12 Ground GND 13 Ch. #1-2 Total Et Bit 2 [DxyC2] Output 12T2 14 Ground GND 15 Ch. #1-2 Total Et Bit 3 [DxyC3] Output 12T3 16 Ground GND 17 Ch. #1-2 Total Et Bit 4 [DxyC4] Output 12T4 18 Ground GND 19 Ch. #1-2 Total Et Bit 5 [DxyC5] Output 12T5 20 Ground GND 21 Ch. #1-2 Total Et Bit 6 [DxyC6] Output 12T6 22 Ground GND 23 Ch. #1-2 Total Et Bit 7 [DxyC7] Output 12T7 24 Ground GND ------------------------------------------------------------------------ J310: 24-pin connector to Paddleboard for Channel #2 EM Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #2-1 EM Et CREQ* [DxyC10] In/Out 21EREQ 2 Ground GND 3 Ch. #2-1 EM Et CSTRB* [DxyC8] Output 21ESTB 4 Ground GND 5 Ch. #2-1 EM Et CACK* [DxyC11] In/Out 21EACK 6 Ground GND 7 Ch. #2-1 EM Et CRDY* [DxyC9] Input 21ERDY 8 Ground GND 9 Ch. #2-1 EM Et Bit 0 [DxyC0] Output 21E0 10 Ground GND 11 Ch. #2-1 EM Et Bit 1 [DxyC1] Output 21E1 12 Ground GND 13 Ch. #2-1 EM Et Bit 2 [DxyC2] Output 21E2 14 Ground GND 15 Ch. #2-1 EM Et Bit 3 [DxyC3] Output 21E3 16 Ground GND 17 Ch. #2-1 EM Et Bit 4 [DxyC4] Output 21E4 18 Ground GND 19 Ch. #2-1 EM Et Bit 5 [DxyC5] Output 21E5 20 Ground GND 21 Ch. #2-1 EM Et Bit 6 [DxyC6] Output 21E6 22 Ground GND 23 Ch. #2-1 EM Et Bit 7 [DxyC7] Output 21E7 24 Ground GND ------------------------------------------------------------------------ J311: 24-pin connector to Paddleboard for Channel #2 EM Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #2-2 EM Et CREQ* [DxyC10] In/Out 22EREQ 2 Ground GND 3 Ch. #2-2 EM Et CSTRB* [DxyC8] Output 22ESTB 4 Ground GND 5 Ch. #2-2 EM Et CACK* [DxyC11] In/Out 22EACK 6 Ground GND 7 Ch. #2-2 EM Et CRDY* [DxyC9] Input 22ERDY 8 Ground GND 9 Ch. #2-2 EM Et Bit 0 [DxyC0] Output 22E0 10 Ground GND 11 Ch. #2-2 EM Et Bit 1 [DxyC1] Output 22E1 12 Ground GND 13 Ch. #2-2 EM Et Bit 2 [DxyC2] Output 22E2 14 Ground GND 15 Ch. #2-2 EM Et Bit 3 [DxyC3] Output 22E3 16 Ground GND 17 Ch. #2-2 EM Et Bit 4 [DxyC4] Output 22E4 18 Ground GND 19 Ch. #2-2 EM Et Bit 5 [DxyC5] Output 22E5 20 Ground GND 21 Ch. #2-2 EM Et Bit 6 [DxyC6] Output 22E6 22 Ground GND 23 Ch. #2-2 EM Et Bit 7 [DxyC7] Output 22E7 24 Ground GND ------------------------------------------------------------------------ J312: 24-pin connector to Paddleboard for Channel #2 Total Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #2-1 Total Et CREQ* [DxyC10] In/Out 21TREQ 2 Ground GND 3 Ch. #2-1 Total Et CSTRB* [DxyC8] Output 21TSTB 4 Ground GND 5 Ch. #2-1 Total Et CACK* [DxyC11] In/Out 21TACK 6 Ground GND 7 Ch. #2-1 Total Et CRDY* [DxyC9] Input 21TRDY 8 Ground GND 9 Ch. #2-1 Total Et Bit 0 [DxyC0] Output 21T0 10 Ground GND 11 Ch. #2-1 Total Et Bit 1 [DxyC1] Output 21T1 12 Ground GND 13 Ch. #2-1 Total Et Bit 2 [DxyC2] Output 21T2 14 Ground GND 15 Ch. #2-1 Total Et Bit 3 [DxyC3] Output 21T3 16 Ground GND 17 Ch. #2-1 Total Et Bit 4 [DxyC4] Output 21T4 18 Ground GND 19 Ch. #2-1 Total Et Bit 5 [DxyC5] Output 21T5 20 Ground GND 21 Ch. #2-1 Total Et Bit 6 [DxyC6] Output 21T6 22 Ground GND 23 Ch. #2-1 Total Et Bit 7 [DxyC7] Output 21T7 24 Ground GND ------------------------------------------------------------------------ J313: 24-pin connector to Paddleboard for Channel #2 Total Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #2-2 Total Et CREQ* [DxyC10] In/Out 22TREQ 2 Ground GND 3 Ch. #2-2 Total Et CSTRB* [DxyC8] Output 22TSTB 4 Ground GND 5 Ch. #2-2 Total Et CACK* [DxyC11] In/Out 22TACK 6 Ground GND 7 Ch. #2-2 Total Et CRDY* [DxyC9] Input 22TRDY 8 Ground GND 9 Ch. #2-2 Total Et Bit 0 [DxyC0] Output 22T0 10 Ground GND 11 Ch. #2-2 Total Et Bit 1 [DxyC1] Output 22T1 12 Ground GND 13 Ch. #2-2 Total Et Bit 2 [DxyC2] Output 22T2 14 Ground GND 15 Ch. #2-2 Total Et Bit 3 [DxyC3] Output 22T3 16 Ground GND 17 Ch. #2-2 Total Et Bit 4 [DxyC4] Output 22T4 18 Ground GND 19 Ch. #2-2 Total Et Bit 5 [DxyC5] Output 22T5 20 Ground GND 21 Ch. #2-2 Total Et Bit 6 [DxyC6] Output 22T6 22 Ground GND 23 Ch. #2-2 Total Et Bit 7 [DxyC7] Output 22T7 24 Ground GND ------------------------------------------------------------------------ J320: 24-pin connector to Paddleboard for Channel #3 EM Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #3-1 EM Et CREQ* [DxyC10] In/Out 31EREQ 2 Ground GND 3 Ch. #3-1 EM Et CSTRB* [DxyC8] Output 31ESTB 4 Ground GND 5 Ch. #3-1 EM Et CACK* [DxyC11] In/Out 31EACK 6 Ground GND 7 Ch. #3-1 EM Et CRDY* [DxyC9] Input 31ERDY 8 Ground GND 9 Ch. #3-1 EM Et Bit 0 [DxyC0] Output 31E0 10 Ground GND 11 Ch. #3-1 EM Et Bit 1 [DxyC1] Output 31E1 12 Ground GND 13 Ch. #3-1 EM Et Bit 2 [DxyC2] Output 31E2 14 Ground GND 15 Ch. #3-1 EM Et Bit 3 [DxyC3] Output 31E3 16 Ground GND 17 Ch. #3-1 EM Et Bit 4 [DxyC4] Output 31E4 18 Ground GND 19 Ch. #3-1 EM Et Bit 5 [DxyC5] Output 31E5 20 Ground GND 21 Ch. #3-1 EM Et Bit 6 [DxyC6] Output 31E6 22 Ground GND 23 Ch. #3-1 EM Et Bit 7 [DxyC7] Output 31E7 24 Ground GND ------------------------------------------------------------------------ J321: 24-pin connector to Paddleboard for Channel #3 EM Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #3-2 EM Et CREQ* [DxyC10] In/Out 32EREQ 2 Ground GND 3 Ch. #3-2 EM Et CSTRB* [DxyC8] Output 32ESTB 4 Ground GND 5 Ch. #3-2 EM Et CACK* [DxyC11] In/Out 32EACK 6 Ground GND 7 Ch. #3-2 EM Et CRDY* [DxyC9] Input 32ERDY 8 Ground GND 9 Ch. #3-2 EM Et Bit 0 [DxyC0] Output 32E0 10 Ground GND 11 Ch. #3-2 EM Et Bit 1 [DxyC1] Output 32E1 12 Ground GND 13 Ch. #3-2 EM Et Bit 2 [DxyC2] Output 32E2 14 Ground GND 15 Ch. #3-2 EM Et Bit 3 [DxyC3] Output 32E3 16 Ground GND 17 Ch. #3-2 EM Et Bit 4 [DxyC4] Output 32E4 18 Ground GND 19 Ch. #3-2 EM Et Bit 5 [DxyC5] Output 32E5 20 Ground GND 21 Ch. #3-2 EM Et Bit 6 [DxyC6] Output 32E6 22 Ground GND 23 Ch. #3-2 EM Et Bit 7 [DxyC7] Output 32E7 24 Ground GND ------------------------------------------------------------------------ J322: 24-pin connector to Paddleboard for Channel #3 Total Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #3-1 Total Et CREQ* [DxyC10] In/Out 31TREQ 2 Ground GND 3 Ch. #3-1 Total Et CSTRB* [DxyC8] Output 31TSTB 4 Ground GND 5 Ch. #3-1 Total Et CACK* [DxyC11] In/Out 31TACK 6 Ground GND 7 Ch. #3-1 Total Et CRDY* [DxyC9] Input 31TRDY 8 Ground GND 9 Ch. #3-1 Total Et Bit 0 [DxyC0] Output 31T0 10 Ground GND 11 Ch. #3-1 Total Et Bit 1 [DxyC1] Output 31T1 12 Ground GND 13 Ch. #3-1 Total Et Bit 2 [DxyC2] Output 31T2 14 Ground GND 15 Ch. #3-1 Total Et Bit 3 [DxyC3] Output 31T3 16 Ground GND 17 Ch. #3-1 Total Et Bit 4 [DxyC4] Output 31T4 18 Ground GND 19 Ch. #3-1 Total Et Bit 5 [DxyC5] Output 31T5 20 Ground GND 21 Ch. #3-1 Total Et Bit 6 [DxyC6] Output 31T6 22 Ground GND 23 Ch. #3-1 Total Et Bit 7 [DxyC7] Output 31T7 24 Ground GND ------------------------------------------------------------------------ J323: 24-pin connector to Paddleboard for Channel #3 Total Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #3-2 Total Et CREQ* [DxyC10] In/Out 32TREQ 2 Ground GND 3 Ch. #3-2 Total Et CSTRB* [DxyC8] Output 32TSTB 4 Ground GND 5 Ch. #3-2 Total Et CACK* [DxyC11] In/Out 32TACK 6 Ground GND 7 Ch. #3-2 Total Et CRDY* [DxyC9] Input 32TRDY 8 Ground GND 9 Ch. #3-2 Total Et Bit 0 [DxyC0] Output 32T0 10 Ground GND 11 Ch. #3-2 Total Et Bit 1 [DxyC1] Output 32T1 12 Ground GND 13 Ch. #3-2 Total Et Bit 2 [DxyC2] Output 32T2 14 Ground GND 15 Ch. #3-2 Total Et Bit 3 [DxyC3] Output 32T3 16 Ground GND 17 Ch. #3-2 Total Et Bit 4 [DxyC4] Output 32T4 18 Ground GND 19 Ch. #3-2 Total Et Bit 5 [DxyC5] Output 32T5 20 Ground GND 21 Ch. #3-2 Total Et Bit 6 [DxyC6] Output 32T6 22 Ground GND 23 Ch. #3-2 Total Et Bit 7 [DxyC7] Output 32T7 24 Ground GND ------------------------------------------------------------------------ J330: 24-pin connector to Paddleboard for Channel #4 EM Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #4-1 EM Et CREQ* [DxyC10] In/Out 41EREQ 2 Ground GND 3 Ch. #4-1 EM Et CSTRB* [DxyC8] Output 41ESTB 4 Ground GND 5 Ch. #4-1 EM Et CACK* [DxyC11] In/Out 41EACK 6 Ground GND 7 Ch. #4-1 EM Et CRDY* [DxyC9] Input 41ERDY 8 Ground GND 9 Ch. #4-1 EM Et Bit 0 [DxyC0] Output 41E0 10 Ground GND 11 Ch. #4-1 EM Et Bit 1 [DxyC1] Output 41E1 12 Ground GND 13 Ch. #4-1 EM Et Bit 2 [DxyC2] Output 41E2 14 Ground GND 15 Ch. #4-1 EM Et Bit 3 [DxyC3] Output 41E3 16 Ground GND 17 Ch. #4-1 EM Et Bit 4 [DxyC4] Output 41E4 18 Ground GND 19 Ch. #4-1 EM Et Bit 5 [DxyC5] Output 41E5 20 Ground GND 21 Ch. #4-1 EM Et Bit 6 [DxyC6] Output 41E6 22 Ground GND 23 Ch. #4-1 EM Et Bit 7 [DxyC7] Output 41E7 24 Ground GND ------------------------------------------------------------------------ J321: 24-pin connector to Paddleboard for Channel #4 EM Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #4-2 EM Et CREQ* [DxyC10] In/Out 42EREQ 2 Ground GND 3 Ch. #4-2 EM Et CSTRB* [DxyC8] Output 42ESTB 4 Ground GND 5 Ch. #4-2 EM Et CACK* [DxyC11] In/Out 42EACK 6 Ground GND 7 Ch. #4-2 EM Et CRDY* [DxyC9] Input 42ERDY 8 Ground GND 9 Ch. #4-2 EM Et Bit 0 [DxyC0] Output 42E0 10 Ground GND 11 Ch. #4-2 EM Et Bit 1 [DxyC1] Output 42E1 12 Ground GND 13 Ch. #4-2 EM Et Bit 2 [DxyC2] Output 42E2 14 Ground GND 15 Ch. #4-2 EM Et Bit 3 [DxyC3] Output 42E3 16 Ground GND 17 Ch. #4-2 EM Et Bit 4 [DxyC4] Output 42E4 18 Ground GND 19 Ch. #4-2 EM Et Bit 5 [DxyC5] Output 42E5 20 Ground GND 21 Ch. #4-2 EM Et Bit 6 [DxyC6] Output 42E6 22 Ground GND 23 Ch. #4-2 EM Et Bit 7 [DxyC7] Output 42E7 24 Ground GND ------------------------------------------------------------------------ J322: 24-pin connector to Paddleboard for Channel #4 Total Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #4-1 Total Et CREQ* [DxyC10] In/Out 41TREQ 2 Ground GND 3 Ch. #4-1 Total Et CSTRB* [DxyC8] Output 41TSTB 4 Ground GND 5 Ch. #4-1 Total Et CACK* [DxyC11] In/Out 41TACK 6 Ground GND 7 Ch. #4-1 Total Et CRDY* [DxyC9] Input 41TRDY 8 Ground GND 9 Ch. #4-1 Total Et Bit 0 [DxyC0] Output 41T0 10 Ground GND 11 Ch. #4-1 Total Et Bit 1 [DxyC1] Output 41T1 12 Ground GND 13 Ch. #4-1 Total Et Bit 2 [DxyC2] Output 41T2 14 Ground GND 15 Ch. #4-1 Total Et Bit 3 [DxyC3] Output 41T3 16 Ground GND 17 Ch. #4-1 Total Et Bit 4 [DxyC4] Output 41T4 18 Ground GND 19 Ch. #4-1 Total Et Bit 5 [DxyC5] Output 41T5 20 Ground GND 21 Ch. #4-1 Total Et Bit 6 [DxyC6] Output 41T6 22 Ground GND 23 Ch. #4-1 Total Et Bit 7 [DxyC7] Output 41T7 24 Ground GND ------------------------------------------------------------------------ J323: 24-pin connector to Paddleboard for Channel #4 Total Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #4-2 Total Et CREQ* [DxyC10] In/Out 42TREQ 2 Ground GND 3 Ch. #4-2 Total Et CSTRB* [DxyC8] Output 42TSTB 4 Ground GND 5 Ch. #4-2 Total Et CACK* [DxyC11] In/Out 42TACK 6 Ground GND 7 Ch. #4-2 Total Et CRDY* [DxyC9] Input 42TRDY 8 Ground GND 9 Ch. #4-2 Total Et Bit 0 [DxyC0] Output 42T0 10 Ground GND 11 Ch. #4-2 Total Et Bit 1 [DxyC1] Output 42T1 12 Ground GND 13 Ch. #4-2 Total Et Bit 2 [DxyC2] Output 42T2 14 Ground GND 15 Ch. #4-2 Total Et Bit 3 [DxyC3] Output 42T3 16 Ground GND 17 Ch. #4-2 Total Et Bit 4 [DxyC4] Output 42T4 18 Ground GND 19 Ch. #4-2 Total Et Bit 5 [DxyC5] Output 42T5 20 Ground GND 21 Ch. #4-2 Total Et Bit 6 [DxyC6] Output 42T6 22 Ground GND 23 Ch. #4-2 Total Et Bit 7 [DxyC7] Output 42T7 24 Ground GND ------------------------------------------------------------------------ J340: 24-pin connector to Paddleboard for Channel #5 EM Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #5-1 EM Et CREQ* [DxyC10] In/Out 51EREQ 2 Ground GND 3 Ch. #5-1 EM Et CSTRB* [DxyC8] Output 51ESTB 4 Ground GND 5 Ch. #5-1 EM Et CACK* [DxyC11] In/Out 51EACK 6 Ground GND 7 Ch. #5-1 EM Et CRDY* [DxyC9] Input 51ERDY 8 Ground GND 9 Ch. #5-1 EM Et Bit 0 [DxyC0] Output 51E0 10 Ground GND 11 Ch. #5-1 EM Et Bit 1 [DxyC1] Output 51E1 12 Ground GND 13 Ch. #5-1 EM Et Bit 2 [DxyC2] Output 51E2 14 Ground GND 15 Ch. #5-1 EM Et Bit 3 [DxyC3] Output 51E3 16 Ground GND 17 Ch. #5-1 EM Et Bit 4 [DxyC4] Output 51E4 18 Ground GND 19 Ch. #5-1 EM Et Bit 5 [DxyC5] Output 51E5 20 Ground GND 21 Ch. #5-1 EM Et Bit 6 [DxyC6] Output 51E6 22 Ground GND 23 Ch. #5-1 EM Et Bit 7 [DxyC7] Output 51E7 24 Ground GND ------------------------------------------------------------------------ J341: 24-pin connector to Paddleboard for Channel #5 EM Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #5-2 EM Et CREQ* [DxyC10] In/Out 52EREQ 2 Ground GND 3 Ch. #5-2 EM Et CSTRB* [DxyC8] Output 52ESTB 4 Ground GND 5 Ch. #5-2 EM Et CACK* [DxyC11] In/Out 52EACK 6 Ground GND 7 Ch. #5-2 EM Et CRDY* [DxyC9] Input 52ERDY 8 Ground GND 9 Ch. #5-2 EM Et Bit 0 [DxyC0] Output 52E0 10 Ground GND 11 Ch. #5-2 EM Et Bit 1 [DxyC1] Output 52E1 12 Ground GND 13 Ch. #5-2 EM Et Bit 2 [DxyC2] Output 52E2 14 Ground GND 15 Ch. #5-2 EM Et Bit 3 [DxyC3] Output 52E3 16 Ground GND 17 Ch. #5-2 EM Et Bit 4 [DxyC4] Output 52E4 18 Ground GND 19 Ch. #5-2 EM Et Bit 5 [DxyC5] Output 52E5 20 Ground GND 21 Ch. #5-2 EM Et Bit 6 [DxyC6] Output 52E6 22 Ground GND 23 Ch. #5-2 EM Et Bit 7 [DxyC7] Output 52E7 24 Ground GND ------------------------------------------------------------------------ J342: 24-pin connector to Paddleboard for Channel #5 Total Et Copy #1 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #5-1 Total Et CREQ* [DxyC10] In/Out 51TREQ 2 Ground GND 3 Ch. #5-1 Total Et CSTRB* [DxyC8] Output 51TSTB 4 Ground GND 5 Ch. #5-1 Total Et CACK* [DxyC11] In/Out 51TACK 6 Ground GND 7 Ch. #5-1 Total Et CRDY* [DxyC9] Input 51TRDY 8 Ground GND 9 Ch. #5-1 Total Et Bit 0 [DxyC0] Output 51T0 10 Ground GND 11 Ch. #5-1 Total Et Bit 1 [DxyC1] Output 51T1 12 Ground GND 13 Ch. #5-1 Total Et Bit 2 [DxyC2] Output 51T2 14 Ground GND 15 Ch. #5-1 Total Et Bit 3 [DxyC3] Output 51T3 16 Ground GND 17 Ch. #5-1 Total Et Bit 4 [DxyC4] Output 51T4 18 Ground GND 19 Ch. #5-1 Total Et Bit 5 [DxyC5] Output 51T5 20 Ground GND 21 Ch. #5-1 Total Et Bit 6 [DxyC6] Output 51T6 22 Ground GND 23 Ch. #5-1 Total Et Bit 7 [DxyC7] Output 51T7 24 Ground GND ------------------------------------------------------------------------ J343: 24-pin connector to Paddleboard for Channel #5 Total Et Copy #2 ------------------------------------------------------------------------ Pin# Signal Description Direction Mnemonic ---- ------------------ --------- -------- 1 Ch. #5-2 Total Et CREQ* [DxyC10] In/Out 52TREQ 2 Ground GND 3 Ch. #5-2 Total Et CSTRB* [DxyC8] Output 52TSTB 4 Ground GND 5 Ch. #5-2 Total Et CACK* [DxyC11] In/Out 52TACK 6 Ground GND 7 Ch. #5-2 Total Et CRDY* [DxyC9] Input 52TRDY 8 Ground GND 9 Ch. #5-2 Total Et Bit 0 [DxyC0] Output 52T0 10 Ground GND 11 Ch. #5-2 Total Et Bit 1 [DxyC1] Output 52T1 12 Ground GND 13 Ch. #5-2 Total Et Bit 2 [DxyC2] Output 52T2 14 Ground GND 15 Ch. #5-2 Total Et Bit 3 [DxyC3] Output 52T3 16 Ground GND 17 Ch. #5-2 Total Et Bit 4 [DxyC4] Output 52T4 18 Ground GND 19 Ch. #5-2 Total Et Bit 5 [DxyC5] Output 52T5 20 Ground GND 21 Ch. #5-2 Total Et Bit 6 [DxyC6] Output 52T6 22 Ground GND 23 Ch. #5-2 Total Et Bit 7 [DxyC7] Output 52T7 24 Ground GND ------------------------------------------ CURRENT REQUIREMENTS FOR THE CRC ------------------------------------------ Component N V Imin Imax NImin NImax --------- --- --- ------ ------ ------- ------- F100325 17 +5V 0.065A ~~~~ 1.105A ~~~~ -5V 0.017A 0.037A 0.289A 0.629A F100324 5 +5V 0.038A ~~~~ 0.190A ~~~~ -5V 0.070A 0.022A 0.110A 0.350A 74ALS540 3 +5V 0.005A 0.022A 0.015A 0.066A 74ALS541 4 +5V 0.005A 0.022A 0.020A 0.088A 74AS573 20 +5V 0.010A 0.027A 0.200A 0.540A 74HCT20 5 +5V 0.04mA 0.001A 0.20mA 0.005A 74HCT32 5 +5V 0.04mA 0.001A 0.20mA 0.005A 16RA8 10 +5V 0.170A ~~~~ 1.700A ~~~~ Oscillator 1 +5V ~~~~ 0.001A ~~~~ 0.001A LED's 1 +5V 0.011A ~~~~ 0.011A ~~~~ 1 -2V 0.011A ~~~~ 0.011A ~~~~ 1 -5V 0.011A ~~~~ 0.011A ~~~~ Resistors 10 -2V ~~~~ 0.012A ~~~~ 0.120A - Pull Up 80* +5V ~~~~ 0.50mA ~~~~ 0.040A - Pull Down 80* -5V ~~~~ 0.05mA ~~~~ 0.040A ---------------------------------------------------------- Total at +5V 3.241A 3.751A Total at -2V 0.011A 0.131A Total at -5V 0.410A 1.030A * - This includes the possible use of the control signal pull up/pull down resistors, which may or may not be used, at an assumed value of 10K Ohms. ------------------------------------------ NOTE: FIFO Structure (Lack of) ------------------------------------------ The CRC does not provide any FIFO-type action. It has been argued that perhaps it should, to separate the ERPB-to-CRC transfer from the CRC-to-DSP transfer. The difficulty with FIFO-ing the data passing through the CRC is the following: what to do if it "breaks"? That is, how does the FIFO "walk out of" an error? The CRC-to-DSP transfer is unidirectional (this is considered essential). The DSP cannot directly talk to the CRC (at least through the obvious channel of the COM port). The CRC has no connection to anything else that could do the job. Therefore, unless a new connection to the CRC is added (for example, from the 68K), it is not possible to recover from FIFO errors, and putting a FIFO on the CRC is not useful. ----------- ECO History ----------- The most recent revision of the CRC card is Revision A. It requires a few ECOs for correct operation: (1) Crystal (X1) The socket for crystal Y1 is the incorrect size. To install Y1, bend pins 1 and 4 (the Ground and Output pins) by 0.1" so that they fit in the socket. Wrap Kapton tape around the body of the crystal to insulate these pins from the body of the crystal (which is at ground potential). (note: see ECO (2) for additional crystal-related ECOs) (2) Token Grabber PALs (U64, U65, U66, U67, U68) The CRC was designed for 16RA8 PALs, but actually uses 16V8 PALs. To allow the Token Grabber 16V8 PAL to work, the following modifications must be made: Cut --- the cosmetic trace connecting the two pins of the WRAP2 jumpers connected to pin 1 of each of the following ICs: U64, U65, U66, U67, U68 Connect ------- pin 8 to pin 1 on each of the following ICs: U64, U65, U66, U67, U68 (note that this can be done simply by forming a wire-wrap wire to the appropriate length and inserting the ends into the appropriate socket holes, along with the Token Grabber PAL. The wire-wrap wire will then be safely between the IC and the socket, and no soldering is required) Replace ------- The 10MHz crystal Y1 with a 1MHz crystal. (note: see ECO (1) for additional crystal-related ECOs) Change the schematic (pages 15-16) ---------------------------------- Change the Type Designator from PAL16RA8 to PALCE16V8 on the following ICs: U64, U65, U66, U67, U68 Show the connection between pin 8 and pin 1 of each of the following ICs: U64, U65, U66, U67, U68 Change the value field from 10MHz to 1MHz on crystal Y1 (3) Strobe Clipper PALs (U48, U53, U55, U56, U57) The CRC was designed for 16RA8 PALs, but actually uses 16V8 PALs. To allow the Strobe Clipper 16V8 PAL to work, the following modification must be made: Connect ------- pin 12 to pin 7 on each of the following ICs: U48, U53, U55, U56, U57 (note that this can be done simply by forming a wire-wrap wire to the appropriate length and inserting the ends into the appropriate socket holes, along with the Token Grabber PAL. The wire-wrap wire will then be safely between the IC and the socket, and no soldering is required) Change the schematic (page 14) ------------------------------ Change the Type Designator from PAL16RA8 to PALCE16V8 on the following ICs: U48, U53, U55, U56, U57 Show the connection between pin 12 and pin 7 of each of the following ICs: U48, U53, U55, U56, U57 (4) /CREQ series-terminating and pull-down resistors The circuitry for driving the /CREQ signal from the CRC to the Hydra card is incorrect. The following changes must be made: Replace ------- The 20K ohm resistor with a 750 ohm resistor at the following locations: R69, R89, R131, R137, R71, R73, R143, R149, R75, R77, R155, R161, R79, R81, R167, R173, R83, R84, R179, R185 (note: these locations are designed for 1/8 watt resistors but 1/4 watt resistors can be used if installed carefully) Install ------- 8.2K ohm resistors at the following locations: R90, R93, R129, R135, R97, R101, R141, R147, R105, R109, R153, R159, R113, R117, R165, R171, R120, R125, R177, R183 (note: these locations are designed for 1/8 watt resistors but 1/4 watt resistors can be used if installed carefully) Wire-wrap wires between VEE and pin 2 of each of the following WRAP2 jumper blocks: J200, J188, J195, J201, J207, J213, J239, J208, J216, J222, J245, J217, J225, J231, J251, J236, J234, J264, J257, J269 Wire-wrap wires between the /CREQ positions of all of the WRAP2 pull-up/down blocks and the -4.5V power plane. The easiest way to do this is to bus all of the /CREQ_1 positions together on one bus, bus all of the /CREQ_2 positions together on another bus, connect the two busses together with a single wire, and then connect this composite bus to a convenient -4.5V supply (for example, the -4.5V pin of C80). Change the schematic (pages 17-21) ---------------------------------- Change the Type Designator field from RES203 to RES751, and change the value field from 20K ohms to 750 ohms for the following resistors: R69, R89, R131, R137, R71, R73, R143, R149, R75, R77, R155, R161, R79, R81, R167, R173, R83, R84, R179, R185 Show the following resistors as 8.2K ohm resistors connected to -4.5V: R90, R93, R129, R135, R97, R101, R141, R147, R105, R109, R153, R159, R113, R117, R165, R171, R120, R125, R177, R183 (5) Tokens Grabbed indicator LEDs (D14, D15, D16, D17, D18) The LEDs which indicate "All Tokens Grabbed" are more useful if they show "One or More Tokens Not Grabbed." In this way, they turn ON if one or more tokens are missing. It is much easier to see an LED turn on intermittently than to see it turn off. Replace ------- The 74HCT32 chips with 74HCT08 chips at locations: U60, U61, U62, U63, U69 Change the schematic (page 23) ------------------------------ Change the Type Designator field from 74AS32 to 74HCT08 at locations: U60, U61, U62, U63, U69 Change the notation text "All Tokens Grabbed" to "One or More Tokens Not Grabbed" near D14. Chance PCB Text --------------- Change the silkscreen text "All Tokens Grabbed" to "One or More Tokens Not Grabbed" near the row of token LEDs. (6) General schematic clarifications There are some clarifications to make on the schematic which do not correspond to circuit changes. Rather, these clarifications either illustrate the locations of cosmetic copper on the PCB as manufactured, or more clearly specify the device used on the PCB as built. Change the schematic -------------------- pages 9-11: pins 1 and 2 are connected on each of: J84, J95, J88, J92, J96 pages 12-13: pins 1 and 2 are connected on each of: J57, J66, J59, J52, J53, J54, J55, J56, J63, J64, J127, J111, J129, J114, J131, J117, J133, J120, J135, J123 page 14: pins 1 and 2 are connected on each of: J145, J146, J147, J148, J149, J150, J155, J156 J152, J163 (note: see ECO (3) for other schematic changes on page 14) pages 15-16: pins 1 and 2 are connected on each of: J189, J190, J191, J192, J194, J157, J151 all of the text "CH x TOT CACK DELAY x" and "CH x EM CACK DELAY x" near WRAP2 jumpers is meaningless. These WRAP2 jumpers provide testpoints for some internal processing in the Token Grabber PALs. They are only connected to these PALs and have no connection elsewhere on the CRC PCB. They can be re-labelled "NO CONNECTION." (note: see ECO (2) for other schematic changes on pages 15-16) pages 17-21: note that the following resistors ARE NOT installed on the CRC PCB: R87, R85, R93, R91, R129, R127, R135, R133 R97, R95, R101, R99, R141, R139, R147, R145 R105, R103, R109, R107, R153, R151, R159, R157 R113, R111, R117, R115, R165, R163, R171, R169 R120, R119, R125, R123, R177, R175, R183, R181 all "valueless" resistors on these pages are to be 110 ohm resistors. pins 1 of the following jumpers pairs are connected together: J199-J258, J204-J252, J196-J255, J186-J253 J242-J266, J212-J268, J205-J270, J209-J265 J248-J241, J221-J246, J214-J240, J218-J244 J254-J219, J230-J228, J223-J224, J227-J220 J260-J211, J272-J203, J232-J187, J261-J202 (note: see ECO (4) for other schematic changes on pages 17-21) page 24: Change the Type Designator from 74AS20 to 74HCT20 for the following ICs: U47, U49, U50, U51, U52 pins 1 and 2 are connected on each of: J137, J138, J154, J158, J161, J170, J139, J142, J140, J143