ERPB and DC Project Record Energy Readout Paddle Board and Distributor Card Steve Pier for the D0 Calorimeter Level 1.5 Project Department of Physics University of California, Irvine Irvine, CA 92717-4575 USA About this Documentation Revision history: rev 1.0: May 25, 1994 This document was created using Microsoft Word version 2.0c. The timing diagrams appended to printed versions of this document were translated from a text format to HPGL using the program HPWAVE.exe. The schematics appended to printed versions of this document were created with OrCAD Schematic Design Tools 386+ version 1.10A. See the appendix for more information on computer files related to this project. Acknowledgments J. Dane, R. Schwarz (UC Irvine), R. Bard (Maryland) for the D0 Calorimeter Level 1.5 Project: J. Drinkard, A. Lankford (UC Irvine), D. Edmunds, S. Gross (MSU) The following corporations provided reduced product pricing or other forms of academic support: National Semiconductor Texas Instruments Xilinx Table of Contents About this Documentation............................i Acknowledgments.....................................i Overview............................................3 Operation...........................................3 LCA Configuration..............................3 Data Reception from CTFE's.....................3 Data Transmission to CRC's.....................5 Installation Reference..............................5 Introduction...................................5 ERPB Configuration Board.......................6 Distributor Card (DC)..........................6 Energy Readout Paddle Board (ERPB).............9 MTG Interface..................................11 Initially Implemented Features......................14 Initial LCA Configurations.....................14 Multiple Readout Orders........................14 Nine-bit to Eight-bit Packing..................16 Data Buffering.................................16 Future Capabilities.................................16 High-Speed Data Reception......................16 High-Speed Readout.............................16 Fault Reporting................................17 Run-Time Data Path Diagnostics.................17 Remote Control of the DC.......................17 Long-Term Hardware Support..........................18 Spares.........................................18 LCA Configuration..............................18 Scheduling..........................................18 Funding.............................................20 Manufacture.........................................21 ERPB...........................................21 DC.............................................22 Burn-in and Test....................................22 DC.............................................22 ERPB...........................................23 ERPB Automated Test............................23 Modifications.......................................24 XMIT_STB generation on DC......................24 Appendices..........................................25 Acronyms and Terminology.......................25 Computer Files.................................27 Bills of Materials.............................29 LCA Configuration Text Files...................32 GAL and PROM Text Files........................62 Timing Diagrams................................73 Overview -------- This document describes UCI's hardware contributions to the D0 Calorimeter Level 1.5 Trigger Upgrade Project. It is meant to serve not only as a technical description, but also as a broad record of design, manufacture, and testing. D0 is the D0 detector at Fermi National Accelerator Laboratory (FNAL). The calorimeter is the part of the detector that directly measures particle energy. The trigger is the electronic system that decides which beam crossings produced interactions of sufficient interest to have their data permanently recorded. The trigger upgrade allows certain triggering decisions to be made partially on the basis of DSP analysis of calorimeter data. Three types of cards work together to move data from the Calorimeter Trigger Front End (CTFE) cards to the DSP's. Two of these were supplied by UCI, the third by MSU: Designed at Number in Number of Description (Card) University System Spares ------------------ ----------- ------ --------- Cable Receiver Card (CRC) MSU 2* 1* Distributor Card (DC) UCI 10 6** Energy Readout (ERPB) UCI 80 13 Paddle Board * Two more CRC's may be added to the system in the future. Only one spare is assembled. Parts exist to build eight more CRC's. ** The six DC spares include three of the prototype DC's. Operation --------- LCA Configuration ----------------- The logic of an LCA is determined by bits stored in on-chip RAM. This RAM must be loaded with the proper configuration after powerup. The yellow LED on each ERPB is lit whenever any of the eight LCA's is not yet configured. The configuration data bits are stored in a Serial Configuration PROM (SCP) located on the DC. The data bits are loaded serially via three LCA pins. The system can be set up so that a single SCP on the master DC loads all LCA's in all racks. The LCA configuration process can be triggered manually by pressing the SW3 pushbutton on the DC. The preferred method, however, is to trigger configuration from the MTG. See the Installation Reference section for details. Data Reception from CTFE's -------------------------- Each CTFE has four output channels. Each channel outputs two 9-bit words per beam crossing. These two words, Total Et (Total) and Electromagnetic Et (EM)are time-multiplexed, with Total being presented at the CTFE output first. A single ERPB connects to four CTFE's, for a total of sixteen data channels. On the ERPB, CTFE data channels are immediately translated from differential ECL to TTL levels. The TTL versions are then connected to Logic Cell Arrays (LCA's). Each LCA handles two channels, so there are eight LCA's on an ERPB. The LCA's do the following: 1. The LCA's pack the nine CTFE data bits into eight bits. Data packing is currently implemented as saturation on overflow. I.e., each of the eight LSB's is OR'd with the MSB. Other schemes can be implemented in the future; EM and Total need not use the same scheme. 2. The LCA's segregate Total Et and EM Et. EM and Total have separate packers, buffers and readout registers. EM and Total are first segregated in the buffers, since each buffer has its own write strobe. TOTAL_we is active when Total data are valid; EM_we is active when EM data are valid. The EM and Total readout registers have a common clock, Readout_CLK, since EM and Total data are read out in parallel. 3. The LCA's buffer data from several beam crossings. In the current implementation, data from only a single beam crossing must be buffered, so the buffer is simply a register. As beam crossing rate increases, more data will require buffering, and the buffer design will become more complex. A CLB in an LCA can be configured as two 16x1 bit RAM's or a single 1x32 bit RAM. Early in the project, to evaluate the feasibility of using the XC4002A-5PC84C LCA, a 16- deep buffer configuration was designed and found to be workable. 4. The LCA's hold a single beam crossing's data during transmission. Data transmission takes about 15 microseconds, so the trigger upgrade was designed to allow reception of new data while older data are transmitted to the DSP's. A single beam crossing's data set (EM and Total for channel A and B) is transferred to the readout register, where it remains until data transmission is complete. 5. The LCA's multiplex two data channels onto the ERPB's data bus. The ERPB has a 16-bit data bus to which all LCA's are connected. Half of the bus is used for EM data, and the other half is used for Total data. Each LCA must be able to connect either channel A or channel B to this bus. In the current implementation, a multiplexer establishes this connection, but an option that requires fewer CLB resources is to use on-chip tri-state buffers to drive an on-chip data bus. The reception of data from CTFE's is controlled by signals from the MTG: INPUT_CLK goes active when CTFE data (either EM or Total) are valid. TOTAL is high when CTFE's are outputting Total; it is low when they are outputting EM. STORE causes CTFE data to be written into the buffers. LATCH causes buffer data to be copied into the readout register. See the timing diagrams in the appendix. Data Transmission to CRC's -------------------------- Once data are waiting in thereadout register, the MTG triggers readout by briefly activating XMIT_TRIG (MTG_6). Though the DC passes this signal to the ERPB's, they ignore it. Data transmission is orchestrated by the DC's transmit sequencer and a state machine in each LCA. The sequencer and state machines are clocked by XMIT_CLK, generated on the DC. Except for XMIT_CLK, all data and control signals for transmission travel over the daisy chain cables. Transmission proceeds as follows: 1. ROEB (Register Output Enable Below) from the DC to ERPB #0 (directly below the DC) is always active, so ERPB #0 is always driving data into the DC. 2. DDCB_0 (Down Daisy Chain Below 0) is normally inactive, forcing all LCA state machines to remain in state 0. All of the LCA state machines on a given ERPB are always in the same state. When this state is 0-15, one of the eight LCA's on the ERPB is driving the data bus, and the ERPB's ROEB output is inactive. 3. The MTG activates LATCH, causing ERPB LCA's to place data in the readout latch. 4. The MTG briefly activates XMIT_TRIG. 5. The DC verifies that XMIT_TRIG is active for more than one period of XMIT_CLK. 6. The DC activates its DDCB_0 (Down Daisy Chain Below 0), which is connected to ERPB #0. 7. In response to DDCB_0 going active, all state machines on ERPB #0 begin advancing state on XMIT_CLK. 8. With each state, one LCA drives data for a single channel onto the data bus. The actual channel driven is dependent upon the state and the selected readout order. Each LCA has three hard-wired signals that tell it which LCA it is, 0- 7. This allows each LCA to determine during which states it should be driving the bus. 9. Once all sixteen channels have been driven on the bus, ERPB #0 activates its DDCB_0 output and ROEB output, allowing the next ERPB in the chain to transmit its data. 10. When all data from the ERPB's have been sent to the CRC, the sequencer on the DC releases its DDCB_0 output. This forces ERPB #0 back into state 0, in which it, too, releases its DDCB_0 output. Eventually all state machines on all ERPB's return to state 0. 11. The DC sequencer eventually resets itself and waits for the next XMIT_TRIG. During transmission, the DC creates a single strobe pulse for each data word. The strobe and data are translated to differential ECL and sent to the CRC. Currently, one data word is sent per XMIT_CLK. See the High-Speed Readout section of this document for other possibilities. See XMITB_00.tim and related timing diagrams for daisy chain timing details. Installation Reference ---------------------- Introduction ------------ This section was originally provided to MSU on March 9, 1994 in order to facilitate installation of ERPB's and DC's at FNAL. It is presented here with little editing. ERPB Configuration Board ------------------------ The ERPB configuration board is used for testing/burn-in only. It supplies all the signals necessary to configure and burn-in an ERPB, including a 16 MHz XMIT_CLK for use during burn-in. To use the configuration board, attach a 40-pin ribbon cable between the configuration board and the ERPB(s). Attach a power cable between the configuration board and H2 on one of the ERPB's. Push the pushbutton on the configuration board to trigger the configuration process. A distributor card can be used for the same purpose. See the DC section for necessary DIP switch settings. Caution: unless the cable between configuration board (or DC) and ERPB is very short, a terminator board should be connected to the end of the cable. Distributor Card (DC) --------------------- The Distributor Card (DC) provides services to the ERPB's. These services include configuring the LCA's, buffering MTG control signals, and orchestrating data transmission to the CRC. The DC generates XMIT_CLK, which controls the data transmission rate. Each rack has one DC, and all ten DC's in the system can be connected together. When connected, the entire system can use configuration signals and XMIT_CLK from a single 'master' DC. The connectors JD1 and JD2 accept the inter-DC cables. JD1 receives signals from the previous DC in the chain; JD2 sends signals to the next DC in the chain. The first DC in the chain is the master DC. This DC must have a transmit crystal (X2) and a serial configuration PROM (e.g., SCP1) installed. LED's ----- There are two LED's on a DC: green and red. green LED: when lit, this LED indicates that the entire rack is powered up. It will also light if the daisy chain cable is disconnected from the DC. When the green LED is off, drivers for all CMOS signals on the daisy chain connector are floated. red LED: this LED is currently not used. Production DC's are assembled without resistor R2, causing the LED to never light. With R2 installed, the red LED is connected to ALT MTG Register 1, so it can be controlled from the MTG. Connectors ---------- J1: connector to backplane. This is a DIN 96 connector that plugs directly into backplane pins. It is connected to ground, VEE (-5V), and -2V. -2V is not currently used. CTFE data signals on this connector are made available on JT1. J2: connector to backplane. This is a DIN 96 connector that plugs directly into backplane pins. It is connected only to ground and VCC (+5V). JT1: CTFE data connector to ERPB. This connector makes available CTFE data signals whose backplane pins are covered by J1. A ribbon cable from this connector connects to the ERPB immediately below the DC. The signals are differential ECL. JP1: parallel connector to all ERPB's in the rack. A cable from this connector connects to JP1 on each ERPB. The end of this cable should be terminated after the last ERPB. All signals are differential ECL and are driven from the DC. JB1: daisy chain connector to the ERPB just below the DC. This connector connects via a ribbon cable to JA1 on the ERPB just below the DC. Most of the signals operate at CMOS levels. JX1: transmit connector to CRC. A cable from this connector attaches to the CRC. All signals are differential ECL. Most signals are driven by the DC. There are three spare signals. These signals may be either inputs or outputs depending on the jumpers installed at H3 and H4. JM1: MTG connector. A cable from this connector attaches to the MTG. All signals are differential ECL. The MTG drives all signals. The DC has no on-board terminators for this cable. JD1: inter-DC connector. JD2: inter-DC connector. A cable between racks is driven by JD2 on one DC and received at JD1 on the next DC in the chain. The first DC in the chain, the master, has no connection to JD1. The last DC in the chain has no connection at JD2. Terminators for signals on these connectors are located on the DC. H1: auxiliary power connector. This connector can be used to supply power to the DC when it is not installed in the rack. It can also be used as a test point and to power small boards when the DC is in the rack. A nearby test point, labeled VTT, can be used to test the voltage on the VTT (terminator) plane. Jumpers ------- H2: CRC strobe delay header. A single jumper installed on this header selects the delay for the CRC data strobe. For shorter delays, install the jumper nearer to the backplane and vice versa. The delay range is approximately 5 ns to 30 ns w.r.t. XMIT_CLK. The data latches, clocked by XMIT_CLK, have a delay of 10 ns max. A modification to the DC was made to force XMIT_STB low when XMIT_CLK is low. See the Modifications section. XMIT_CLK ___/~~~~~~~\_______/~~~~ (on DC only) XMIT_DATA ====X===============X=== (on DC-to-CRC cable) XMIT_STB ________/~~\__________ (on DC-to-CRC cable) -->| |<-- delay adjustable via H2 H3: spare CRC output header. H4: spare CRC input header. Jumpers installed on these headers connect spare wires in the CRC (transmit) cable to either DC inputs or DC outputs. See the Transmit Connector schematic (DXCON.sch) for details. No jumpers are currently installed, because no spare signals are currently used. SJ1-SJ4: shorted jumper sites. SJ1-SJ4 define the connection to the VTT plane. The default is for VTT to be connected to VEE (-5V). Traces within SJ1-SJ4 must be cut to change the VTT connection. Holes connected to -2V are provided within SJ1-SJ4 for future use. SJ5-SJ22: shorted jumper sites. These shorted jumper sites consist of two through-holes that are shorted by a trace. The trace may be cut and a component (e.g., a ferrite inductor) may be installed to filter the signal. Switches -------- SW3: LCA configuration pushbutton. This pushbutton, when pressed, triggers the LCA configuration process. If the DC's are set up to be configured from the master DC, then SW3 on the master DC must be pressed to trigger configuration. SW1: ID/Mode DIP switch. This switch will be useful in the future. For now, all switches should be down. SW2: Setup DIP switch. This switch selects many modes of operation. For default operation, all switches should be down. Exception: switch #8 is used to select forward or reverse readout order. A synopsis of switch meanings is printed on the silkscreen. Meaning when switch is up --------------------------------------------------------- #1: use local (not master) LCA configuration data #2: use MTG (not SCP) as the source of LCA configuration data #3: use SCP2 (not SCP1) #4: use local (not master) transmit clock #5: disable transmission of data to the CRC #6: disable reporting of faults to the CRC #8: use reverse (not forward) readout order The default (all switches down), therefore, is: the configuration bitstream comes from SCP1 on the master DC XMIT_CLK originates on the master DC data transmission to the CRC is enabled fault reporting (via the CRC) is enabled Note: fault reporting is not currently implemented, so #6 is ignored. Programmable Chips ------------------ GAL1 16V8: Setup GAL, contains logic that helps MTG set up DC remotely. GAL2 22V10: Selection GAL, selects signals to use locally and to send to next DC. GAL3 22V10: LCA Configuration GAL, controls LCA configuration process. GAL4 22V10: Transmit GAL, controls transmit sequencer. U23 7C291: PROM holds transmission sequence (U23 is mostly fault control). U26 7C291: PROM holds transmission sequence (U26 handles most transmit signals). SCP1 1736: Serial Configuration PROM, holds one LCA configuration bitstream. SCP2 1736: Serial Configuration PROM, holds one LCA configuration bitstream. DC Crystals ----------- X1: this crystal is used for miscellaneous purposes. This crystal must be installed on all DC's. X2: this is the transmit crystal. This crystal must be installed on the master DC. This crystal must be present on any DC that uses its own (local) transmit clock. The VTT Plane ------------- Load resistors on ECL outputs (RLOAD13 resistor networks) are attached to the VTT plane. Currently, the VTT plane is connected to VEE at SJ1-SJ4, and load resistors of 330 ohms are used. SJ1-SJ4 provide the option of connecting VTT to another voltage (e.g., -2V). Terminators ----------- MTG signals are not terminated on the DC. An external terminator board is required. A terminator board is also required on the parallel cable after the last ERPB. The necessary terminators for the inter-DC cable and the spare inputs on the transmit cable (from the CRC) are provided on the DC. Power-Up Detection ------------------ There is a chance that a CMOS output driving a non-powered CMOS input can damage that input. To avoid this, power-up detection circuitry disables all CMOS outputs on all daisy chain connectors until all ERPB's and the DC are powered up. Actually, because there are only two backplanes in the rack, the only place where this problem can arise is between the lowest ERPB installed in the upper backplane and the highest ERPB installed in the lower backplane. The signals SENSE5 and PWR_UP5 are bussed signals on the daisy chain cables. A circuit on the DC senses a power failure on SENSE5. See the Daisy Chain Connector schematic (DDASY.sch). This signal is forced low by non-powered ERPB's. When all ERPB's are powered, SENSE5 goes high, and the DC's power-up detection circuit activates PWR_UP5. PWR_UP5 is used by ERPB's to enable CMOS outputs. All ERPB's have a pull-down resistor on PWR_UP5, so if the DC is not installed, PWR_UP is inactive. The DC's and ERPB's indicate that PWR_UP is active by lighting their green LED's. Energy Readout Paddle Board (ERPB) ---------------------------------- LED's ----- There are three LED's on an ERPB: green, yellow, red. These LED's are controlled by the ERPB's Fault GAL (U35), so their meaning may change in the future. green LED: when lit, this LED indicates that the entire rack is powered up. In order to light, the distributor card and daisy chain cables must be installed and all cards in the rack must be powered up. When the green LED is off, all CMOS drivers on the daisy chain connectors are floated. yellow LED: when lit, this LED indicates that at least one LCA on the ERPB is not configured. This LED will go out after the configuration process completes successfully. It may subsequently re-light if power momentarily fails, the PROG\ line is activated, etc. A yellow LED that remains on after the configuration process completes (configuration takes < 1 second) indicates a failure. The problem may be with the ERPB, the cabling, or the distributor card. red LED: this LED is currently meaningless. The current Fault GAL uses a signal, GI_0, from LCA #1 to control the LED. This signal happens to be connected through a resistor to the SEL0 jumper of H1. So if the LCA's are not configured (so their I/O pins all float), or if the LCA configuration does not drive GI_0 on LCA #1, then the LED reflects the state of the SEL0 jumper. In the future, this LED will probably have some useful purpose when the LCA's are configured. See the discussion of the ERPB's H1 header. Connectors ---------- H2: auxiliary power connector. This connector can be used as a test point, to supply power to the ERPB, or to supply power to external cards (e.g., the configuration board). JP1: parallel connector. Signals are all differential ECL inputs to ERPB. All ERPB's are connected in parallel via this connector. Diode D1 attached to this connector is not used. JA1: daisy chain connection to the board Above. JB1: daisy chain connection to the board Below. Most signals are CMOS levels. There are inputs and outputs. Many signals, though wired, buffered, etc., are not currently used. Bussed signals on this connector include: ground DFAULT\ (fault data) SENSE5 (+5V sense signal) PWR_UP5 (high if entire rack has +5V) J20: connector to backplane. This is a DIN 96 connector that plugs directly into backplane pins. It is only connected to ground and VCC (+5V). CTFE Data Connectors J1x and J3x: J10: connector to CTFE i. This is a DIN 96 connector that plugs directly into backplane pins. This connector also provides ground and VEE (-5V) connections. J11: connector to CTFE j, J12: connector to CTFE k, J13: connector to CTFE l. These are protected headers without ejectors that get cabled to the backplane. Pins 1-4 are not connected. J30: connector to CTFE i. This is a DIN 96 connector that plugs directly into backplane pins. This connector also provides ground and VCC (+5V) connections. J31: connector to CTFE j, J32: connector to CTFE k, J33: connector to CTFE l. These are protected headers with ejectors that get cabled to the backplane. Pins 1-4 are not connected. Each of the eight connectors J1x and J3x carries two channels of CTFE data. i, j, k, l are used to indicate that there are four CTFE's attached to an ERPB. For normal readout order, l is above k is above j is above i. Eccentric readout order is cabled differently. Jumpers ------- H1: SEL0/SEL1 header. This header requires one shorting jumper for each of the signals SEL0 and SEL1. Each jumper can be in one of two positions, marked 1 and 0. ERPB's are shipped with jumpers installed in the 1 position. The silkscreen is labeled with H1, SEL0, SEL1, 1, and 0. SEL0 and SEL1 are connected to all LCA's, so their meaning is dependent upon the LCA configuration. The current LCA configuration ignores SEL1 and uses SEL0 (when the jumper is in the 0 position) to select eccentric readout order. Eccentric readout order is used by the one ERPB in each rack that, due to mechanical obstructions, is installed and cabled differently than the other ERPB's. LCA #1 must drive the pins to which SEL0 and SEL1 are connected, so the LCA's latch SEL0 and SEL1 shortly after configuration. LCA #1 does not drive the pins until after all LCA's have latched SEL0 and SEL1. See the discussion of the ERPB's red LED. MTG Interface ------------- Overview -------- The MTG controls flow of data from the CTFE to the ERPB's. Miscellaneous initialization and control functions are also handled by the MTG. A long cable from the MTG connects to the DC's MTG Connector. See the MTG Connector schematic (DMTG.sch) for pinouts. All Signals on this connector are differential ECL and are driven by the MTG. The signals are called MTG_0-9. Two spare signals are called MTG_X and MTG_Y. The DC buffers MTG_0-9 and passes MTG_0-8 on to the ERPB's. The DC also translates MTG_0-9 to TTL and uses these signals locally. See the Distributor Card Overview schematic (DC.sch) for an overview of MTG signals. The meaning of most MTG signals is determined by programmable logic, so this document only describes the anticipated use of the signals. Some MTG signals are given mnemonic aliases. The use of aliases is preferred over the MTG_ names, because it may be necessary in the future (e.g., when a new LCA configuration is designed) to change which MTG signal is used for a particular alias. Summary of MTG signals: MTG Name ERPB Aliases DC Aliases -------- ------------ ---------- MTG_0 INPUT_CLK SETUP_0 MTG_1 TOTAL SETUP_1 MTG_2 STORE\ SETUP_2 MTG_3 LATCH\ SETUP_3 MTG_4 SETUP_4 MTG_5 SETUP_5 MTG_6 XMIT_TRIG SETUP_6, XMIT_TRIG MTG_7 SETUP_7 MTG_8 DC_ADR MTG_9 not connected DC_STB\ \ indicates signal is active low XMIT_TRIG is currently ignored by the ERPB's. Initialization of the DC's and ERPB's ------------------------------------- The LCA's on the ERPB's must be configured. This process may be triggered manually by pressing the pushbutton (SW3) on the master DC. Manual triggering is not recommended as a normal means of configuring the LCA's, because it does not reset the data transmission logic. Because DC_STB\ is activated when the MTG is used to trigger LCA configuration, the data transmission logic is reset. (Whenever DC_STB\ is activated, transmission logic is reset and disabled for 100 ms.) The following procedure is recommended for DC/ERPB initialization: 1. Bring MTG_7 and MTG_8 low 2. Wait 3 us, then bring MTG_9 low 3. Wait 3 us, then bring MTG_9 high (this clocks a 0 into the LCA configuration trigger register) 4. Wait 3 us, then bring MTG_7 high 5. Wait 3 us, then bring MTG_9 low 6. Wait 3 us, then bring MTG_9 high (this clocks a 1 into the LCA configuration trigger register) 7. Flush any garbage that may have been sent to the DSP's via the CRC. Thisprocedure causes a transition of the LCA configuration trigger register, which triggers LCA configuration. Also, the activity on MTG_9 causes the transmit logic to be reset. The three-microsecond delays are necessary to satisfy the DC's glitch-rejection logic. Control of ERPB Reception of Data From the CTFE's ------------------------------------------------- The following signals are used by the ERPB's to capture data from the CTFE's: INPUT_CLK, TOTAL, STORE\, LATCH\. INPUT_CLK and TOTAL are free-running. INPUT_CLK pulses low for each data word output by the CTFE. I.e., it pulses low during the Total Et word and then again during the Electromagnetic Et word. Future high beam-crossing rates may require careful control of INPUT_CLK timing, but initially all that is required is: CTFE data should be valid some time (e.g., 37 ns) before INPUT_CLK goes low CTFE data should remain valid until some time (e.g., 37 ns) after INPUT_CLK rises INPUT_CLK pulse width (low) should be reasonable (e.g., 75 ns) Within an ERPB LCA, all flip-flop clocks and RAM write enables are derived from INPUT_CLK. I.e., only the edges of INPUT_CLK are intended to cause a flip-flop or RAM location to change state. Thus the signals TOTAL, STORE\, and LATCH\ should not change within 37 ns of INPUT_CLK being low. TOTAL is high when Total Et data are being output by the CTFE and low when EM Et data are being output. STORE\ is used to store data from the CTFE's into the LCA's internal buffer. Though variations are possible, it is simplest for STORE\ to be low for one complete beam crossing. Within the LCA's, STORE\ is gated with TOTAL and INPUT_CLK to perform the following functions: STORE\ = low AND TOTAL = high AND INPUT_CLK = low --> write CTFE data into the Total Et buffer STORE\ = low AND TOTAL = low AND INPUT_CLK = low --> write CTFE data into the EM Et buffer STORE\ = low AND TOTAL = low AND INPUT_CLK rises --> increment the buffer address counter LATCH\ is used to read data from the LCA's internal buffer and place it into the LCA's readout register. Though variations are possible, it is simplest for LATCH\ to be low for one complete beam crossing. Within the LCA's, LATCH\ is gated with TOTAL and INPUT_CLK to generate the clock for the readout register: LATCH\ = low AND TOTAL = low AND INPUT_CLK falls --> clock data from buffer into readout register LATCH\ also controls the address presented to the buffers. When LATCH\ is high, the buffer address equals the buffer counter. When LATCH\ is low, the buffer address equals the buffer counter - N - 1. N is a constant built into the LCA configuration that will increase in the future as beam-crossing rate increases. Since the buffers are not dual-ported, LATCH\ should never be active when STORE\ is active, because the CTFE data would be stored in the wrong location in the buffer. Since currently N is 0, the buffer has only one location, and there is no buffer counter. So LATCH\ has no effect on the buffer output at this time. Official meaning of N: Consecutive beam crossings are numbered 1, 2, 3, ... STORE\ has been active for many beam crossings, and then it goes inactive. Beam crossing j is the last beam crossing for which data were stored. LATCH\ goes active some beam crossing after beam crossing j. This causes data from beam crossing (j-N) to be copied to the readout register. Why there could be confusion about N: the buffer address counter is incremented AFTER each beam crossing for which STORE\ is active. In terms of the buffer address counter, the above meaning of N can be written: STORE\ has been active for many beam crossings, and then it goes inactive. The buffer address counter has value k after the last data are stored. LATCH\ goes active some beam crossing after the last stored beam crossing. This causes data from buffer location (k-1-N) to be copied to the readout register. The official meaning above was adopted for two reasons: 1. It is hardware-independent. 2. It is easy to remember: If N = 0, then a latch following a store latches the data just stored. Warning: in some old versions of the file RECVA_00.tim, 7-N should instead be 7-N-1. Control of Data Transmission to the CRC's ----------------------------------------- Once the desired data are placed in the readout register, the MTG need only signal the DC's to start transmission. This is accomplished by bringing XMIT_TRIG high for about 1 us. The Transmit GAL on the DC conditions XMIT_TRIG to avoid triggering on glitches, so XMIT_TRIG might not be recognized if it is too short (< ~400 ns); it might cause unpredictable operation if it is too long (> ~5 us). Initially Implemented Features ------------------------------ Initial LCA Configurations -------------------------- Three LCA configurations are currently available. Test: The test configuration is used during automated testing. It allows any signal input to any LCA to be output on the ERPB's data bus. See the Burn-in and Test section for details. Burn-in: The burn-in configuration is used during burn-in. It attempts to dissipate power in the LCA's by toggling internal flip-flops at high frequency. The flip-flops are arranged in a giant shift register that extends through all eight LCA's. In LCA #1, the shift register's signal frequency is divided and presented to the ERPB's red LED. The LED flashes at about .5 Hz when a 16 MHz signal is applied to XMIT_CLK. Since the shift register goes through all LCA's, the red LED is an indication that no LCA has suffered a major failure. Run00: The Run00 configuration is used when the ERPB's are operating as part of the L1.5 Trigger System. The configuration must not only receive data from the CTFE's, but also orchestrate its transmission to the DC. The Run00 configuration will most likely be replaced as beam crossing rates increase. New configurations will have deeper buffers and shorter propagation delays. For Run00 details, see the Operation section. Multiple Readout Orders ----------------------- To simplify DSP software development, ERPB's have four different readout orders. Five of the CTFE racks have positive ETA readout and the other five have negative ETA readout. Each rack has one eccentric-readout ERPB, which is cabled in a way different from the other ERPB's. A switch setting on the DC selects positive or negative ETA readout orders. A jumper on each ERPB can be set to indicate normal or eccentric readout orders. There are several different ways to specify ERPB data channels, and thus readout orders: ETA & PHI: ETA and PHI are the detector coordinates of the calorimeter trigger tower connected to the channel Jmn & -p: Jmn specifies the ERPB backplane connector (m = 1 or 3, n = 0, 1, 2, 3). -p specifies the CTFE data channel (p= 1, 2, 3, 4). Xk & -A or -B: Xk specifies the LCA (k = 0-7). -A and -B specify which channel of the LCA. Each of these representations can be useful. The ETA & PHI representation is convenient for DSP software developers and system designers. The J representation is useful during testing and ERPB repair. The X representation is useful when designing an LCA configuration. A spreadsheet was created to translate between the different formats. Shown below is this spreadsheet applied to the current four readout orders. [NOT SHOWN IN ELECTRONIC DOCUMENT] This spreadsheet shows readout orders as derived from the J-to-X Map, ETA-PHI Maps, and the Readout Order Rule. In the Readout Order tables, readout proceeds from the top of the table to the bottom. Nine-bit to Eight-bit Packing ----------------------------- The 9-bit CTFE output words are packed into 8-bit bytes within the LCA. At present, both EM and Total use the same technique: each of CTFE bits 0-7 is OR'd with bit 8 to form the new byte. I.e., if the value of CTFE data exceeds 255, then it is saturated to 255. Data Buffering -------------- CTFE data, after packing, are written into the buffer in the LCA. Currently, the buffer is simply a byte-wide register. (There are four of these buffers: Ch_A EM, Ch_A Total, Ch_B EM, Ch_B Total.) Another set of four registers, the readout registers, is attached to the buffer outputs. Data are moved to the readout registers prior to readout. New CTFE data may be written to the buffer during readout. Future Capabilities ------------------- High-Speed Data Reception ------------------------- As the beam crossing frequency increases, redesign of the LCA configuration will be necessary. Higher beam crossing rates require buffers more complicated than the single register currently implemented. Trigger decisions will be made several beam crossings after the data of interest are stored in the buffers. So the buffers must be deep enough to hold data until a trigger decision is made. CLB's in the XC4002 LCA are ideally suited for implementing buffers, because they can be configured as random access memories. At higher beam crossing rates, propagation delays within an LCA become more critical. They can be minimized by careful layout, utilization of specialized routing resources (e.g., global long lines), etc. Pipelining of CTFE data may be necessary at the fastest beam crossing rates. IOB's contain latches suitable for this purpose. High-Speed Readout ------------------ Readout time is significant compared to DSP algorithm execution time. Readout time can be reduced by changing the way data are transmitted. The DSP serial port architecture constrains the timing of data transmission. One mode of transmission, as initially implemented, is to send four bytes, one every 100 ns. Another method compatible with the 320C40 serial port is to send four bytes every 60 ns, then pause for 60 ns. Initial method: 100ns * 4 = 400 ns Faster method: 60ns * 5 = 300 ns per four bytes The faster method will gradually fill the 320C40's serial port buffers, but data transmission stops before the buffers get full. (The 320C40's DMA controller is draining the serial port buffers as transmission proceeds.) Fault Reporting --------------- Logic and signal paths are provided on the DC and ERPB to allow fault data to be appended to the end of the transmit data stream. During transmission of data to the CRC, shift registers on the DC accumulate fault information from the ERPB's. After all data words have been transmitted, fault words from the shift registers are transmitted. The following signals can be used to transfer fault bits from the ERPB's to the DC: FAULT_CLK - a bussed signal on the parallel cable (same as DST_3) TOK - a daisy-chained signal on the daisy chain cable DFAULT\ - a bussed signal on the daisy chain cable FAULT_CLK is generated on the DC. It is only active during data transmission. TOK is the fault token. DFAULT\ is the fault data bus. During transmission, the DC produces a stream of pulses on FAULT_CLK and activates TOK. An ERPB drives DFAULT\ with fault information when it has received the token. Up to four fault bits for each ERPB can be stored in the DC's fault shift registers. An ERPB eventually passes the token on to the next ERPB in the chain. Any information available to the Fault GAL (U35 on the ERPB) can be used for flagging faults: HDC - use to flag fault if LCA's are not configured PWR_UP\ - use to flag fault if ERPB thinks it is not powered up DDCI_0, etc. - use to flag fault if ERPB was not given the transmit go-ahead when expected GI_0 - use to flag fault based on information from LCA #1 GAL's and PROM's on the DC and ERPB must be reprogrammed to support fault reporting. Run-Time Data Path Diagnostics ------------------------------ Logic and signal paths are provided on the DC and ERPB to allow introduction of diagnostic data into the LCA's. Typically, these data bits would be introduced into the data path in place of CTFE data. Serial loading of data into the LCA's is independent of all other ERPB functions, so diagnostic data can be loaded even as real data are being received and transmitted. The following signals can be used to implement data path diagnostics. All of the signals can be used for other purposes if data path diagnostics are not supported. DIAG_MODE\ (MTG_4) - control signal that selects diagnostic data instead of CTFE data DIAG_CLK (MTG_5) - clock that clocks DIAG_DATA DIAG_DATA (MTG_8) - data being clocked into the LCA during data loading Remote Control of the DC ------------------------ DC Setup -------- If the eighth switch of the ID/MODE DIP switch (SW1 on the DC) is in the up position, the SETUP DIP switch is ignored and DC setup is controlled by the MTG. During remote DC setup, signals MTG_0 - MTG_7 are used as a data bus. MTG_8 selects either the MAIN MTG register or an ALT MTG register. There are two ALT MTG registers; the ALT_REG bit of the MAIN MTG register determines which ALT register is written. MTG_9 strobes data into the MTG registers. The MAIN MTG registers of all DC's are written simultaneously, but ALT MTG registers will only be written if DIST_S_0 - DIST_S_3 (in the MAIN MTG register) matches the ERPB's ID number on the ID/MODE DIP switch. (1111 matches all ID numbers). For more DC setup details, see the Setup Logic schematic (DSET.sch). The MTG setup capability should only be used during the initialization of the system (activity on MTG_9 disables data transmission). LCA Configuration ----------------- The LCA configuration bitstream and control signals can come from the MTG instead of from an SCP on the DC. The signals MTG_DIN, MTG_CCLK, and RACK_CONF in ALT MTG register 1 are used to perform the configuration. Each rack can receive a different configuration. See above and consult the Setup Logic schematic (DSET.sch) for more information. Long-Term Hardware Support -------------------------- Spares ------ Fully assembled and tested spare ERPB's and DC's are maintained at FNAL. Spare parts, bare boards, and a few fully assembled prototype ERPB's and DC's are held at UCI. LCA Configuration ----------------- Configuration of Xilinx LCA's (specifically, the XC4002APC84C-5) requires XACT software from Xilinx. The initial LCA configurations were designed on a Sun SPARCstation 10 using Xilinx XACT Design Editor Software version 4.31. No schematic capture tools were used, because at present the automatic place-and- route tools cannot take full advantage of some features of the XC4002. Also, it is likely that a design for the ultimate 132 ns beam-crossing rate will require hand placement. Current designs are contained in text files that are executed by XDE directly. A copy of these files is appended to this document. To create the LCA configuration from these text files, run XDE and select the proper part, package, and speed. Then type 'e' (editlca). This runs the LCA editor itself. Then type 'exec all.x'. This will execute all of the commands in all of the text files. Save the result. The Xilinx programs 'makebits' and 'makeprom' are used to translate the XDE file format into an Intel MCS86 format file suitable for burning the SCP. The script file 'make_prom' (also in the appendix) will run 'makebits' and 'makeprom'. Scheduling ---------- UCI became involved with the design of the ERPB in July of 1993. An ambitious delivery date of December 8 was eventually scheduled for the first eight ERPB's. In a meeting on August 5, attendees agreed that the addition of a new type of card, the DC, would simplify the ERPB and solve several minor problems. Many factors caused the schedule to slip, and the first eight fully-tested ERPB's were actually delivered to MSU on February 18, 1994. The first DC was shipped to MSU on March 8. Schedules for other parts of the system also slipped, so deliveries from UCI (some via UMD, which tested the ERPB's) fit in well with overall system installation. Item Anticipated Actual ---- ----------- ------ DC added to project Aug 08 2500 production ECL-TTL translators ordered Sep 14 first ERPB prototype parts order placed Sep 22 Sep 15 PCB CAD software purchased Sep 20 ERPB layout completed Sep 29 Nov 02 780 production LCA's ordered Nov 08 5 prototype ERPB PCB's ordered Sep 29 Nov 11 final production parts order placed Oct 27 Nov 22 ERPB with connectors shipped to MSU for Nov 03 Dec 01 mechanical checks fully assembled ERPB shipped to MSU for tests Nov 03 Dec 08 100 production ERPB PCB's ordered Nov 03 Dec 13 first DC production parts order placed Dec 15 production ERPB assembly order placed w/GWT Nov 17 Jan 07 10 assembled ERPB's delivered to UCI by GWT Jan 18 9 assembled ERPB's shipped to UMD for Dec 01 Jan 20 burn-in and test 85 assembled ERPB's delivered to UCI by GWT Jan 28 25 assembled ERPB's shipped to UMD for Feb 02 burn-in and test 20 assembled ERPB's shipped to UMD for Feb 08 burn-in and test 5 prototype DC PCB's ordered Feb 11 First fully-tested production ERPB's Dec 08 Feb 18 arrive at MSU 24 assembled ERPB's shipped to UMD for Feb 18 burn-in and test 16 assembled ERPB's shipped to UMD for Feb 23 burn-in and test assembled prototype DC shipped to MSU Mar 08 15 production DC PCB's ordered Mar 11 final ERPB shipment from UMD arrives at MSU Dec 22 Mar 18 production DC soldering order placed Apr 07 7 fully-tested production DC's shipped to MSU May 03 6 fully-tested production DC's shipped to MSU May 09 Project documentation and file archiving completed Jun 01 The original schedule was not met due to several factors: The time required to design and lay out the ERPB was underestimated. Purchasing time increased due to a semiconductor shortage. The shortage also contributed to design delays, since designing could not proceed until parts availability was confirmed. The time required to evaluate prototypes was underestimated. The winter holidays affected suppliers and contractors, setting back ERPB assembly by several weeks. The time to design, lay out, and test the DC was not considered in the original schedule. The DC also became more sophisticated than originally envisioned. Delays with other aspects of the trigger upgrade made more time available. UCI took advantage of this time to add more hardware features, perform more careful assembly and testing, etc. The time to document the project was not considered in the original schedule. Funding -------- This project was funded by the U.S. Department of Energy through an FNAL subcontract. Until the subcontract was signed, work proceeded under a memorandum of understanding dated August 10, 1993. Subcontract: B59920, dated November 8, 1993. Total value: $118,000. Official delivery date: 08-31-94 UCI account and fund number: 485870-59912 Expenditure Highlights ---------------------- Item Anticipated Actual ---- ----------- ------ Components XC4002A-5PC84C (LCA) $30,240 $27,300 TTL/ECL translators for ERPB $6,885 $11,170 ECL components for DC $2,501 ERPB production bare boards $16,750 $10,130 DC production bare boards $2,700 $2,430 ERPB prototypes $3,203 DC prototypes $2,475 ERPB assembly $7,750 $6,903 Engineering software $2,500 $5,480 Summary Material $83,000 $91,733 Personnel $35,000 $26,267 Total $118,000 $118,000 All values are approximate. Only the summary values are meant to be self-consistent and complete. Despite padding and overestimation of material costs, the actual material costs exceeded anticipated by about 10 percent. Some factors that contributed to this: Prototype costs were not anticipated. No allowance was made for required excess production components. E.g., if 90 production ERPB's are required, parts for 100 must be purchased to allow for lost or damaged parts, etc. The final DC was substantially more sophisticated than originally envisioned. Software costs were higher than anticipated. What is not apparent from the above figures is that personnel cost estimates were also unrealistic. Though the project remained within budget, it did so only because personnel costs were highly subsidized by other DOE research funds. A rough estimate of true personnel costs for the project is $65,000. Manufacture ----------- ERPB ---- ERPB PCB's were manufactured by Cartel Electronics of Placentia, California. The boards have six copper layers. The internal copper layers are: 2 - GND 3 - VCC (+5V ) 4 - VEE ( - 5V ) 5 - GND Serial Numbers: Prototype PCB's: S/N P1-P5 (bare boards were not electrically tested). Production PCB's: S/N 1-96, plus four boards without S/N's (bare boards were electrically tested). Only S/N 1-95 were fully assembled. Production ERPB's were assembled by Golden West Technology of Fullerton, California. A stainless steel stencil was used for application of solder paste. Nearly all components were placed by automated equipment. Surface-mount soldering used an infrared reflow process. Most through-hole components were wave soldered. The exceptions (JP1, J10, J20, J30) could not be wave soldered, because the boards were gripped by the edges during wave soldering. All fluxes were water based. Final washing was in water. DC -- DC PCB's were manufactured by Cartel Electronics of Placentia, California. The boards have six copper layers. The internal copper layers are: 2 - GND 3 - VCC (+5V ) 4 - VEE ( - 5V ) 5 - VTT ( termination voltage, -5V) Serial Numbers: Prototype PCB's: S/N P1-P5 (bare boards were not electrically tested). Production PCB's: S/N 1-15, plus four boards without S/N's (bare boards were electrically tested). Only S/N 1-13 were fully assembled. The DC photoplots contain four terminator boards in addition to the DC; for each DC PCB manufactured, four terminator PCB's were manufactured. The terminator PCB's can be assembled with a variety of connectors, allowing termination of ribbon cables of various widths. Production DC's had parts stuffed by hand at UCI. One component, U22, was surface mounted, so it was fully soldered at UCI. Solder mask was applied to footprints of J1, J2, JP1, JT1, and all SPARE's. All parts except J1, J2, JP1, JT1 were wave soldered at QTA of Irvine, California. Those parts not wave soldered were hand soldered by QTA after removal of solder mask. The solder mask and all fluxes were water based. Final washing was in water. Burn-in and Test ---------------- All production ERPB and DC bare PCB's were electrically tested by the manufacturer. All were visually inspected after assembly. DC -- Production DC's (S/N 1-13) were processed as follows: Preliminary tests: -5V supply current (typically 1.6A +/- .1A) +5V supply current (typically 1.6A +/- .1A) LCA configuration Burn-in: 160 hours at room temperature, nominal supply voltage (+5V, -5V), no signals applied Final Tests: -5V supply current +5V supply current LCA configuration transmit trigger transmit sequencer bits transmit connector stb transmit connector data daisy chain data daisy chain handshake daisy chain power sense transmit disable on MTG_9 MTG_0-8 -> parallel cable DST 0, 2, 4, 5, 6 DC-to-DC connections GLOB_CONF backplane connectors: power backplane connectors: shorts These tests were performed manually using signal sources, an oscilloscope, etc. ERPB ---- ERPB S/N 4 was rejected due to mechanical, perhaps only cosmetic, damage. It remains at UCI. ERPB's S/N 1 through 93, excluding 4, were processed at UMD as follows: Initial test: Automated test as described below. Burn-in: 100 hours minimum at room temperature or above, nominal supply voltage (+5V, -5V), XMIT_CLK =16 MHz, LCA's loaded with burn-in configuration. Final Test: Automated test as described below. ERPB Automated Test ------------------- UMD designed and constructed a test apparatus specifically for ERPB testing. Almost every input and output of the ERPB can be tested. A special LCA configuration is used during the test. Each LCA acts as a tri-state 16-bit x 3 multiplexer. The 48 inputs to the multiplexer are connected to virtually every LCA input pin. The multiplexer outputs from all 8 LCA's are connected to the ERPB's main data bus. The LCA that is driving the bus is selected by MTG_0-MTG_2. I.e., when MTG_0-MTG_2 equals LCA_0-LCA_2, the output of the mux is enabled onto the ERPB data bus. The mux address signals are MTG_3 (LSB) and MTG_4 (MSB). The test LCA configuration also directly connects DIAG_I to DIAG_0, allowing testing of the signal chain that proceeds from X7 to X6 ... to X0. See the CTFE Connectors and LCA's schematic (CON_LCA.sch). Table of Test Configuration Multiplexer Inputs ---------------------------------------------- 0 0 0 1 1 x <-- mux address (MTG_4 MTG_3) XDATA_0: A0 B7 GO_0 . A1 B8 GO_1 . A2 MTG_8 GO_2 . A3 MTG_7 GO_3 . A4 MTG_6 DIAG_I . A5 MTG_5 JMP_0 . A6 MTG_4 JMP_1 XDATA_7: A7 MTG_3 LCA_0 XDATA_8: A8 MTG_2 LCA_1 . B0 MTG_1 LCA_2 . B1 MTG_0 0 . B2 DST_0 0 . B3 DST_1 0 . B4 DST_2 0 . B5 DST_3 0 XDATA_15: B6 DST_6 M0 A0-A7, B0-B7 = data from CTFE's. MTG... = Master Timing Generator signals (via JP1 and the distributor). DST... = signals generated by the distributor (via JP1). GO... = transmit GAL outputs. See the Daisy Chain Cable schematic (DAISY.sch). DIAG_I = diagnostic data input. JMP... = on-board jumpers (from H1). LCA... = the hard-wired LCA number (e.g., X0 has these signals all tied low). M0 = one of the LCA's configuration mode bits (pulled high). XDATA_... = ERPB's main data bus The test apparatus is driven by a commercial digital i/o card connected to a PC- compatible's parallel port. So the test exercises most signals, but does so at relatively low speeds. At least one ERPB that survived UMD burn-in and tests showed intermittent behavior when installed in the system. The UMD tests do not use the actual LCA configuration that will be loaded during a D0 run. UCI developed software to test the ERPB with the 'run' LCA configuration, but found that the digital i/o card and its drivers severely limited the speed at which tests could be performed. The software is flexible and could be used to run a variety of tests with a variety of hardware. The C source code is available in file utest.zip. Modifications ------------- XMIT_STB generation on DC ------------------------- The CRC is dependent on the timing of both edges of XMIT_STB. The initial design of the DC forced XMIT_STB to be high for the same amount of time as XMIT_CLK was high. In order to safely meet CRC timing criteria, a narrower XMIT_STB width was required. All prototype and production DC's were modified by cutting one trace and adding two jumpers. These modifications appear on the DC Transmit Logic schematic (DXLOG.sch). GAL4 was reprogrammed. XMIT_STB is now forced low when XMIT_CLK goes low. The delay (selectable with the jumper on H2) now delays only the rising edge of XMIT_STB. XMIT_CLK ___/~~~~~~~\_______/~~~~ (on DC only) XMIT_DATA ====X===============X=== (on DC-to-CRC cable) XMIT_STB ________/~~\__________ (on DC-to-CRC cable) -->| |<-- delay adjustable via H2 Appendices ---------- Acronyms and Terminology ------------------------ Acronyms and terminology as used in this document: 320C40 - The type of DSP initially used for the L1.5 Trigger Upgrade. The 320C40 is manufactured by Texas Instruments. CLB - Configurable Logic Block. An LCA contains many CLB's, each of which can be configured to perform a desired logic function. CLB's contain latches, logic, etc. In the XC4000 series, CLB's can be configured as random access memories. The XC4002A, used for the ERPB's, contains 64 CLB's in an 8x8 matrix. Configuration - The process by which an LCA is loaded with the bitstream that defines its function. The function itself is also called a configuration. Configuration Board - A small hand-wired circuit board containing logic capable of configuring the LCA's on an ERPB. It generates a 16 MHz XMIT_CLK for use during ERPB burn-in. The board connects to the ERPB through the parallel connector, JP1. Two such boards were built by UMD. CRC - Cable Receiver Card. The card that receives data transmitted from the DC's. It sends the data on to the DSP's. CTFE - Calorimeter Trigger Front End. A type of circuit card in the D0 Calorimeter Trigger. ERPB's receive data from CTFE cards. Daisy Chain - A cabling scheme in which a separate cable is connected between each device and the next device in the chain. ERPB's transmit data to the DC over a daisy chain cable. The ERPB/DC daisy chain cable has a few parallel (bussed) signals. DC - Distributor Card (formerly DIST). DOE - United States Department of Energy. DSP - Digital Signal Processor. EM - Electromagnetic Et data as output by the CTFE. EM also refers to the packed version of the CTFE Electromagnetic Et data as output by the ERPB. ERPB - Energy Readout Paddle Board. Et - Transverse Energy. FNAL - Fermi National Accelerator Lab, Batavia Illinois, USA. FPGA - Field Programmable Gate Array. A type of re-configurable logic device. GAL - Generic Array Logic. A trademark for a family of programmable logic devices from Lattice Semiconductor Corporation. A single type of GAL can be used as a pin-compatible substitute for many types of programmable logic devices (e.g., a GAL16V8 can emulate a 16R8, 16P8, etc.) GWT - Golden West Technology. The company that assembled the ERPB's. IOB - Input Output Block. An LCA contains an IOB on most of its I/O pins. In the XC4000 series, IOB's can be configured as inputs, outputs, i/o's, latched inputs, latched outputs, etc. LCA - Logic Cell Array. A trademark for a family of RAM-based field programmable gate arrays from Xilinx Corporation. LED - Light Emitting Diode. Master DC - The DC whose configuration information and XMIT_CLK are used by all DC's. DC-to-DC cabling is required to use a master DC. Only the master DC need have an SCP installed. If there is no cabling, each DC must have its own SCP in order to configure the LCA's in its rack. Use of remote (i.e., master DC) configuration information and XMIT_CLK can be overridden through DIP switch settings. Master Timing Generator - A type of card that generates timing signals used throughout the calorimeter trigger. One MTG is programmed to generate the signals that control the operation of the ERPB and DC. All DC's in the system receive the same ten MTG signals, MTG_0 - MTG_9. Each DC buffers MTG_0 - MTG_8 and sends the resulting signals to its ERPB's. MSU - Michigan State University. MTG - Master Timing Generator. Pack - to convert 9-bit CTFE data to the 8-bit data required for ERPB output. Parallel - A cabling scheme in which a single cable is connected to several devices. Each device on the cable sees the same signals. The DC sends MTG and other timing signals to its ERPB's via a parallel cable. PCB - Printed Circuit Board. PROM - Programmable Read Only Memory. Read out - to send data from the ERPB's to the CRC's. Same as transmit. SCP - Serial Configuration PROM. A PROM containing LCA configuration information. An SCP outputs its contents as a serial bitstream. Setup - Setup refers to the operating modes of the DC as determined by the SETUP DIP switch (SW2) on the DC. Setup options are printed on the DC silkscreen. Terminator Board - A small circuit board that connects to the end of a ribbon cable. The board contains resistors that terminate the differential ECL signals on the ribbon cable. The boards are used to terminate the MTG cable and the Parallel cable. The PCB's were manufactured as part of the DC PCB, but were separated at the final stage of manufacture. See the DC PCB silkscreen. Total - Total Et data as output by the CTFE. Total = Hadronic + Electromagnetic. Total also refers to the packed version of the CTFE Total Et data as output by the ERPB. Translation - The converting of a signal from one level standard (e.g., TTL) to another (e.g., ECL). Transmit - to send data from the ERPB's to the CRC's. Same as readout. UCI - University of California, Irvine. UMD - University of Maryland. XACT - Xilinx Automatic CAE Tools. The set of software tools used for developing LCA designs. XDE - XACT Design Editor. The program used to enter, edit, and analyze an LCA design. Computer Files -------------- This document was created using Microsoft Word version 2.0c. PC-based CAD tools: Schematics were created with OrCAD Schematic Design Tools 386+ version 1.10A. PCB Layouts were designed with OrCAD PC Board Layout Tools 386+ version 1.00. GAL designs were created with OrCAD Programmable Logic Design Tools 386+ version 1.10. Sun SPARCstation-based CAD tools: LCA configurations were designed with Xilinx XACT Design Editor Software version 4.31. This document: ERPB_DC.doc Microsoft Word format ERPB_DC.txt ASCII text format Timing diagram text files: TIMING.zip compressed timing diagram text files CAD files: LIB.zip compressed schematic and layout libraries (OrCAD) ERPB.zip compressed ERPB schematics and layout (OrCAD) DC.zip compressed DC schematics and layout (OrCAD) ERPB_GBR.zip compressed ERPB Gerber photoplot text files DC_GBR.zip compressed DC Gerber photoplot text files GAL.zip compressed GAL and PROM text files PROG.zip compressed GAL, PROM, SCP device programmer text files (e.g.,JEDEC) LCA_TEST.zip compressed Test LCA execute (text) files LCA_BURN.zip compressed Burn LCA execute (text) files LCA_RUN.zip compressed Run LCA execute (text) files Miscellaneous: READOUT.xls readout order spreadsheet (Microsoft Excel) utest.zip compressed C source files for ERPB test software developed at UCI Program files (run under DOS): HPWAVE.exe Timing diagram translation program SEQ.exe Sequencer PROM translation program PKUNZIP.exe decompression program For copies of any of the above files, contact pier@nucleus.ps.uci.edu or root@nucleus.ps.uci.edu. Bills of Materials ------------------- ERPB ---- Energy Readout Paddle Board Revised: October 14, 1993 ERPB.sch Revision: Bill Of Materials October 26, 1993 10:01:39 Page 1 Item Quantity Reference Part ORDER NUMBER DESCRIPT ________________________________________________________________________________ 1 98 CD1,CD2,CD3,CD4,CD5,CD6, CDC TBD .1 uF, X CD7,CD8,CD9,CD10,CD11, CD12,CD13,CD14,CD15,CD16, CD17,CD18,CD19,CD20,CD21, CD22,CD23,CD24,CD25,CD26, CD27,CD28,CD29,CD30,CD31, CD32,CD33,CD34,CD35,CD36, CD37,CD38,CD39,CD40,CD41, CD42,CD43,CD44,CD45,CD46, CD47,CD48,CD49,CD50,CD51, CD52,CD53,CD54,CD55,CD56, CD57,CD58,CD59,CD60,CD61, CD62,CD63,CD64,CD65,CD66, CD67,CD68,CD69,CD70,CD71, CD72,CD73,CD74,CD75,CD76, CD77,CD78,CD79,CD80,CD81, CD82,CD83,CD84,CD85,CD86, CD87,CD88,CD89,CD90,CD91, CD92,CD93,CD94,CD95,CD96, CD97,CD98 2 1 LED1 LED_R TBD red LED 3 1 LED2 LED_Y TBD yellow L 4 1 LED3 LED_G TBD green LE 5 1 JP1 CON40RP TBD 40-pin r 6 3 J11,J12,J13 CON40U TBD 40-pin s 7 3 J31,J32,J33 CON40P TBD 40-pin s 8 2 JA1,JB1 CON50P TBD 50-pin s 9 3 J10,J20,J30 DIN96 TBD 96-pin r 10 15 R1,R2,R3,R4,R5,R6,R7,R8, R2.2K TBD 2.2K, 1/ R9,R10,R11,R12,R15,R17, R18 11 3 R13,R14,R16 R270 TBD 270, 1/8 12 1 S2 SPARE16 NONE spare SO 13 1 S1 SPARE20 NONE spare SO 14 12 TD1,TD2,TD3,TD4,TD5,TD6, TDC TBD 10 uF, t TD7,TD8,TD9,TD10,TD11, TD12 15 27 U1,U2,U3,U4,U5,U6,U7,U8, 100325QC 100325QC National U9,U10,U11,U12,U13,U14, U15,U16,U17,U18,U19,U20, U21,U22,U23,U24,U25,U26, U27 16 1 U36 74AC00 TBD quad NAN 17 1 U28 74AC541 TBD octal no 18 3 U29,U30,U31 74ACT541 TBD octal no 19 2 U32,U33 74AC574 TBD octal re 20 1 U34 GAL22V10 GAL22V10B-7LP Lattice 21 1 U35 GAL16V8 GAL16V8A-15LP Lattice 22 1 U37 RPACK13 766-141-R5.1K CTS resi 23 8 X1,X2,X3,X4,X5,X6,X7,X0 ERPB_LCA XC4002A-5PC84C Xilinx L 24 2 D1,D2 D_SOT TBD diode in 25 1 Q1 NPN_SOT TBD NPN tran 26 1 H1 HEADER 3X2 TBD 3x2 stra 27 1 H2 HEADER 3 NONE test poi DC -- Distributor Card Revised: January 30, 1994 DIST.sch Revision: Bill Of Materials February 13, 1994 8:56:15 Page 1 Item Quantity Reference Part ORDER NUMBER DESCRIPT ________________________________________________________________________________ 1 53 CD1,CD2,CD3,CD4,CD5,CD6, CDC TBD .1 uF, X CD7,CD8,CD9,CD10,CD11, CD12,CD13,CD14,CD15,CD16, CD17,CD18,CD19,CD20,CD21, CD22,CD23,CD24,CD25,CD26, CD27,CD28,CD29,CD30,CD31, CD32,CD33,CD34,CD35,CD36, CD37,CD38,CD39,CD40,CD41, CD42,CD43,CD44,CD45,CD46, CD47,CD48,CD49,CD50,CD51, CD52,CD53 2 1 LED1 LED_R TBD red LED 3 1 LED2 LED_G TBD green LE 4 1 JP1 CON40RP TBD 40-pin r 5 2 JT1,JX1 CON40P TBD 40-pin s 6 1 JB1 CON50P TBD 50-pin s 7 2 J1,J2 DIN96 TBD 96-pin r 8 3 R2,R11,R12 R270 TBD 270, 1/8 9 2 S2,S4 SPARE16 NONE spare SO 10 2 S1,S3 SPARE20 NONE spare SO 11 13 TD1,TD2,TD3,TD4,TD5,TD6, TDC TBD 10 uF, t TD7,TD8,TD9,TD10,TD11, TD12,TD13 12 2 U1,U2 100314DC TBD 13 7 U15,U36,U37,U38,U39,U41, 100324DC TBD U42 14 4 U3,U4,U14,U40 100325DC TBD 15 1 U22 74AC00 TBD quad NAN 16 2 U19,U34 74ACT541 TBD octal no 17 2 U20,U21 74AC574 TBD octal re 18 3 GAL2,GAL3,GAL4 GAL22V10 GAL22V10B-7LP Lattice 19 1 GAL1 GAL16V8 GAL16V8A-15LP Lattice 20 1 H1 HEADER 3 NONE test poi 21 2 C1,C2 10 uF TBD 22 1 C3 4.7 uF TBD 23 1 C4 .1 uF TBD 24 1 H3 HEADER 6X2 TBD 25 1 H4 HEADER 6 TBD 26 2 JD1,JD2 CON20P TBD 27 1 JM1 CON34P TBD 28 1 H2 HEADER 9X2 TBD 29 3 Q1,Q2,Q3 3906 TBD PNP tran 30 8 R1,R3,R4,R5,R6,R7,R8,R9 R10K TBD 31 1 R10 R1K TBD 32 2 SCP1,SCP2 SCP TBD socket o 33 2 U5,U6 PULLUP13 TBD resistor 34 4 U30,U31,U32,U33 74ACT299 TBD 35 1 U9 74HCT85 TBD 36 3 U7,U8,U35 74HCT157 TBD 37 2 U13,U18 74HCT123 TBD 38 5 U16,U17,U25,U28,U29 74F163 TBD 39 5 U10,U11,U12,U24,U27 74F574 TBD 40 2 U23,U26 7C291 TBD Cypress 41 1 X1 OSC_8MHZ TBD 8 MHz o 42 1 X2 OSC_20MHz TBD 20 MHz o 43 2 SW1,SW2 DIPSW_8 TBD 16-pin D 44 1 SW3 PUSHBUTTON TBD normally 45 2 RT2,RT1 RTERM7 TBD resistor 46 9 RL1,RL2,RL3,RL4,RL5,RL6, RLOAD13 TBD resistor RL7,RL8,RL9 Configuration Board ------------------- ERPB LCA Configuration Board Revised: November 17, 1993 CONF.sch Revision: Bill Of Materials November 17, 1993 10:36:23 Page 1 Item Quantity Reference Part ORDER NUMBER DESCRIPT ________________________________________________________________________________ 1 7 CD1,CD2,CD3,CD4,CD5,CD6, CDC TBD .1 uF, X CD7 2 2 TD1,TD2 TDC TBD 10 uF, t 3 1 U4 GAL16V8 GAL16V8A-15LP Lattice 4 3 C1,C2,C3 4.7 uF TBD 4.7 uF c 5 1 H1 PWR CONN TBD standard 6 1 JP1 Header TBD 3-post u 7 1 J1 CON40A TBD 40-pin p 8 2 R1,R2 30K TBD 30K resi 9 1 R3 15K TBD 15K resi 10 1 S1 Pushbutton TBD pushbutt 11 1 U1 74HCT221 TBD dual one 12 1 U2 RPACK15 TBD resistor 13 1 U3 MC10H124 TBD TTL/MECL 14 1 U5 74ALS163 TBD 4-bit sy 15 1 U6 SCP TBD serial c 16 1 U7 OSC TBD crystal LCA Configuration Text Files ---------------------------- Test Configuration ------------------ file etest_2.txt (all .x files for the ERPB test configuration): ----------------------------------------------------------- File ALL.x ----------------------------------------------------------- ;This file is used to create the ERPB test LCA ;Select LCA type XC4002PC84, then go to EDIT_LCA ;In EDIT_LCA, type exec all.x execute blk_name.x ;name blocks (clb's, iob's, buffers) execute nets.x ;route input nets execute blk_conf.x ;configure some blocks execute blk_copy.x ;copy to all other configured blocks endfile em = electromagnetic energy to = tot = total energy blk_name.x names blocks (clb's, iob's, buffers) nets.x adds and routes all nets ----------------------------------------------------------- File BLK_CONF.x ----------------------------------------------------------- ; Block Configuration File Generated by blocks.c ; Source File: blks.xrp editblk COMPARE config F4:F4I G2:G2I G3:G3I X:H Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3:F4 G:G2:G3 H:F:G H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = (F1@F2)+(F3@F4) equate G = G2@G3 equate H = ~(F+G) endblk editblk DELAY config F4: G2: G3: X:H Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1 G:G1 H:F H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1 equate G = G1 equate H = F endblk p 32 editblk GEN_DC config F4: G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F: G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = 0 endblk editblk GEN_OE config F4: G2:G2I G3: X:H Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1 G:G1:G2 H:F H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1 equate G = ~(G1*G2) equate H = F endblk editblk MXF_00 config F4:F4I G2: G3:G3I X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4 G:G1:G3:G4 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = (F1*F4)+(~F1*F3) equate G = (G1*G4)+(~G1*G3) endblk editblk MXP_00 config F4: G2:G2I G3:G3I X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3 G:G1:G2:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = (F1*F3)+(~F1*F2) equate G = (G1*G3)+(~G1*G2) endblk editblk A0 config INFF: I1:I I2: O: OUT: PAD: TRI: RDBK: OSPEED:SLOW endblk editblk HDC config INFF: I1: I2: O: OUT: PAD:PULLDOWN TRI: RDBK: OSPEED:SLOW endblk editblk SO config INFF: I1: I2: O: OUT:O PAD: TRI: RDBK: OSPEED:SLOW endblk editblk T0 config INFF: I1: I2: O: OUT:O PAD: TRI:T RDBK: OSPEED:SLOW endblk ----------------------------------------------------------- File BLK_COPY.x ----------------------------------------------------------- ; This file copies configured blocks to unconfigured blocks that should ; have the same configuration. ;COMPARE ;DELAY p 33 ;GEN_DC ;GEN_OE cb MXF_00 MXF_02 MXF_04 MXF_06 MXF_08 MXF_10 MXF_12 MXF_14 cb MXP_00 MXP_02 MXP_04 MXP_06 MXP_08 MXP_10 MXP_12 MXP_14 ;input pins cb A0 A1 A2 A3 A4 A5 A6 A7 A8 ;Channel A from CTFE cb A0 B0 B1 B2 B3 B4 B5 B6 B7 B8 ;Channel B from CTFE cb A0 M0 M1 M2 M3 M4 M5 M6 M7 M8 ;MTG 0-8 cb A0 D0 D1 D2 D3 D6 ;DST 0-3, 6 cb A0 O0 O1 O2 O3 ;GO 0-3 outputs from GAL cb A0 SI ;serial input (diag) cb A0 I0 I3 I4 I5 I6 ;GI 0,3-6 inputs to GAL ;In operation, GI 0... are outputs for LCA#1 only. ;In this test, they are inputs for all LCA's. ;tristate output pins cb T0 T1 T2 T3 T4 T5 T6 T7 cb T0 E0 E1 E2 E3 E4 E5 E6 E7 ;;;;outputs ;nb p41 SO ;diagnostics serial data out = "INIT*" ;nb p77 I0 ;GI 0-6 ;nb TDO I1 ;"TDO" (output only) tdo.o is controlled by tdo.t ;nb p72 I2 ;"DOUT" ;nb p70 I3 ;nb p69 I4 ;nb p68 I5 ;nb p67 I6 ----------------------------------------------------------- File BLK_NAME.x ----------------------------------------------------------- ;This file names blocks. nb clb_r1c2 MXF_14 nb clb_r2c2 MXF_12 nb clb_r3c2 MXF_10 nb clb_r4c2 MXF_08 nb clb_r5c2 MXF_06 nb clb_r6c2 MXF_04 nb clb_r7c2 MXF_02 nb clb_r8c2 MXF_00 nb clb_r1c5 MXP_14 nb clb_r2c5 MXP_12 nb clb_r3c5 MXP_10 nb clb_r4c5 MXP_08 nb clb_r5c5 MXP_06 nb clb_r6c5 MXP_04 nb clb_r7c5 MXP_02 nb clb_r8c5 MXP_00 p 34 nb clb_r2c8 COMPARE ;compares LCA0-2 w/ MTG0-2 nb clb_r8c8 DELAY ;provides delay for OE* generation nb clb_r1c7 GEN_OE ;generates OE* nb clb_r1c3 GEN_DC ;generates a DC level of 0 nb p9 E7 ;electromagnetic energy ouputs nb p14 E6 nb p15 E5 nb p16 E4 nb p17 E3 nb p18 E2 nb p19 E1 nb p20 E0 nb p23 T7 ;total energy ouputs nb p24 T6 nb p25 T5 nb p26 T4 nb p27 T3 nb p37 T2 nb p28 T1 nb p29 T0 nb p38 A0 ;channel A data inputs nb p39 A1 nb p40 A2 nb p44 A3 nb p45 A4 nb p46 A5 nb p47 A6 nb p48 A7 nb p49 A8 nb p50 B0 ;channel B data inputs nb p56 B1 nb p58 B2 nb p59 B3 nb p60 B4 nb p61 B5 nb p62 B6 nb p65 B7 nb p66 B8 nb p13 M0 ;MTG 0-8 nb p35 M1 nb p10 M2 nb p80 M3 nb p51 M4 nb p78 M5 nb p3 M6 nb p4 M7 nb p5 M8 nb p57 D0 ;DST 0-6 nb p6 D1 p 35 nb p7 D2 nb p8 D3 ;nb p13 D4 ;"PROG*" ;nb p13 D5 ;"CCLK" nb p71 D6 ;"DIN" nb p79 SI ;diagnostics serial data in nb p41 SO ;diagnostics serial data out = "INIT*" nb p77 I0 ;GI 0-6 nb TDO I1 ;"TDO" (output only) tdo.o is controlled by tdo.t nb p72 I2 ;"DOUT" nb p70 I3 nb p69 I4 nb p68 I5 nb p67 I6 nb p81 O0 ;GO 0-3 nb p82 O1 nb p83 O2 nb p84 O3 nb p36 HDC ;HDC = High During Configuration (pulldown after configuration) ;also available: md0.i ("M0"), md1.o ("M1"), md2.i ("M2") ;md1 and md0 are connected off-chip, md2 is tied to VCC ;md1.o is controlled by md1.t ----------------------------------------------------------- File NETS.x ----------------------------------------------------------- ;This file routes nets. ; these are mux address inputs ;mux_a0, mux_a1 = MTG_3, MTG_4 ;MTG 3,4 = mux address lines an mux_a0 M3.i1 MXP_14.f1 MXP_14.g1 ap mux_a0 MXP_12.f1 MXP_12.g1 ap mux_a0 MXP_10.f1 MXP_10.g1 ap mux_a0 MXP_08.f1 MXP_08.g1 ap mux_a0 MXP_06.f1 MXP_06.g1 ap mux_a0 MXP_04.f1 MXP_04.g1 ap mux_a0 MXP_02.f1 MXP_02.g1 ap mux_a0 MXP_00.f1 MXP_00.g1 an mux_a1 M4.i1 MXF_14.f1 MXF_14.g1 ap mux_a1 MXF_12.f1 MXF_12.g1 ap mux_a1 MXF_10.f1 MXF_10.g1 ap mux_a1 MXF_08.f1 MXF_08.g1 ap mux_a1 MXF_06.f1 MXF_06.g1 ap mux_a1 MXF_04.f1 MXF_04.g1 ap mux_a1 MXF_02.f1 MXF_02.g1 ap mux_a1 MXF_00.f1 MXF_00.g1 p 36 an final_oe GEN_OE.y E7.t E6.t E5.t E4.t E3.t E2.t E1.t E0.t ap final_oe T7.t T6.t T5.t T4.t T3.t T2.t T1.t T0.t ;intermediate mux nets an int_15 MXP_14.y MXF_14.g3 an int_14 MXP_14.x MXF_14.f3 an int_13 MXP_12.y MXF_12.g3 an int_12 MXP_12.x MXF_12.f3 an int_11 MXP_10.y MXF_10.g3 an int_10 MXP_10.x MXF_10.f3 an int_09 MXP_08.y MXF_08.g3 an int_08 MXP_08.x MXF_08.f3 an int_07 MXP_06.y MXF_06.g3 an int_06 MXP_06.x MXF_06.f3 an int_05 MXP_04.y MXF_04.g3 an int_04 MXP_04.x MXF_04.f3 an int_03 MXP_02.y MXF_02.g3 an int_02 MXP_02.x MXF_02.f3 an int_01 MXP_00.y MXF_00.g3 an int_00 MXP_00.x MXF_00.f3 an mxo_15 MXF_14.y E7.o ;mux outputs to IOB's an mxo_14 MXF_14.x E6.o an mxo_13 MXF_12.y E5.o an mxo_12 MXF_12.x E4.o an mxo_11 MXF_10.y E3.o an mxo_10 MXF_10.x E2.o an mxo_09 MXF_08.y E1.o an mxo_08 MXF_08.x E0.o an mxo_07 MXF_06.y T7.o an mxo_06 MXF_06.x T6.o an mxo_05 MXF_04.y T5.o an mxo_04 MXF_04.x T4.o an mxo_03 MXF_02.y T3.o an mxo_02 MXF_02.x T2.o an mxo_01 MXF_00.y T1.o an mxo_00 MXF_00.x T0.o ;these inputs are selected if mux address = 00 an i_00_0 MXP_00.f2 A0.i1 ;LSB (output on XDATA_0) an i_01_0 MXP_00.g2 A1.i1 an i_02_0 MXP_02.f2 A2.i1 an i_03_0 MXP_02.g2 A3.i1 an i_04_0 MXP_04.f2 A4.i1 ;these are channel A inputs 0-8 an i_05_0 MXP_04.g2 A5.i1 an i_06_0 MXP_06.f2 A6.i1 an i_07_0 MXP_06.g2 A7.i1 an i_08_0 MXP_08.f2 A8.i1 an i_09_0 MXP_08.g2 B0.i1 an i_10_0 MXP_10.f2 B1.i1 ;these are channel B inputs 0-6 an i_11_0 MXP_10.g2 B2.i1 an i_12_0 MXP_12.f2 B3.i1 an i_13_0 MXP_12.g2 B4.i1 p 37 an i_14_0 MXP_14.f2 B5.i1 an i_15_0 MXP_14.g2 B6.i1 ;MSB (output on XDATA_15) ;these inputs are selected if mux address = 01 an i_15_1 MXP_14.g3 D6.i1 ;MSB (output on XDATA_15) an i_14_1 MXP_14.f3 D3.i1 an i_13_1 MXP_12.g3 D2.i1 ;these are DST inputs 0-3, 6 an i_12_1 MXP_12.f3 D1.i1 an i_11_1 MXP_10.g3 D0.i1 an lca_s0 MXP_10.f3 M0.i1 ;these are MTG inputs 0-8 an lca_s1 MXP_08.g3 M1.i1 ;MTG 0-2 = lca select lines an lca_s2 MXP_08.f3 M2.i1 ap mux_a0 MXP_06.g3 ;MTG 3,4 = mux address lines ap mux_a1 MXP_06.f3 an i_05_1 MXP_04.g3 M5.i1 an i_04_1 MXP_04.f3 M6.i1 an i_03_1 MXP_02.g3 M7.i1 an i_02_1 MXP_02.f3 M8.i1 an i_01_1 MXP_00.g3 B8.i1 ;these are channel B inputs 7, 8 an i_00_1 MXP_00.f3 B7.i1 ;LSB (output on XDATA_0) p 38 ;these inputs are selected if mux address = 1x ;MSB (output on XDATA_15) an i_15_2 MXF_14.g4 md0.i ;this bit is the LCA's M0 (conf mode 0 pin) an zero MXF_14.f4 GEN_DC.x ap zero MXF_12.g4 ;these bits are unused and are set to 0 ap zero MXF_12.f4 ap zero MXF_10.g4 ap zero MXF_10.f4 an lca_2 MXF_08.g4 I6.i1 ;LCA_2 = GI (GAL input) 6 an lca_1 MXF_08.f4 I5.i1 ;LCA_1 = GI (GAL input) 5 an lca_0 MXF_06.g4 I4.i1 ;LCA_0 = GI (GAL input) 4 an i_06_2 MXF_06.f4 I3.i1 ;JMP_1 = GI (GAL input) 3 an i_05_2 MXF_04.g4 I0.i1 ;JMP_0 = GI (GAL input) 0 an i_04_2 MXF_04.f4 SI.i1 ;this is serial diagnostic data input an i_03_2 MXF_02.g4 O3.i1 ;these are GO (GAL output) inputs 0-3 an i_02_2 MXF_02.f4 O2.i1 an i_01_2 MXF_00.g4 O1.i1 an i_00_2 MXF_00.f4 O0.i1 ;LSB (output on XDATA_0) ; these are output_enable nets ap lca_2 COMPARE.g3 ;LCA_2 = GI (GAL input) 6 ap lca_1 COMPARE.f3 ;LCA_1 = GI (GAL input) 5 ap lca_0 COMPARE.f1 ;LCA_0 = GI (GAL input) 4 ;ap lca_2 MXF_06.g4 I6.i1 ;LCA_2 = GI (GAL input) 6 ;ap lca_1 MXF_06.f4 I5.i1 ;LCA_1 = GI (GAL input) 5 ;ap lca_0 MXF_04.g4 I4.i1 ;LCA_0 = GI (GAL input) 4 ap lca_s2 COMPARE.g2 ap lca_s1 COMPARE.f4 ap lca_s0 COMPARE.f2 an pre_oe COMPARE.x DELAY.f1 GEN_OE.g2 an del_1 DELAY.x DELAY.g1 ;make delayed version of pre_oe an del_2 DELAY.y GEN_OE.f1 an del_3 GEN_OE.x GEN_OE.G1 ap i_04_2 SO.o ;connect serial out to serial in (diag) ;also available: md0.i ("M0"), md1.o ("M1"), md2.i ("M2") ;md1 and md0 are connected off-chip, md2 is tied to VCC ;md1.o is controlled by md1.t Burn-in Configuration file eburn_0.txt (all .x files for the ERPB burn-in configuration): ----------------------------------------------------------- File ALL.x ----------------------------------------------------------- ;This file is used to create the ERPB burn LCA ;Select LCA type XC4002PC84, then go to EDIT_LCA ;In EDIT_LCA, type exec all.x p 39 execute blk_name.x ;name blocks (clb's, iob's, buffers) execute nets.x ;route input nets execute blk_conf.x ;configure some blocks execute blk_copy.x ;copy to all other configured blocks endfile em = electromagnetic energy to = tot = total energy blk_name.x names blocks (clb's, iob's, buffers) nets.x adds and routes all nets ----------------------------------------------------------- File BLK_CONF.x ----------------------------------------------------------- ; Block Configuration File Generated by blocks.c ; Source File: blks.xrp editblk COMP_01 config F4: G2:G2I G3:G3I X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3 G:G1:G2:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = ~F1*~F2*~F3 equate G = G1*~G2*~G3 endblk editblk COMP_7 config F4: G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3 G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*F2*F3 endblk editblk COMPARE config F4:F4I G2:G2I G3:G3I X:H Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3:F4 G:G2:G3 H:F:G H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = (F1@F2)+(F3@F4) equate G = G2@G3 equate H = ~(F+G) endblk editblk COUNT_00 config F4: G2:G2I G3: X: Y: XQ:QX YQ:QY FFX:K:NOT:RESET FFY:K:NOT:RESET DX:F DY:G F:F1 G:G1:G2 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = ~F1 equate G = G1*(~G2)+(~G1)*G2 endblk editblk GENM1 p 40 config F4: G2: G3: X: Y:G XQ:QX YQ: FFX:K:RESET FFY:RESET DX:F DY: F:F1 G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = ~F1 equate G = 1 endblk editblk MUXSRD config F4: G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3 G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*F3+(~F1)*F2 endblk editblk SR00 config F4: G2: G3: X: Y: XQ:QX YQ:QY FFX:K:RESET FFY:K:RESET DX:F DY:G F:F1 G:G1 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1 equate G = G1 endblk editblk A0 config INFF:IK I1:IQ I2: O: OUT:OQ:OK PAD: TRI:T RDBK: OSPEED:SLOW endblk editblk E5 config INFF: I1:I I2: O: OUT:O PAD: TRI:T:NOT RDBK: OSPEED:SLOW endblk editblk HDC config INFF: I1: I2: O: OUT: PAD:PULLDOWN TRI: RDBK: OSPEED:SLOW endblk editblk I4 config INFF: I1:I I2: O: OUT: PAD: TRI: RDBK: OSPEED: endblk editblk SI config INFF: I1:I I2: O: OUT: PAD: TRI: RDBK: OSPEED:SLOW endblk editblk SO config INFF: I1: I2: O: OUT:O PAD: TRI: RDBK: OSPEED:SLOW endblk editblk T0 config INFF: I1: I2: O: OUT:O PAD:PULLUP TRI:T:NOT RDBK: OSPEED:FAST endblk ----------------------------------------------------------- File BLK_COPY.x ----------------------------------------------------------- ; This file copies configured blocks to unconfigured blocks that should ; have the same configuration. ;COMP_01 p 41 ;COMP_7 ;COMPARE ;GENM1 ;MUXSRD ;SI ;SO cb I4 I5 I6 ;LCA_0 - LCA_2 cb SR00 SR02 SR04 SR06 SR08 cb SR00 SR10 SR12 SR14 SR16 SR18 cb SR00 SR20 SR22 SR24 SR26 SR28 cb SR00 SR30 SR32 SR34 SR36 SR38 cb SR00 SR40 SR42 SR44 SR46 SR48 cb SR00 SR50 SR52 SR54 SR56 SR58 cb SR00 SR60 SR62 SR64 SR66 SR68 cb SR00 SR70 SR72 SR74 SR76 SR78 cb SR00 SR80 SR82 SR84 SR86 cb COUNT_00 COUNT_02 COUNT_04 COUNT_06 COUNT_08 cb COUNT_00 COUNT_10 COUNT_12 COUNT_14 COUNT_16 COUNT_18 cb COUNT_00 COUNT_20 COUNT_22 COUNT_24 COUNT_26 ;input pins (configured as disabled tri-state i/o) cb A0 A1 A2 A3 A4 A5 A6 A7 A8 ;Channel A from CTFE cb A0 B0 B1 B2 B3 B4 B5 B6 B7 B8 ;Channel B from CTFE cb A0 M0 M1 M2 M3 M4 M5 M6 M7 M8 ;MTG 0-8 cb E5 E6 E7 ;these select LCA to drive bus cb T0 T1 T2 T3 T4 T5 T6 T7 ;these are connected to bus cb T0 E0 E1 E2 E3 E4 cb T0 I0 ;GI_0 is also a tri-state output ----------------------------------------------------------- File BLK_NAME.x ----------------------------------------------------------- ;This file names blocks. nb clb_r3c7 COMPARE ;compares LCA# with E5-E7 nb clb_r2c8 COMP_01 ;checks if LCA# is 0 or 1 nb clb_r3c8 COMP_7 ;checks if LCA# is 7 nb clb_r3c6 MUXSRD ;selects shift register data nb clb_r8c1 GENM1 ;generates M1 output nb clb_r1c8 COUNT_00 ;counter nb clb_r1c7 COUNT_02 nb clb_r1c6 COUNT_04 nb clb_r1c5 COUNT_06 nb clb_r1c4 COUNT_08 nb clb_r1c3 COUNT_10 nb clb_r1c2 COUNT_12 p 42 nb clb_r1c1 COUNT_14 nb clb_r2c6 COUNT_16 nb clb_r2c5 COUNT_18 nb clb_r2c4 COUNT_20 nb clb_r2c3 COUNT_22 nb clb_r2c2 COUNT_24 nb clb_r2c1 COUNT_26 nb clb_r3c5 SR00 ;shift register nb clb_r3c4 SR02 nb clb_r3c3 SR04 nb clb_r3c2 SR06 nb clb_r3c1 SR08 nb clb_r4c8 SR10 nb clb_r4c7 SR12 nb clb_r4c6 SR14 nb clb_r4c5 SR16 nb clb_r4c4 SR18 nb clb_r4c3 SR20 nb clb_r4c2 SR22 nb clb_r4c1 SR24 nb clb_r5c8 SR26 nb clb_r5c7 SR28 nb clb_r5c6 SR30 nb clb_r5c5 SR32 nb clb_r5c4 SR34 nb clb_r5c3 SR36 nb clb_r5c2 SR38 nb clb_r5c1 SR40 nb clb_r6c8 SR42 nb clb_r6c7 SR44 nb clb_r6c6 SR46 nb clb_r6c5 SR48 nb clb_r6c4 SR50 nb clb_r6c3 SR52 nb clb_r6c2 SR54 nb clb_r6c1 SR56 nb clb_r7c8 SR58 nb clb_r7c7 SR60 nb clb_r7c6 SR62 nb clb_r7c5 SR64 nb clb_r7c4 SR66 nb clb_r7c3 SR68 nb clb_r7c2 SR70 nb clb_r7c1 SR72 nb clb_r8c8 SR74 nb clb_r8c7 SR76 nb clb_r8c6 SR78 nb clb_r8c5 SR80 nb clb_r8c4 SR82 nb clb_r8c3 SR84 nb clb_r8c2 SR86 p 43 nb p9 E7 ;electromagnetic energy ouputs nb p14 E6 nb p15 E5 nb p16 E4 nb p17 E3 nb p18 E2 nb p19 E1 nb p20 E0 nb p23 T7 ;total energy ouputs nb p24 T6 nb p25 T5 nb p26 T4 nb p27 T3 nb p37 T2 nb p28 T1 nb p29 T0 nb p38 A0 ;channel A data inputs nb p39 A1 nb p40 A2 nb p44 A3 nb p45 A4 nb p46 A5 nb p47 A6 nb p48 A7 nb p49 A8 nb p50 B0 ;channel B data inputs nb p56 B1 nb p58 B2 nb p59 B3 nb p60 B4 nb p61 B5 nb p62 B6 nb p65 B7 nb p66 B8 nb p13 M0 ;MTG 0-8 nb p35 M1 nb p10 M2 nb p80 M3 nb p51 M4 nb p78 M5 nb p3 M6 nb p4 M7 nb p5 M8 nb p57 D0 ;DST 0-6 nb p6 D1 nb p7 D2 nb p8 D3 ;nb p13 D4 ;"PROG*" ;nb p13 D5 ;"CCLK" nb p71 D6 ;"DIN" p 44 nb p79 SI ;diagnostics serial data in nb p41 SO ;diagnostics serial data out = "INIT*" nb p77 I0 ;GI 0-6 nb TDO I1 ;"TDO" (output only) tdo.o is controlled by tdo.t nb p72 I2 ;"DOUT" nb p70 I3 nb p69 I4 ;(LCA_0) nb p68 I5 ;(LCA_1) nb p67 I6 ;(LCA_2) nb p81 O0 ;GO 0-3 nb p82 O1 nb p83 O2 nb p84 O3 nb p36 HDC ;HDC = High During Configuration (pulldown after configuration) ;also available: md0.i ("M0"), md1.o ("M1"), md2.i ("M2") ;md1 and md0 are connected off-chip, md2 is tied to VCC ;md1.o is controlled by md1.t ----------------------------------------------------------- File NETS.x ----------------------------------------------------------- ;This file routes nets. an c_00 COUNT_00.xq COUNT_00.f1 COUNT_00.g1 an c_02 COUNT_02.xq COUNT_02.f1 COUNT_02.g1 an c_04 COUNT_04.xq COUNT_04.f1 COUNT_04.g1 an c_06 COUNT_06.xq COUNT_06.f1 COUNT_06.g1 an c_08 COUNT_08.xq COUNT_08.f1 COUNT_08.g1 an c_10 COUNT_10.xq COUNT_10.f1 COUNT_10.g1 an c_12 COUNT_12.xq COUNT_12.f1 COUNT_12.g1 an c_14 COUNT_14.xq COUNT_14.f1 COUNT_14.g1 an c_16 COUNT_16.xq COUNT_16.f1 COUNT_16.g1 an c_18 COUNT_18.xq COUNT_18.f1 COUNT_18.g1 an c_20 COUNT_20.xq COUNT_20.f1 COUNT_20.g1 an c_22 COUNT_22.xq COUNT_22.f1 COUNT_22.g1 an c_24 COUNT_24.xq COUNT_24.f1 COUNT_24.g1 an c_26 COUNT_26.xq COUNT_26.f1 COUNT_26.g1 an c_01 COUNT_00.yq COUNT_00.g2 COUNT_02.k an c_03 COUNT_02.yq COUNT_02.g2 COUNT_04.k an c_05 COUNT_04.yq COUNT_04.g2 COUNT_06.k an c_07 COUNT_06.yq COUNT_06.g2 COUNT_08.k an c_09 COUNT_08.yq COUNT_08.g2 COUNT_10.k an c_11 COUNT_10.yq COUNT_10.g2 COUNT_12.k an c_13 COUNT_12.yq COUNT_12.g2 COUNT_14.k an c_15 COUNT_14.yq COUNT_14.g2 COUNT_16.k an c_17 COUNT_16.yq COUNT_16.g2 COUNT_18.k an c_19 COUNT_18.yq COUNT_18.g2 COUNT_20.k an c_21 COUNT_20.yq COUNT_20.g2 COUNT_22.k p 45 an c_23 COUNT_22.yq COUNT_22.g2 COUNT_24.k an c_25 COUNT_24.yq COUNT_24.g2 COUNT_26.k an c_27 COUNT_26.yq COUNT_26.g2 an s_00 SR00.xq SR00.g1 an s_02 SR02.xq SR02.g1 an s_04 SR04.xq SR04.g1 an s_06 SR06.xq SR06.g1 an s_08 SR08.xq SR08.g1 an s_10 SR10.xq SR10.g1 an s_12 SR12.xq SR12.g1 an s_14 SR14.xq SR14.g1 an s_16 SR16.xq SR16.g1 an s_18 SR18.xq SR18.g1 an s_20 SR20.xq SR20.g1 an s_22 SR22.xq SR22.g1 an s_24 SR24.xq SR24.g1 an s_26 SR26.xq SR26.g1 an s_28 SR28.xq SR28.g1 an s_30 SR30.xq SR30.g1 an s_32 SR32.xq SR32.g1 an s_34 SR34.xq SR34.g1 an s_36 SR36.xq SR36.g1 an s_38 SR38.xq SR38.g1 an s_40 SR40.xq SR40.g1 an s_42 SR42.xq SR42.g1 an s_44 SR44.xq SR44.g1 an s_46 SR46.xq SR46.g1 an s_48 SR48.xq SR48.g1 an s_50 SR50.xq SR50.g1 an s_52 SR52.xq SR52.g1 an s_54 SR54.xq SR54.g1 an s_56 SR56.xq SR56.g1 an s_58 SR58.xq SR58.g1 an s_60 SR60.xq SR60.g1 an s_62 SR62.xq SR62.g1 an s_64 SR64.xq SR64.g1 an s_66 SR66.xq SR66.g1 an s_68 SR68.xq SR68.g1 an s_70 SR70.xq SR70.g1 an s_72 SR72.xq SR72.g1 an s_74 SR74.xq SR74.g1 an s_76 SR76.xq SR76.g1 an s_78 SR78.xq SR78.g1 an s_80 SR80.xq SR80.g1 an s_82 SR82.xq SR82.g1 an s_84 SR84.xq SR84.g1 an s_86 SR86.xq SR86.g1 an srd MUXSRD.x SR00.f1 an s_01 SR00.yq SR02.f1 an s_03 SR02.yq SR04.f1 an s_05 SR04.yq SR06.f1 an s_07 SR06.yq SR08.f1 an s_09 SR08.yq SR10.f1 an s_11 SR10.yq SR12.f1 an s_13 SR12.yq SR14.f1 p 46 an s_15 SR14.yq SR16.f1 an s_17 SR16.yq SR18.f1 an s_19 SR18.yq SR20.f1 an s_21 SR20.yq SR22.f1 an s_23 SR22.yq SR24.f1 an s_25 SR24.yq SR26.f1 an s_27 SR26.yq SR28.f1 an s_29 SR28.yq SR30.f1 an s_31 SR30.yq SR32.f1 an s_33 SR32.yq SR34.f1 an s_35 SR34.yq SR36.f1 an s_37 SR36.yq SR38.f1 an s_39 SR38.yq SR40.f1 an s_41 SR40.yq SR42.f1 an s_43 SR42.yq SR44.f1 an s_45 SR44.yq SR46.f1 an s_47 SR46.yq SR48.f1 an s_49 SR48.yq SR50.f1 an s_51 SR50.yq SR52.f1 an s_53 SR52.yq SR54.f1 an s_55 SR54.yq SR56.f1 an s_57 SR56.yq SR58.f1 an s_59 SR58.yq SR60.f1 an s_61 SR60.yq SR62.f1 an s_63 SR62.yq SR64.f1 an s_65 SR64.yq SR66.f1 an s_67 SR66.yq SR68.f1 an s_69 SR68.yq SR70.f1 an s_71 SR70.yq SR72.f1 an s_73 SR72.yq SR74.f1 an s_75 SR74.yq SR76.f1 an s_77 SR76.yq SR78.f1 an s_79 SR78.yq SR80.f1 an s_81 SR80.yq SR82.f1 an s_83 SR82.yq SR84.f1 an s_85 SR84.yq SR86.f1 an s_87 SR86.yq SO.o ap S_63 COUNT_00.k ;clock to counter ap C_23 I0.o ;send xmit_clk/2^24 to GI_0 an lca_2 I6.i1 COMPARE.g3 COMP_01.f2 COMP_01.g2 COMP_7.f2 ;LCA_2 = GI (GAL input) 6 an lca_1 I5.i1 COMPARE.f3 COMP_01.f3 COMP_01.g3 COMP_7.f3 ;LCA_1 = GI (GAL input) 5 an lca_0 I4.i1 COMPARE.f1 COMP_01.f1 COMP_01.g1 COMP_7.f1 ;LCA_0 = GI (GAL input) 4 an E7_in E7.i1 COMPARE.g2 an E6_in E6.i1 COMPARE.f4 an E5_in E5.i1 COMPARE.f2 an lca7 COMP_7.x MUXSRD.f1 an diag_in SI.i1 MUXSRD.f2 an m0_in md0.i MUXSRD.f3 p 47 an lca0 COMP_01.x md1.t E5.t E6.t E7.t an lca1 COMP_01.y I0.t an lcaeq COMPARE.x E0.t E1.t E2.t E3.t E4.t T0.t T1.t T2.t T3.t T4.t T5.t T6.t T7.t an m1out GENM1.xq GENM1.f1 md1.o ap S_08 E4.o E3.o E2.o E1.o E0.o T7.o T6.o T5.o T4.o T3.o T2.o T1.o T0.o ;output data ap c_27 E7.o ;counter MSB's select LCA to drive bus ap c_26 E6.o ap c_25 E5.o an p_xck i_bufgp_br.i bufgp_br.i an xmit_clk bufgp_br.o SR00.k SR02.k SR04.k SR06.k SR08.k ap xmit_clk SR10.k SR12.k SR14.k SR16.k SR18.k ap xmit_clk SR20.k SR22.k SR24.k SR26.k SR28.k ap xmit_clk SR30.k SR32.k SR34.k SR36.k SR38.k ap xmit_clk SR40.k SR42.k SR44.k SR46.k SR48.k ap xmit_clk SR50.k SR52.k SR54.k SR56.k SR58.k ap xmit_clk SR60.k SR62.k SR64.k SR66.k SR68.k ap xmit_clk SR70.k SR72.k SR74.k SR76.k SR78.k ap xmit_clk SR80.k SR82.k SR84.k SR86.k ap xmit_clk GENM1.k ap xmit_clk A0.ik A1.ik A2.ik A3.ik A4.ik A5.ik A6.ik A7.ik A8.ik ap xmit_clk B0.ik B1.ik B2.ik B3.ik B4.ik B5.ik B6.ik B7.ik B8.ik ap xmit_clk M0.ik M1.ik M2.ik M3.ik M4.ik M5.ik M6.ik M7.ik M8.ik ap xmit_clk A0.ok A1.ok A2.ok A3.ok A4.ok A5.ok A6.ok A7.ok A8.ok ap xmit_clk B0.ok B1.ok B2.ok B3.ok B4.ok B5.ok B6.ok B7.ok B8.ok ap xmit_clk M0.ok M1.ok M2.ok M3.ok M4.ok M5.ok M6.ok M7.ok M8.ok an hiz GENM1.y A0.t A1.t A2.t A3.t A4.t A5.t A6.t A7.t A8.t ap hiz B0.t B1.t B2.t B3.t B4.t B5.t B6.t B7.t B8.t ap hiz M0.t M1.t M2.t M3.t M4.t M5.t M6.t M7.t M8.t an af0 A0.o A0.i1 an af1 A1.o A1.i1 an af2 A2.o A2.i1 an af3 A3.o A3.i1 an af4 A4.o A4.i1 an af5 A5.o A5.i1 an af6 A6.o A6.i1 an af7 A7.o A7.i1 an af8 A8.o A8.i1 an bf0 B0.o B0.i1 an bf1 B1.o B1.i1 an bf2 B2.o B2.i1 an bf3 B3.o B3.i1 p 48 an bf4 B4.o B4.i1 an bf5 B5.o B5.i1 an bf6 B6.o B6.i1 an bf7 B7.o B7.i1 an bf8 B8.o B8.i1 an mf0 M0.o M0.i1 an mf1 M1.o M1.i1 an mf2 M2.o M2.i1 an mf3 M3.o M3.i1 an mf4 M4.o M4.i1 an mf5 M5.o M5.i1 an mf6 M6.o M6.i1 an mf7 M7.o M7.i1 an mf8 M8.o M8.i1 Run_00 Configuration file e_run_00.txt (all .x files for the ERPB run_00 configuration): ----------------------------------------------------------- File ALL.x ----------------------------------------------------------- execute blk_name.x ;name blocks (clb's, iob's, buffers) execute glob_nets.x ;route global nets execute in_nets.x ;route input nets execute ctrl_nets.x ;route control nets execute data_nets.x ;route data nets execute blk_conf.x ;configure some blocks execute blk_copy.x ;copy to all other configured blocks endfile ----------------------------------------------------------- File BLK_CONF.x ----------------------------------------------------------- ; Block Configuration File Generated by blocks.c ; Source File: blks.xrp editblk COMPARE config F4: G2: G3: X:H Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3:F4 G:G1:G2 H:F:G H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1@F3+F2@F4 equate G = G1@G2 equate H = F+G endblk editblk DELAY config F4: G2: G3: X:F Y:H XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1 G:G1 H:G H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1 equate G = G1 equate H = G p 49 endblk editblk EM__WE_GEN config F4: G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3:F4 G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = ~F1*~F3*~F4 endblk editblk FINAL_OE config F4: G2: G3: X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2 G:G1 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1+F2 equate G = G1 endblk editblk FLOAT_HARD config F4: G2: G3: X:F Y: XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F2:F3:F4 G: H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F4+~(F1*~F2*~F3) endblk editblk LAT_CK_GEN config F4: G2: G3: X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F: G:G1:G3:G4 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = 0 equate G = ~G1+G3+G4 endblk editblk ORDER_A config F4: G2: G3: X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3 G:G1:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1@F3 equate G = G1@G3 endblk editblk ORDER_B config F4: G2: G3: X:F Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F:F1:F3 G:G1:G2:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1@~F3 equate G = G2@(G1*~G3) endblk editblk STATE_CTRL config F4: G2: G3: X:F Y:G XQ:QX YQ: FFX:K:RESET FFY:RESET DX:F DY: F:F1:F2:F3:F4 G:G2:G3:G4 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*F2*F3*F4 equate G = G2*G3*G4 endblk editblk STATE_01 config F4: G2: G3: X:H Y: XQ:QX YQ:QY FFX:K:RESET FFY:K:RESET DX:F DY:G F:F1:F2:F3 G:G1:G2:G3:G4 H:F:G H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*(F2@~F3) equate G = G1*(G4@(~G3*G2)) equate H = ~F*~G endblk p 50 editblk STATE_23 config F4: G2: G3: X:H Y: XQ:QX YQ:QY FFX:K:RESET FFY:K:RESET DX:F DY:G F:F1:F2:F3:F4 G:G1:G2:G3:G4 H:F:H1 H1:C4 DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*(F2@(~F3*F4)) equate G = G1*(G4@(~G3*G2)) equate H = H1*~F endblk editblk TO__WE_GEN config F4: G2: G3: X: Y:G XQ: YQ: FFX:RESET FFY:RESET DX: DY: F: G:G1:G3:G4 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate G = G1*~G3*~G4 endblk editblk TO_LAT_A_0 config F4: G2: G3: X: Y: XQ:QX YQ:QY FFX:K:RESET FFY:K:RESET DX:F DY:G F:F3 G:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F3 equate G = G3 endblk editblk TO_MXL_B_0 config F4: G2: G3: X:F Y:G XQ:QX YQ:QY FFX:K:RESET FFY:K:RESET DX:DIN DY:H F:F1:F2:F4 G:G1:G2:G4 H:H1 H1:C4 DIN:C3 SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1*F2+(~F1)*F4 equate G = G1*G2+(~G1)*G4 equate H = H1 endblk editblk TO_XLB_B_0 config F4: G2: G3: X: Y: XQ:QX YQ:QY FFX:K:NOT:RESET FFY:K:NOT:RESET DX:F DY:G F:F1:F3 G:G1:G3 H: H1: DIN: SR: EC: RAM: CIN: COUT: CDIR: RDBK: equate F = F1+F3 equate G = G1+G3 endblk editblk A0 config INFF: I1: I2:I O: OUT: PAD: TRI: RDBK: OSPEED:SLOW endblk editblk SO config INFF: I1: I2: O: OUT:O PAD: TRI: RDBK: OSPEED:SLOW endblk editblk T0 config INFF: I1: I2: O: OUT:O PAD: TRI:T RDBK: OSPEED:SLOW endblk editblk P36 config INFF: I1: I2: O: OUT: PAD:PULLDOWN TRI: RDBK: OSPEED:SLOW endblk ----------------------------------------------------------- p 51 File BLK_COPY.x ----------------------------------------------------------- ;this file copies configured blocks to non-configured blocks cb TO_MXL_B_0 TO_MXL_B_1 TO_MXL_B_2 TO_MXL_B_3 cb TO_MXL_B_0 EM_MXL_B_0 EM_MXL_B_1 EM_MXL_B_2 EM_MXL_B_3 cb TO_LAT_A_0 TO_LAT_A_1 TO_LAT_A_2 TO_LAT_A_3 cb TO_LAT_A_0 EM_LAT_A_0 EM_LAT_A_1 EM_LAT_A_2 EM_LAT_A_3 cb TO_XLB_B_0 TO_XLB_B_1 TO_XLB_B_2 TO_XLB_B_3 cb TO_XLB_B_0 EM_XLB_B_0 EM_XLB_B_1 EM_XLB_B_2 EM_XLB_B_3 cb TO_XLB_B_0 TO_XLB_A_0 TO_XLB_A_1 TO_XLB_A_2 TO_XLB_A_3 cb TO_XLB_B_0 EM_XLB_A_0 EM_XLB_A_1 EM_XLB_A_2 EM_XLB_A_3 ; direct inputs cb A0 B8 B7 B6 B5 B4 B3 B2 B1 B0 A8 A7 A6 A5 A4 A3 A2 A1 cb A0 ST LA D2 RI J0 DN L0 L1 L2 ;direct outputs cb SO NE ; tristate outputs cb T0 E7 E6 E5 E4 E3 E2 E1 E0 T7 T6 T5 T4 T3 T2 T1 cb T0 RO ----------------------------------------------------------- File BLK_NAME.x ----------------------------------------------------------- nb clb_r1c5 STATE_CTRL ;state machine control, etc. nb clb_r2c5 STATE_01 ;state machine registers, etc. nb clb_r3c5 STATE_23 nb clb_r2c6 ORDER_A ;transmit order translation nb clb_r3c6 ORDER_B nb clb_r3c7 COMPARE ;comparison of currently transmitting LCA w/ LCA's id# nb clb_r2c8 DELAY ;delay for delaying fall of fin_oe_bar nb clb_r2c7 FINAL_OE ;final gating for LCA's oe\ nb clb_r3c8 FLOAT_HARD ;float hardwired inputs unless LCA id# = 1 ;_A_ = channel A ;_B_ = channel B ;TO = total energy ;EM = electromagnetic energy nb clb_r1c1 EM_MXL_B_3 ;MXL_B = output mux + latch for channel B nb clb_r2c1 EM_MXL_B_2 nb clb_r3c1 EM_MXL_B_1 p 52 nb clb_r4c1 EM_MXL_B_0 nb clb_r1c2 EM_LAT_A_3 ;LAT_A = latch for channel A nb clb_r2c2 EM_LAT_A_2 nb clb_r3c2 EM_LAT_A_1 nb clb_r4c2 EM_LAT_A_0 nb clb_r1c3 EM_XLB_A_3 ;XLB = translate (from 9 to 8 bits) + buffer nb clb_r2c3 EM_XLB_A_2 ;for this design, the buffer is only 1 deep nb clb_r3c3 EM_XLB_A_1 nb clb_r4c3 EM_XLB_A_0 nb clb_r1c4 EM_XLB_B_3 nb clb_r2c4 EM_XLB_B_2 nb clb_r3c4 EM_XLB_B_1 nb clb_r4c4 EM_XLB_B_0 nb clb_r5c1 TO_MXL_B_3 ;MXL_B = output mux + latch for channel B nb clb_r6c1 TO_MXL_B_2 nb clb_r7c1 TO_MXL_B_1 nb clb_r8c1 TO_MXL_B_0 nb clb_r5c2 TO_LAT_A_3 ;LAT_A = latch for channel A nb clb_r6c2 TO_LAT_A_2 nb clb_r7c2 TO_LAT_A_1 nb clb_r8c2 TO_LAT_A_0 nb clb_r5c3 TO_XLB_A_3 ;XLB = translate (from 9 to 8 bits) + buffer nb clb_r6c3 TO_XLB_A_2 ;for this design, the buffer is only 1 deep nb clb_r7c3 TO_XLB_A_1 nb clb_r8c3 TO_XLB_A_0 nb clb_r5c4 TO_XLB_B_3 nb clb_r6c4 TO_XLB_B_2 nb clb_r7c4 TO_XLB_B_1 nb clb_r8c4 TO_XLB_B_0 nb clb_r8c8 TO__WE_GEN ;clock and write enable generators nb clb_r8c5 EM__WE_GEN nb clb_r1c8 LAT_CK_GEN nb p9 E7 ;electromagnetic energy ouputs nb p14 E6 nb p15 E5 nb p16 E4 nb p17 E3 nb p18 E2 nb p19 E1 nb p20 E0 nb p23 T7 ;total energy ouputs nb p24 T6 nb p25 T5 nb p26 T4 nb p27 T3 p 53 nb p37 T2 nb p28 T1 nb p29 T0 nb p38 A0 ;channel A data inputs nb p39 A1 nb p40 A2 nb p44 A3 nb p45 A4 nb p46 A5 nb p47 A6 nb p48 A7 nb p49 A8 nb p50 B0 ;channel B data inputs nb p56 B1 nb p58 B2 nb p59 B3 nb p60 B4 nb p61 B5 nb p62 B6 nb p65 B7 nb p66 B8 nb p35 TO ;total (input) tells if data is total or electromagnetic nb p10 ST ;store (input) tells LCA to store data in buffer nb p80 LA ;latch (input) tells LCA to latch buffer output nb p13 IK ;input clock nb p57 XK ;transmit clock nb p81 RI ;ready in = down daisy chain (DDC) in (GO_0) nb p70 RO ;ready out = down daisy chain (DDC) out (GI_3) ;because GI_3 = JMP_1, all LCA's except #1 must float GI_3 nb p41 SO ;DIAG_O (= serial output) (used as a test point in this design) nb p77 J0 ;JMP_0 (when low = eccentric readout order) nb p7 D2 ;DST_2 (when high = negative ETA readout order) nb p72 NE ;(GI_2) output enable for next ERPB's register (active high) nb tdo TE ;(GI_1) output enable for this ERPB's LCA buffer (active low) (tdo = pin 75) nb p69 L0 ;LCA #0 hard-wired LCA ID # nb p68 L1 ;LCA #1 nb p67 L2 ;LCA #2 nb p71 DN ;LCA configuration data in (used to float hardwired i/o's) ;hard-wired i/o's should be configured to float when DIN is high ;at the end of configuration, DIN looks like: ~~~~~~~~~\______ ; logic becomes active here --^ ----------------------------------------------------------- File CTRL_NET.x p 54 ----------------------------------------------------------- ;s0-s3 are the state machine's outputs an s0 STATE_01.xq STATE_CTRL.f1 an s1 STATE_01.yq STATE_CTRL.f2 STATE_CTRL.g2 an s2 STATE_23.xq STATE_CTRL.f3 STATE_CTRL.g3 an s3 STATE_23.yq STATE_CTRL.f4 STATE_CTRL.g4 ;feedback within state machine ap s0 STATE_01.f2 STATE_01.g2 ap s1 STATE_01.g4 ap s2 STATE_23.f2 ap s3 STATE_23.g4 an carry_1 STATE_01.x STATE_23.f4 STATE_23.c4 an carry_2 STATE_23.x STATE_23.g2 ;hold holds the state machine (when high) an hold STATE_CTRL.x STATE_01.f3 STATE_01.g3 ap hold STATE_23.f3 STATE_23.g3 ;clear_bar clears the state machine (when low) an clear_bar RI.i2 STATE_01.f1 STATE_01.g1 ap clear_bar STATE_23.f1 STATE_23.g1 ;buf_oes (when high) disables this ERPB's LCA buffer ; and enables next ERPB's output register an buf_oes STATE_CTRL.xq TE.o NE.o ;ready output to next ERPB (the XMIT GAL delay of one clock forms DDC out) an ready_out STATE_CTRL.y RO.o ;translation of state into transmission order, then into this LCA's oe ap s0 ORDER_A.f1 ap s1 ORDER_A.g1 ap s2 ORDER_B.f1 ORDER_B.g1 ap s3 ORDER_B.g2 ;neg_eta = DST_2 = use transmission order appropriate to negative eta an neg_eta D2.i2 ORDER_A.f3 ORDER_A.g3 ;normal = normal readout (when high) or eccentric readout (when low) an normal J0.i2 ORDER_B.f3 ORDER_B.g3 ;output_B = output channel B (when high) or channel A (when low) an output_B ORDER_A.x EM_MXL_B_0.f1 EM_MXL_B_0.g1 ap output_B EM_MXL_B_1.f1 EM_MXL_B_1.g1 ap output_B EM_MXL_B_2.f1 EM_MXL_B_2.g1 ap output_B EM_MXL_B_3.f1 EM_MXL_B_3.g1 ap output_B TO_MXL_B_0.f1 TO_MXL_B_0.g1 p 55 ap output_B TO_MXL_B_1.f1 TO_MXL_B_1.g1 ap output_B TO_MXL_B_2.f1 TO_MXL_B_2.g1 ap output_B TO_MXL_B_3.f1 TO_MXL_B_3.g1 ;x_lca = id# of LCA which should currently have its data outputs enabled an x_lca_0 ORDER_A.y COMPARE.f1 an x_lca_1 ORDER_B.x COMPARE.f2 an x_lca_2 ORDER_B.y COMPARE.g1 ;this_lca = hardwired id# of this LCA an this_lca_0 L0.i2 COMPARE.f3 FLOAT_HARD.f1 an this_lca_1 L1.i2 COMPARE.f4 FLOAT_HARD.f2 an this_lca_2 L2.i2 COMPARE.g2 FLOAT_HARD.f3 ;hard_oe_bar enables output of hard-wired i/o's if LCA id# = 1 ;and if din_float is low. din_float goes low shortly after configuration an din_float DN.i2 FLOAT_HARD.f4 an hard_oe_bar FLOAT_HARD.x RO.t an low LAT_CK_GEN.x TE.t ;all LCA's have this output enabled, ;though it is only used by LCA 1 ;output enable for this chip (active low) ;a delay is used to delay the fall of fin_oe_bar an pre_oe_bar COMPARE.x DELAY.g1 FINAL_OE.f2 an delay_1 DELAY.y DELAY.f1 an delay_2 DELAY.x FINAL_OE.g1 an delay_3 FINAL_OE.y FINAL_OE.f1 autoroute off an fin_oe_bar FINAL_OE.x E0.t E1.t E2.t E3.t E4.t E5.t E6.t E7.t ap fin_oe_bar T0.t T1.t T2.t T3.t T4.t T5.t T6.t T7.t ap fin_oe_bar SO.o ;output fin_oe_bar on DIAG_O for test only en fin_oe_bar row.C.long.1:CI.X en fin_oe_bar col.F.local.1:row.C.long.1 en fin_oe_bar col.A.long.0:row.C.long.1 autoroute on route fin_oe_bar ----------------------------------------------------------- File DATA_NET.x ----------------------------------------------------------- ;*** data ***; ;channel A uses a CLB to latch buffer output ;channel B uses the register in the output mux (MXL) ;EM ch A, buffer output an ema_bo_0 EM_XLB_A_0.xq EM_LAT_A_0.f3 an ema_bo_1 EM_XLB_A_0.yq EM_LAT_A_0.g3 an ema_bo_2 EM_XLB_A_1.xq EM_LAT_A_1.f3 an ema_bo_3 EM_XLB_A_1.yq EM_LAT_A_1.g3 p 56 an ema_bo_4 EM_XLB_A_2.xq EM_LAT_A_2.f3 an ema_bo_5 EM_XLB_A_2.yq EM_LAT_A_2.g3 an ema_bo_6 EM_XLB_A_3.xq EM_LAT_A_3.f3 an ema_bo_7 EM_XLB_A_3.yq EM_LAT_A_3.g3 ;TO ch A, buffer output an toa_bo_0 TO_XLB_A_0.xq TO_LAT_A_0.f3 an toa_bo_1 TO_XLB_A_0.yq TO_LAT_A_0.g3 an toa_bo_2 TO_XLB_A_1.xq TO_LAT_A_1.f3 an toa_bo_3 TO_XLB_A_1.yq TO_LAT_A_1.g3 an toa_bo_4 TO_XLB_A_2.xq TO_LAT_A_2.f3 an toa_bo_5 TO_XLB_A_2.yq TO_LAT_A_2.g3 an toa_bo_6 TO_XLB_A_3.xq TO_LAT_A_3.f3 an toa_bo_7 TO_XLB_A_3.yq TO_LAT_A_3.g3 ;EM ch B, buffer output an emb_bo_0 EM_XLB_B_0.xq EM_MXL_B_0.c3 an emb_bo_1 EM_XLB_B_0.yq EM_MXL_B_0.c4 an emb_bo_2 EM_XLB_B_1.xq EM_MXL_B_1.c3 an emb_bo_3 EM_XLB_B_1.yq EM_MXL_B_1.c4 an emb_bo_4 EM_XLB_B_2.xq EM_MXL_B_2.c3 an emb_bo_5 EM_XLB_B_2.yq EM_MXL_B_2.c4 an emb_bo_6 EM_XLB_B_3.xq EM_MXL_B_3.c3 an emb_bo_7 EM_XLB_B_3.yq EM_MXL_B_3.c4 ;TO ch B, buffer output an tob_bo_0 TO_XLB_B_0.xq TO_MXL_B_0.c3 an tob_bo_1 TO_XLB_B_0.yq TO_MXL_B_0.c4 an tob_bo_2 TO_XLB_B_1.xq TO_MXL_B_1.c3 an tob_bo_3 TO_XLB_B_1.yq TO_MXL_B_1.c4 an tob_bo_4 TO_XLB_B_2.xq TO_MXL_B_2.c3 an tob_bo_5 TO_XLB_B_2.yq TO_MXL_B_2.c4 an tob_bo_6 TO_XLB_B_3.xq TO_MXL_B_3.c3 an tob_bo_7 TO_XLB_B_3.yq TO_MXL_B_3.c4 ;EM ch A, latch output an ema_lo_0 EM_LAT_A_0.xq EM_MXL_B_0.f4 an ema_lo_1 EM_LAT_A_0.yq EM_MXL_B_0.g4 an ema_lo_2 EM_LAT_A_1.xq EM_MXL_B_1.f4 an ema_lo_3 EM_LAT_A_1.yq EM_MXL_B_1.g4 an ema_lo_4 EM_LAT_A_2.xq EM_MXL_B_2.f4 an ema_lo_5 EM_LAT_A_2.yq EM_MXL_B_2.g4 an ema_lo_6 EM_LAT_A_3.xq EM_MXL_B_3.f4 an ema_lo_7 EM_LAT_A_3.yq EM_MXL_B_3.g4 ;TO ch A, latch output an toa_lo_0 TO_LAT_A_0.xq TO_MXL_B_0.f4 an toa_lo_1 TO_LAT_A_0.yq TO_MXL_B_0.g4 an toa_lo_2 TO_LAT_A_1.xq TO_MXL_B_1.f4 an toa_lo_3 TO_LAT_A_1.yq TO_MXL_B_1.g4 an toa_lo_4 TO_LAT_A_2.xq TO_MXL_B_2.f4 an toa_lo_5 TO_LAT_A_2.yq TO_MXL_B_2.g4 an toa_lo_6 TO_LAT_A_3.xq TO_MXL_B_3.f4 an toa_lo_7 TO_LAT_A_3.yq TO_MXL_B_3.g4 ;EM ch B, latch output an emb_lo_0 EM_MXL_B_0.xq EM_MXL_B_0.f2 an emb_lo_1 EM_MXL_B_0.yq EM_MXL_B_0.g2 p 57 an emb_lo_2 EM_MXL_B_1.xq EM_MXL_B_1.f2 an emb_lo_3 EM_MXL_B_1.yq EM_MXL_B_1.g2 an emb_lo_4 EM_MXL_B_2.xq EM_MXL_B_2.f2 an emb_lo_5 EM_MXL_B_2.yq EM_MXL_B_2.g2 an emb_lo_6 EM_MXL_B_3.xq EM_MXL_B_3.f2 an emb_lo_7 EM_MXL_B_3.yq EM_MXL_B_3.g2 ;TO ch B, latch output an tob_lo_0 TO_MXL_B_0.xq TO_MXL_B_0.f2 an tob_lo_1 TO_MXL_B_0.yq TO_MXL_B_0.g2 an tob_lo_2 TO_MXL_B_1.xq TO_MXL_B_1.f2 an tob_lo_3 TO_MXL_B_1.yq TO_MXL_B_1.g2 an tob_lo_4 TO_MXL_B_2.xq TO_MXL_B_2.f2 an tob_lo_5 TO_MXL_B_2.yq TO_MXL_B_2.g2 an tob_lo_6 TO_MXL_B_3.xq TO_MXL_B_3.f2 an tob_lo_7 TO_MXL_B_3.yq TO_MXL_B_3.g2 ;EM mux output an em_mxo_0 EM_MXL_B_0.x E0.o an em_mxo_1 EM_MXL_B_0.y E1.o an em_mxo_2 EM_MXL_B_1.x E2.o an em_mxo_3 EM_MXL_B_1.y E3.o an em_mxo_4 EM_MXL_B_2.x E4.o an em_mxo_5 EM_MXL_B_2.y E5.o an em_mxo_6 EM_MXL_B_3.x E6.o an em_mxo_7 EM_MXL_B_3.y E7.o ;TO mux output an to_mxo_0 TO_MXL_B_0.x T0.o an to_mxo_1 TO_MXL_B_0.y T1.o an to_mxo_2 TO_MXL_B_1.x T2.o an to_mxo_3 TO_MXL_B_1.y T3.o an to_mxo_4 TO_MXL_B_2.x T4.o an to_mxo_5 TO_MXL_B_2.y T5.o an to_mxo_6 TO_MXL_B_3.x T6.o an to_mxo_7 TO_MXL_B_3.y T7.o ----------------------------------------------------------- File GLOB_NET.x ----------------------------------------------------------- an i_input_ck i_bufgp_tl.i bufgp_tl.i ;PGK1 - PGK4 global pins and nets ;an i_diag_ck i_bufgp_tr.i bufgp_tr.i an i_xmit_ck i_bufgp_br.i bufgp_br.i an i_total i_bufgp_bl.i bufgp_bl.i an i_to_we TO__WE_GEN.y bufgs_br.i ;SGK1 - SGK4 global nets an i_em_we EM__WE_GEN.x bufgs_bl.i an i_lat_ck LAT_CK_GEN.y bufgs_tr.i ;an i_lca_oe_bar COMPARE.x bufgs_tl.i ;an i_d_mode i_bufgs_br.i bufgs_br.i ;(pin 51 = DM, global pin) autoroute off an to_we bufgs_br.o an em_we bufgs_bl.o an lat_ck bufgs_tr.o an input_ck bufgp_tl.o p 58 an xmit_ck bufgp_br.o ;an diag_mode bufgs_br.o ;an diag_ck bufgp_tr.o autoroute on ;transmit clock __/~~ ap xmit_ck STATE_01.k STATE_23.k STATE_CTRL.k ;EM buffer write enable (actually, __/~~ is used as register clock) ap em_we EM_XLB_A_0.k EM_XLB_B_0.k ap em_we EM_XLB_A_1.k EM_XLB_B_1.k ap em_we EM_XLB_A_2.k EM_XLB_B_2.k ap em_we EM_XLB_A_3.k EM_XLB_B_3.k ;TO buffer write enable (actually, __/~~ is used as register clock) ap to_we TO_XLB_A_0.k TO_XLB_B_0.k ap to_we TO_XLB_A_1.k TO_XLB_B_1.k ap to_we TO_XLB_A_2.k TO_XLB_B_2.k ap to_we TO_XLB_A_3.k TO_XLB_B_3.k ;latch clocks ( __/~~ is used as register clock) ap lat_ck EM_LAT_A_0.k EM_MXL_B_0.k ap lat_ck EM_LAT_A_1.k EM_MXL_B_1.k ap lat_ck EM_LAT_A_2.k EM_MXL_B_2.k ap lat_ck EM_LAT_A_3.k EM_MXL_B_3.k ap lat_ck TO_LAT_A_0.k TO_MXL_B_0.k ap lat_ck TO_LAT_A_1.k TO_MXL_B_1.k ap lat_ck TO_LAT_A_2.k TO_MXL_B_2.k ap lat_ck TO_LAT_A_3.k TO_MXL_B_3.k ap input_ck LAT_CK_GEN.g3 an latch_bar LA.i2 LAT_CK_GEN.g4 ap input_ck EM__WE_GEN.f3 TO__WE_GEN.g3 autoroute off an total bufgp_bl.o autoroute on ap total EM__WE_GEN.f1 TO__WE_GEN.g1 LAT_CK_GEN.g1 an store_bar ST.i2 EM__WE_GEN.f4 TO__WE_GEN.g4 ;output enable for this LCA ;an lca_oe_bar bufgs_tl.o E0.t E1.t E2.t E3.t E4.t E5.t E6.t E7.t ;ap lca_oe_bar T0.t T1.t T2.t T3.t T4.t T5.t T6.t T7.t ;ap lca_oe_bar SO.o ;output lca_oe_bar on DIAG_O for test only ----------------------------------------------------------- File IN_NETS.x ----------------------------------------------------------- ;*** Channel A inputs *** an cha_in_8 A8.i2 TO_XLB_A_0.f1 ;each LSB is OR'd with MSB p 59 ap cha_in_8 TO_XLB_A_0.g1 ap cha_in_8 TO_XLB_A_1.f1 ap cha_in_8 TO_XLB_A_1.g1 ap cha_in_8 TO_XLB_A_2.f1 ap cha_in_8 TO_XLB_A_2.g1 ap cha_in_8 TO_XLB_A_3.f1 ap cha_in_8 TO_XLB_A_3.g1 ap cha_in_8 EM_XLB_A_0.f1 ap cha_in_8 EM_XLB_A_0.g1 ap cha_in_8 EM_XLB_A_1.f1 ap cha_in_8 EM_XLB_A_1.g1 ap cha_in_8 EM_XLB_A_2.f1 ap cha_in_8 EM_XLB_A_2.g1 ap cha_in_8 EM_XLB_A_3.f1 ap cha_in_8 EM_XLB_A_3.g1 an cha_in_0 A0.i2 TO_XLB_A_0.f3 EM_XLB_A_0.f3 an cha_in_1 A1.i2 TO_XLB_A_0.g3 EM_XLB_A_0.g3 an cha_in_2 A2.i2 TO_XLB_A_1.f3 EM_XLB_A_1.f3 an cha_in_3 A3.i2 TO_XLB_A_1.g3 EM_XLB_A_1.g3 an cha_in_4 A4.i2 TO_XLB_A_2.f3 EM_XLB_A_2.f3 an cha_in_5 A5.i2 TO_XLB_A_2.g3 EM_XLB_A_2.g3 an cha_in_6 A6.i2 TO_XLB_A_3.f3 EM_XLB_A_3.f3 an cha_in_7 A7.i2 TO_XLB_A_3.g3 EM_XLB_A_3.g3 ;*** Channel B inputs *** an chb_in_8 B8.i2 TO_XLB_B_0.f1 ;each LSB is OR'd with MSB ap chb_in_8 TO_XLB_B_0.g1 ap chb_in_8 TO_XLB_B_1.f1 ap chb_in_8 TO_XLB_B_1.g1 ap chb_in_8 TO_XLB_B_2.f1 ap chb_in_8 TO_XLB_B_2.g1 ap chb_in_8 TO_XLB_B_3.f1 ap chb_in_8 TO_XLB_B_3.g1 ap chb_in_8 EM_XLB_B_0.f1 ap chb_in_8 EM_XLB_B_0.g1 ap chb_in_8 EM_XLB_B_1.f1 ap chb_in_8 EM_XLB_B_1.g1 ap chb_in_8 EM_XLB_B_2.f1 ap chb_in_8 EM_XLB_B_2.g1 ap chb_in_8 EM_XLB_B_3.f1 ap chb_in_8 EM_XLB_B_3.g1 an chb_in_0 B0.i2 TO_XLB_B_0.f3 EM_XLB_B_0.f3 an chb_in_1 B1.i2 TO_XLB_B_0.g3 EM_XLB_B_0.g3 an chb_in_2 B2.i2 TO_XLB_B_1.f3 EM_XLB_B_1.f3 an chb_in_3 B3.i2 TO_XLB_B_1.g3 EM_XLB_B_1.g3 an chb_in_4 B4.i2 TO_XLB_B_2.f3 EM_XLB_B_2.f3 an chb_in_5 B5.i2 TO_XLB_B_2.g3 EM_XLB_B_2.g3 an chb_in_6 B6.i2 TO_XLB_B_3.f3 EM_XLB_B_3.f3 an chb_in_7 B7.i2 TO_XLB_B_3.g3 EM_XLB_B_3.g3 p 60 make_prom (for run_00) This UNIX shell script runs XACT programs to create a file suitable for burning an SCP. Execute the file all.x (see above) in XDE. Save the result in e_run.lca. Run the make_prom script file from the shell command line. ----------------------------------------------------------- file make_prom ----------------------------------------------------------- # make bitstream file, -t = tie down unused interconnect makebits -f crc:enable -f donepin:pullup -t e_run.lca # make prom file in Intel format, 4 kbyte PROM, starting at address 0 makeprom -f MCS -s 4 -u 0 e_run.bit p 61 GAL and PROM Text Files Summary DC GAL's DIST1_00.pld 16V8 DC GAL1 for run DIST2_00.pld 22V10 DC GAL2 for run DIST3_00.pld 22V10 DC GAL3 for run DIST4_01.pld 22V10 DC GAL4 for run ERPB GAL's TEG16.pld 16V8 ERPB Fault GAL (U35) for run and automated test TEG22.pld 22V10 ERPB Transmit GAL (U34) for automated test ERPBX_00.pld 22V10 ERPB Transmit GAL (U34) for run Configuration Board GAL CONF.pld 16V8 Configuration Board GAL DC PROM's DIST_00.seq 7C291 DC PROM's (U23 and U26) for run DC GAL's ----------------------------------------------------------- File DIST1_00.PLD ----------------------------------------------------------- DIST1_00.pld: pld file for D0 distributor GAL1 (Setup GAL) |GAL16V8A 2:DS0, |distributor select code from MTG | 3:DS1, | 4:DS2, | 5:DS3, | 6:ALTREG, |selects which of two alt registers should be written | 7:EQUAL, |high if distributor mode = select code from MTG | 8:MTG8, |distributor register select (0 = main, 1 = alt) | 9:MTG9, |distributor strobe | 19:Q19, |flip-flop outputs available for synchronization/deglit | 18:Q18, | 17:O17, | 16:O16, | 15:MAINRCLK, |clock to Main MTG register | 14:ALT0RCLK, |clock to Alt 0 MTG register | 13:ALT1RCLK, |clock to Alt 1 MTG register | 12:XDISTRIG, |A high-to-low transition triggers the transmit-disable |Clock: CLK1US | |Value: "DIST Setup GAL" |Type: "GAL16V8A" | |Title: "Distributor Card Setup GAL" |Title: "February 14, 1994" |Signature: "DIST1_00" | | Q19 = CLK1US // MTG9 | Q18 = CLK1US // Q19 | O17 = (DS0 & DS1 & DS2 & DS3) # EQUAL |intermediate signal (distributor i | O16 = 0 | XDISTRIG = CLK1US // Q18 # Q19 | MAINRCLK = CLK1US // Q18 # Q19' # MTG8 | ALT0RCLK = CLK1US // Q18 # Q19' # MTG8' # O17' # ALTREG | ALT1RCLK = CLK1US // Q18 # Q19' # MTG8' # O17' # ALTREG' ----------------------------------------------------------- File DIST2_00.PLD ----------------------------------------------------------- DIST2_00.pld: pld file for D0 distributor GAL2 (Transmit/Configure Source Selection |GAL22V10 2:MASTERb, | 3:REMXCLK, | 4:REMPROGb, | 5:REMCCLK, | 6:REMDIN, | 7:LOCXCLK, | 8:LOCPROGb, | 9:LOCCCLK, | 10:LOCDIN, | 11:USELOCX, | 13:USELOCC, 23: | 22:OUTXCLK, | 21:OUTPROGb, | 20:OUTCCLK, | 19:OUTDIN, | 18:INUXCLK, | 17:INUPROGb, | 16:INUCCLK, | 15:INUDIN 14: | |Value: "DIST Selection GAL" |Type: "GAL22V10" | |Title: "Distributor Card Selection GAL" |Title: "February 14, 1994" | |Signature: "DIST2_00" Signals output to next distributor: |OUTXCLK = ( MASTERb' & LOCXCLK ) # ( MASTERb & REMXCLK ) |transmit clock |OUTPROGb = ( MASTERb' & LOCPROGb ) # ( MASTERb & REMPROGb ) |PROG\ (to LCA's) |OUTCCLK = ( MASTERb' & LOCCCLK ) # ( MASTERb & REMCCLK ) |CCLK (to LCA's) |OUTDIN = ( MASTERb' & LOCDIN ) # ( MASTERb & REMDIN ) |DIN (to LCA's) Signals in use on this distributor: |INUXCLK = ( (USELOCX # MASTERb') & LOCXCLK ) # ( (USELOCX # MASTERb')' & REMXCLK |INUPROGb = ( (USELOCC # MASTERb') & LOCPROGb ) # ( (USELOCC # MASTERb')' & REMPROGb |INUCCLK = ( (USELOCC # MASTERb') & LOCCCLK ) # ( (USELOCC # MASTERb')' & REMCCLK |INUDIN = ( (USELOCC # MASTERb') & LOCDIN ) # ( (USELOCC # MASTERb')' & REMDIN |Vectors: | { | Test MASTERb, REMXCLK, REMPROGb, REMCCLK, REMDIN | Test LOCXCLK, LOCPROGb, LOCCCLK, LOCDIN, USELOCX, USELOCC | End } ----------------------------------------------------------- File DIST3_00.PLD ----------------------------------------------------------- DIST3_00.pld: pld file for D0 distributor GAL3 (LCA Configuration GAL) |GAL22V10 2:ONESHOT, | 3:USEMTG, | 4:USEROM1, | 5:ROMDATA0, | 6:ROMCEO0b, | 7:ROMDATA1, | 8:ROMCEO1b, | 9:MTGDIN, | 10:MTGCCLK, | 11:RACKCONF, | 13:GLOBCONF, | 23:synca, | 22:q22, | 21:ROMCLK, | 20:ROMOEb, | 19:LOCPROGb, | 18:LOCCCLK, | 17:LOCDIN, | 16:romdin, | 15:DINEN, | 14:TRIGAb, |Clock: CLK2US | |Value: "DIST LCA Configuration GAL" |Type: "GAL22V10" | |Title: "Distributor Card LCA Configuration GAL" |Title: "February 15, 1994" | |Signature: "DIST3_00" Signals derived directly from configuration one-shot: | synca = CLK2US // ONESHOT | ROMOEb = CLK2US // synca | LOCPROGb = CLK2US // !( synca & !ROMOEb ) Note on USEROM1: what was originally intended to be SCP1 (ROM 0) was inadvertently assigned the reference SCP2 and vice versa. To fix this, (and keep the setup switch information on the silkscreen accurate), USEROM1 has been complemented in the equations below. ROMCLK and CCLK generation: | Tceobmux = ( USEROM1' * ROMCEO1b ) # ( USEROM1 * ROMCEO0b ) |mux: CEOb from ROM | T1 = (!ROMCLK) # ROMOEb # (!Tceobmux) | ROMCLK = CLK2US // T1 | LOCCCLK = ( USEMTG * MTGCCLK ) # ( USEMTG' * ROMCLK ) |mux: CCLK from MTG DIN generation: | Trommux = ( USEROM1' * ROMDATA1 ) # ( USEROM1 * ROMDATA0 ) |mux: DIN from ROM1 | romdin = CLK2US // Trommux # Tceobmux' |DIN from ROM, | Tdinmux = ( USEMTG * MTGDIN ) # ( USEMTG' * romdin ) |mux: DIN from MTG | LOCDIN = Tdinmux * DINEN |force DIN Configuration trigger: | q22 = CLK2US // RACKCONF ## GLOBCONF |if RACKCONF ch | TRIGAb = CLK2US // ( ( RACKCONF ## GLOBCONF ) ## q22 )' |if q22 changes, TRIG |Vectors: | { | End } ----------------------------------------------------------- File DIST4_01.PLD ----------------------------------------------------------- DIST4_01.pld: pld file for D0 distributor GAL4 (Transmit Sequencer Control GAL) rev 01: X_STB is shortened by gating with XMIT_CLK |GAL22V10 2:XMIT_TRIG, | 3:XDIS_PULSE, 4:UDC_0b, 5:SPX_IN, | 6:DIAG_DATA, 7:F_DISABLE 8:F_DISABLE | 9:X_DISABLE, | 10:SQ_CLK_MASK, | 11:SQ_FBACK0, 13:SQ_FBACK1, | 23:sync_trig, | 22:q22, | 21:ENP, | 20:LOADb, | 19:CLRb, | 18:DIAG_DO, | 17:XMIT_OUT, | XMIT_OUT = XMIT_CLK, see note 1 below | 16:FSR_CLRb, | 15:X_STB, | see note 1 below | 14:DEL_XCLK, | delayed XMIT_CLK, see note 1 below |Clock: XMIT_CLK | |Value: "DIST Sequencer Control GAL" |Type: "GAL22V10" | |Title: "Distributor Card Transmit Sequencer Control GAL" |Title: "March 2, 1994" | Signature: "DIST4_01" !!use this line to have signature | sync_trig = XMIT_CLK // XMIT_TRIG | q22 = 0 | ENP = 1 | LOADb = 1 | CLRb = ( ( sync_trig & XMIT_TRIG ) # SQ_FBACK0' ) & X_DISABLE' & XDIS_PUL | DIAG_DO = DIAG_DATA | XMIT_OUT = XMIT_CLK | FSR_CLRb = 0 |always clear fault shift register X_STB = DEL_XCLK & SQ_CLK_MASK' !!use this line for full STB width | X_STB = DEL_XCLK & SQ_CLK_MASK' & XMIT_CLK |rev 01 |Vectors: | { test XMIT_TRIG, test XDIS_PULSE test DIAG_DATA test X_DISABLE test SQ_CLK_MASK test SQ_FBACK0 test DEL_XCLK | End } ERPB GAL's ----------------------------------------------------------- File TEG16.PLD ----------------------------------------------------------- |GAL16V8A 2:GI0, | 3:HDC, | 4:PWRUPb, | 5:TOKI, | 6:DDCI0, | 7:DDCI1, | 8:UDCI0, | 9:UDCI1, | 19:TOXGAL, | 18:REDb, | 17:YELLOWb, | 16:GREENb, | 15:TOKO, | 14:TP14, |pin 14 and pin 13 are not connected | 13:TP13, | 12:DFAULT, |Clock: FAULTCLK | |Value: "Fault GAL" |Type: "GAL16V8A" | |Title: "Prototype Test Version of Fault GAL" |Title: "November 30, 1993" | |Signature: "Fault 00" | TOXGAL = FAULTCLK | REDb = !GI0 | YELLOWb = !HDC | GREENb = PWRUPb | TOKO = TOKI | TP14 = DDCI0 | TP13 = DDCI1 | DFAULT = UDCI0 |Vectors: | { | Display (REDb)c," ", (YELLOWb)c," ", (GREENb)c," ", (TOKO)c," ", \ | (TP14)c," ", (TP13)c," ", (DFAULT)c | Test GI0, HDC, PWRUPb, TOKI, DDCI0, DDCI1, UDCI0, UDCI1, FAULTCLK | End } ----------------------------------------------------------- File TEG22.PLD ----------------------------------------------------------- |GAL22V10 2:GI6, | 3:GI5, | 4:GI4, | 5:GI3, | 6:GI2, | 7:GI1, | 8:DDCI0, | 9:DDCI1, | 10:UDCI0, | 11:UDCI1, | 13:FRFGAL, | 23:GO0, | 22:GO1, | 21:GO2, | 20:GO3, | 19:DDCO0, | 18:DDCO1, | 17:UDCO0, | 16:UDCO1, | 15:ROEO, | 14:BUFOEb, |Clock: XMITCLK | |Value: "Transmit GAL" |Type: "GAL22V10" | |Title: "Prototype Test Version of Transmit GAL" |Title: "November 30, 1993" | |Signature: "Xmit 00" |GO0 = DDCI0 |GO1 = DDCI1 |GO2 = UDCI0 |GO3 = UDCI1 |DDCO0 = DDCI0 |DDCO1 = DDCI1 |UDCO0 = UDCI0 |UDCO1 = UDCI1 |ROEO = DDCI0 |ROEO goes to ERPB below |BUFOEb = DDCI1 |BUFOEb controls LCA buffer |Vectors: | { | Display (GO0)c," ", (GO1)c," ", (GO2)c," ", (GO3)c," ", (DDCO0)c, \ | " ",(DDCO1)c," ", (UDCO0)c," ", (UDCO1)c," ", (ROEO)c," ", (BUFOEb)c | Test DDCI0, DDCI1, UDCI0, UDCI1 | End } ----------------------------------------------------------- File ERPBX_00.PLD ----------------------------------------------------------- ERPBX_00.pld: pld file for D0 ERPB Transmit GAL (U34) |GAL22V10 2:GI_6, | inputs from LCA #1 | 3:GI_5, | 4:GI_4, | 5:GI_3, | 6:GI_2, | 7:GI_1, | 8:DDCI_0, | down daisy chain inputs | 9:DDCI_1, | 10:UDCI_0, | up daisy chain inputs | 11:UDCI_1, | 13:FAULT_IN, | input from fault GALs | 23:GO_0, | outputs to all GALs | 22:GO_1, | 21:GO_2, | 20:GO_3, | 19:DDCO_0, | down daisy chain outputs | 18:DDCO_1, | 17:UDCO_0, | up daisy chain outputs | 16:UDCO_1, | 15:ROEO, | register ouput enable to ERPB below (active high) | 14:BUF_OEb, | LCA buffer output enable (active low) |Clock: XMIT_CLK | |Value: "DIST Selection GAL" |Type: "GAL22V10" | |Title: "ERPB Transmit GAL" |Title: "February 25, 1994" | |Signature: "ERPBX_00" |GO_0 = DDCI_0 |GO_1 = DDCI_1 |GO_2 = XMIT_CLK // DDCI_0 |GO_3 = XMIT_CLK // DDCI_1 |DDCO_0 = XMIT_CLK // GI_3 |DDCO_1 = GI_3 |UDCO_0 = 0 |UDCO_1 = 1 |ROEO = GI_2 |BUF_OEb = GI_1 |Vectors: | { | Ripple on | Display (GO_0)c," ", (GO_1)c," ", (GO_2)c," ", (GO_3)c," ", \ | (DDCO_0)c," ", (DDCO_1)c," ", (UDCO_0)c," ", (UDCO_1)c," ", (ROEO)c," ", (BUF_ | Clear DDCI_0 | Clear DDCI_1 | Clear GI_3 | Clear GI_2 | Clear GI_1 B D D U U U D D D D F G G G G C C C C R _ O O O O O O O O O O _ _ _ _ _ _ _ _ E E +0 1 2 3 0 1 0 1 O b -- -- -- -- -- -- -- -- -- -- | Test XMIT_CLK = 2(0,1) | Set DDCI_0 | Test XMIT_CLK = 2(0,1) | Set DDCI_1 | Test XMIT_CLK = 2(0,1) | Set GI_3 | Test XMIT_CLK = 2(0,1) | Set GI_2 | Test XMIT_CLK = 2(0,1) | Set GI_1 | Test XMIT_CLK = 2(0,1) | End } Configuration Board GAL ----------------------------------------------------------- File CONF.PLD ----------------------------------------------------------- |GAL16V8A 2:ONESHOTA, | 3:ONESHOTB, | 4:ROMDATA, | 5:ROMCEOb, | 6:XMITSEL, | 7:-, | 8:-, | 9:C16MHZ, | 19:TRIGB, | 18:SYNCA, | 17:ROMCLK, | 16:ROMOEb, | 15:XMITCLK, | 14:PROGb, | 13:CCLK, | 12:DIN, |Clock: CONFCLK | |Value: "Configuration GAL" |Type: "GAL16V8A" | |Title: "ERPB LCA Configuration Board" |Title: "November 18, 1993" | |Signature: "etest 00" | TRIGB = 0 | XMITCLK = XMITSEL & C16MHZ | T1 = !ROMCLK # ROMOEb # !ROMCEOb | SYNCA = CONFCLK // ONESHOTA | ROMCLK = CONFCLK // T1 | CCLK = CONFCLK // T1 | ROMOEb = CONFCLK // SYNCA | PROGb = CONFCLK // !( SYNCA & !ROMOEb ) | DIN = CONFCLK // ROMDATA & ROMCEOb |after configuration, DIN = 0 |Vectors: | { | Ripple on | Display (CONFCLK)c," ", (ONESHOTA)c," ", (ROMDATA)c," ", (ROMCEOb)c," ", \ | (SYNCA)c," ", (ROMOEb)c," ", (ROMCLK)c," ", (PROGb)c," ", (DIN)c," ", (CCLK)c | Clear ONESHOTA | Clear ONESHOTB | Clear ROMDATA | Clear ROMCEOb | Clear XMITSEL | Clear C16MHZ O C N R R O E O O R R N S M M S O O P F H D C Y M M R C C O A E N O C O D C L T T O C E L G I L K A A * A * K * N K -- -- -- -- -- -- -- -- -- -- | Test CONFCLK = 2(0,1) | Set ONESHOTA | Test CONFCLK = 2(0,1) | Set ROMCEOb |it does not really work this way | Clear ONESHOTA | Test CONFCLK = 1(0,1) | Test ROMDATA, CONFCLK = 3(10b, 11b, 00b, 01b, 00b, 01b, 10b, 11b) | Clear ROMCEOb | Test CONFCLK = 3(0,1) | End } DC PROM's The DIST_00.seq file describes the PROM bits for the DC transmit sequencer PROM's (U2 The program SEQ.exe is used to convert a .seq file into a BIT file. An example .seq f ; File EXAMPLE.seq CONVERT { ADDRESS 0, 255 ; ROM address + 1 000000000000000011111111111111112222222222222222 ; 0123456789abcdef0123456789abcdef0123456789abcdef Q0: ADC_LR: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> Q1: DAC_LR: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> Q2: ADC_SCLK: ~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__R48,1 Q3: DAC_BICK: ~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__~~__R48,1 } TO EXAM_A.rom CONVERT { ADDRESS 0, 255 Q0: ADC_OE_S0: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> Q1: ADC_OE_S1: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> Q2: ADC_OE_S2: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> Q3: ADC_OE_EN: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>>> } TO EXAM_B.rom A semicolon indicates the beginning of a comment. The comment ends at the end of the CONVERT initializes the ROM buffer to 0FFh. It also sets the address limits to their values (0, 255). ADDRESS specifies the address limits (in decimal). Exceeding the address limits caus Q0 - Q7 specify which bit in the ROM is being operated upon. ~ = 1, _ = 0 Rn,m is used to repeat the preceding n bits in the ROM buffer m times. > is used to repeat the preceding bit in the ROM buffer until the upper address limit the end of the line are ignored. TO marks the end of the block and specifies the destination file. The file name may must not be followed by any extraneous characters. (Comments and other ignored chara Characters between two colons are ignored. The two colons must be on the same line. ignored. A single line may contain at most one of the following, which must appear at the begi permitted): CONVERT ADDRESS Q TO IHEX.exe must be run to convert the destination file to Intel hex format. ----------------------------------------------------------- File DIST_00.SEQ ----------------------------------------------------------- ; This file is DIST_00.seq created 02-16-94 revised 03-02-94 ; Note: a bug in SEQ.C causes problems if a ; comment is not the only thing on the l ; so use a pair of colons around comments after non-comment characters. CONVERT { ADDRESS 0, 255 ; ROM address 0000000000000000111111111111111122222222222222223333333333333 ; 0123456789abcdef0123456789abcdef0123456789abcdef0123456789abc Q0: SQ_FAULT_CLK: ~> Q1: SQ_FAULT_TOK: ~> Q2: SQ_FSR_0_S0: _> :lo = hold, hi = shift: Q3: SQ_FSR_1_S0: _> Q4: SQ_FSR_0_OE\: ~> Q5: SQ_FSR_1_OE\: ~> Q6: spare: ~> Q7: spare: ~> } TO DU23_00.bit CONVERT { ADDRESS 0, 255 ; ROM address 0000000000000000111111111111111122222222222222223333333333333 ; 0123456789abcdef0123456789abcdef0123456789abcdef0123456789abc Q0: SQ_DDC0: _~~~~~~~~~~~~~~~~~~ R16,7 __> :Down Daisy Chain flag goes hi Q3: SQ_CLK_MASK: ~~~________________ R16,7 ~~> :Clock Mask is low for 128 clo Q4: SQ_FBACK0: ~__________________ R16,7 ~~> :Feedback keeps sequencer runn Q1: SQ_DDC1: ~> :not used: Q2: SQ_ERPB_OE: ~> :ERPB's output is always enabled: Q5: SQ_FBACK1: ~> :not used: Q6: SQ_DST_1: ~> :not used: Q7: SQ_SPARE_OUT: ~> :not used: } TO DU26_00.bit Timing Diagrams CONF_00.tim Trigger of LCA configuration by the MTG RECVA_00.tim Reception of CTFE data by the ERPB XMITB_01.tim Beginning of ERPB to CRC data transmission XMITE_01.tim End of ERPB to CRC data transmission CONB_00.tim LCA configuration by the configuration board