Summary of the Ironics Cards and Their P2 Paddle Cards ---------------------------------------------------------- Rev. 19-MAY-1995 Arrangement of the Ironics Cards in the L1.5 Cal Trig Crate Slot Ironics Card, Its Function and Its Base Address ---- ----------------------------------------------------- 2 Term Answer Base Adrs is $F010 3 Term Select Base Adrs is $F020 4 Readout Control Base Adrs is $F040 5 Path Select Base Adrs is $F080 Term Answer (Terms returned to M103) ------------------------------------ Base Address is $F010. The various port on this Ironics card are used as follows: Port Function ------ --------------------------------------------- 1 Not Used 2 Not Used 3 Not Used 4 All bits are Output. This is the mask of L1.5 CT Answers to be returned to the L1.5 Framework. A bit set to "1" in this mask corresponds to a Positive Answer for that L1.5 CT Term. Bit #i is mapped to L1.5 CT Term #i. 5 All bits are Output. This is the mask of L1.5 CT Dones to be returned to the L1.5 Framework. A bit set to "1" in this mask corresponds to a L1.5 CT Term which has been evaluated (i.e. a L1.5 CT Term for which the Answer is valid). Bit #i is mapped to L1.5 CT Term #i. All bits must be set to "0" at some time before the L1.5 Cal Trig responds to the L1.5 Framework. 6 Not Used Term Select ----------- Base Address is $F020. The various port on this Ironics card are used as follows: Port Function ------ --------------------------------------------- 1 Not Used 2 All bits are Output Ironics bits 0:7 are address lines 0:7. 3 All bits are Output Ironics bits 0:7 are address lines 8:15. 4 All bits are I/O Ironics bits 0:7 are memory data bits 0:7. 5 All bits are Output Ironics bit 0 controls the Mux_Sel. Setting this bit to 1 selects Ironics Programming Set a 0 for normal operation. Ironics bit 1 controls the /WE signal to the SRAM's. Normal 1 pulse to 0 to write Ironics bit 2 controls the /OE signal to the SRAM's. Normal 0 i.e. reading the SRAM's set to 1 when writing. Ironics bit 3 is used to generate a clock to the '399 latch during Ironics Programming. Normally 0, pulse to 1 to clock the latch. Ironics bits 4:7 are not used. 6 Not Used Readout Control --------------- Base Address is $F040. The various port on this Ironics card are used as follows: Port Function ------ --------------------------------------------- 1 Not Used 2 All bits are Outputs. Ironics bit 0 is the Slave Ready signal to the VBD SRDY input. 3 All bits are Inputs. Ironics bit 0 is high if Readout is required. Ironics bit 1 is high if NO readout is required (e.g. L15 reject). Ironics bit 4 indicates the state of of the VBD DONE signal. 4 All bits are Outputs. Pulsing Ironics bit 0 high clears the Readout Control paddle board. Setting Ironics bit 1 high or low sets the R.C. Front-End Busy high or low. Ironics bit 4 controls the #1 MVME214 high-->enables VME low-->enables VSB Ironics bit 5 controls the #2 MVME214 high-->enables VME low-->enables VSB 5 All bits are Inputs. They read the TAS Number bits 8:15 6 All bits are Inputs. They read the TAS Number bits 0:7 Path Select ----------- Base Address is $F080. The various port on this Ironics card are used as follows: Port Function ------ --------------------------------------------- 1 The LSBit of Port #1 is used to control the ExtEnb signal for L15CT MTG Channel #7. This signal controls when the MTG can send Transmit_Trigger to the ERPB cards. 2 Not Used 3 All bits are Outputs. Bits 0:6 are not used. Bit 7 when pulsed high clears the 16RA8 Path Select PAL. During the time that Bit 7 is pulsed high the L15 Cal Trig is forced Front-End_Busy. 4 All bits are Inputs. They read the "Path" output signals from the 16RA8 Path Select PAL. Bit 0 when set means "L15 cycle is running and this crate is required to calculate at least one Term". Bit 1 when set means "L15 cycle is running". Bit 2 when set means "Level 1 trigger fired and this crate is required to calculate at least one Term". Bit 3 when set means "Level 1 trigger fired". Bits 4:7 are not used. 5 All bits are Inputs. Bit 0 is latched Level 0 Slow Vertex bit 8 Bit 7 is latched Level 0 Slow Vertex bit 15 6 All bits are Inputs. Bit 0 is latched Level 0 Slow Vertex bit 0 Bit 7 is latched Level 0 Slow Vertex bit 7