PATH_SELECT_P2_CARD_DESCRIPTION.TXT =================================== Last Update 19-MAY-1995 This file describes the Path Select P2 paddle board. The Path Select P2 paddle board has three functions: 1) it performs the Path Select function for the Level 1.5 Calorimeter Trigger 2) it provides the Engine Control contribution to the Front End Busy signal 3) it performs differential ECL to TTL conversion and latching for the Level 0 Slow Vertex 16 bit vector. There are 4 connectors on the card. Their usage is as follows: J1: Is a 34-pin universal header with latches which brings onto the card the 16 bit Slow Vertex vector from the Level 0 Trigger as differential ECL. J2: Is the 96-pin DIN VME P2 connector which allows communication with the 68K Services computer via an Ironics IV-1623 Parallel I/O Board. J3: Is a 34-pin universal header with latches which provides access to the paddle board-to-paddle board bus as mixed ECL/TTL I/O. J4: This connector provides 6 TTL level buffered test points for monitoring a variety of signals on the Path Select P2. Functions: ========== 1) Path Select -------------- When an event occurs, the Path Select receives the Buffered Hold transfer signal from the Readout Control paddle board. This generates a high "Something Happened" signal ("Something Happened" indicates that the Level 1 Frame Work has begun the TAS Protocol, ie. one or more Level 1 Specific Triggers have fired). If at least one specific trigger requires Level 1.5 Calorimeter Trigger confirmation the Term Select paddle board sends the >=1 Term Needs to be Evaluated (GE1_TNBE) signal over the paddle board-to-paddle board bus. The GE1_TNBE is latched on the Path Select P2 and driven off the card as "That's Me." TTL copies of "That's Me" and "Something Happened" are sent to the 68K Services computer via Ironics I/O ports and a differential ECL copy of "That's Me" is sent to the ERPB MTG to initiate the Level 1 to Level 1.5 data transfer. 2) Engine Control Front End Busy -------------------------------- At the assertion of "Something Happened," the Path Select P2 asserts the Engine Control Front End Busy signal (EC FEBz). EC FEBz is driven to the Readout Control paddle board and mixed with other sources of Front End Busy signal and then sent to the Level 1 Frame Work to suspend further data acquisition until the event in question is resolved. Once activated, the EC FEBz remains high until after the Path Select is reset 3) Level 0 Slow Vertex ---------------------- The Level 0 Slow Vertex inputs are 16 differential ECL bits which are converted to TTL and latched. They come in on J1 on a 34 conductor cable and are terminated by 110 Ohm resistor packs. Conversion from ECL-->TTL is done by 4 MC10125's. The TTL signals are then latched by 2 '574 rising edge triggered flip-flops (Del Hold Trans) and made available to the Ironics card. Test Points ----------- The numbering for the test points starts from the top of the PS-P2 and progresses downward with even numbered pins (bottom row) connected to ground. The current arrangement of signals to the test point buffers are as follows (this is subject to change): Signal Name Type Source Connector ---------------------------------------------------------------------- "That's Me" TTL PAL pin 17 J4-1 Ground GND ---- J4-2 Delayed Hold Trans TTL PAL pin 4 J4-3 Ground GND ---- J4-4 GE1_TNBE TTL PAL pin 3 J4-5 Ground GND ---- J4-6 Buff'd Hold Trans TTL U11 pin 11 J4-7 Ground GND ---- J4-8 "Something Happened"TTL PAL pin 16 J4-9 Ground GND ---- J4-10 Currently Not Used --- ---- J4-11 Ground GND ---- J4-12 Logic and I/O ============= Inputs ------ Signal Name Type Source Connector ---------------------------------------------------------------------- L15 FW Cyc Und* Dif ECL L15 FW J3-7 / J3-8 inverting GE1_TNBE TTL TS-P2PB J3-33 Delayed Hold Trans TTL RC-P2PB J3-31 Reset PS-P2PB TTL Ironics J2-A25 port 3 bit 7 *-L15 FW Cyc Und is currently not in use Logic for Path Select and Engine Control Front End Busy ------------------------------------------------------- In order to guarantee the latching of inputs happens after the Term Select P2 has provided it's outputs, a series of Bel Fuse delay lines (type 0447-0100-02) are used. The rising edge of Buff'd Hold Trans delayed by 300 nanoseconds will be used to latch the data as Delayed Hold Transfer. In the 16RA8 PAL, the rising edge of Delayed Hold Transfer latches the the "Something Happened" output high (the input for "Something Happened" is always high and therefore only the clock is needed). If the GE1_TNBE from the Term Select paddle board is asserted, the 16RA8 PAL latches it as "That's Me," also at the rising edge of Delayed Hold Transfer. The "Something Happened" PAL output is ORed with the Reset Path Select P2 Card from the 68K Services computer and then driven off card as Engine Control Front End Busy. Possible future modification: Since "That's Me" and "Something Happened" may or may not reach a steady state at the same time, they are currently read twice: first to detect "Something Happened" and then to read the level of "That's Me." A possible modification would be to put a delay in the "Something Happened" output so that when "Something Happened" is asserted the contemporary state of "That's Me" would be the correct one. Outputs ------- The PAL sends "That's ME" and "Something Happened" (and two currently unused outputs) to the Ironics I/O port 4. Signal Name Type Destination Connector --------------------------------------------------------------------------- "That's Me" TTL Ironics Port 4 bit 2 J2-C22 "Something Happened"TTL Ironics Port 4 bit 3 J2-C21 EC FEBz TTL RC-P2PB J3-29 "That's Me" ECL L15CT MTG Ch#8 ExtBit J3-11/J3-12 "ExtEnb MTG Ch#7" ECL L15CT MTG Ch#7 ExtEnb J3-15/J3-16 J1: PS-P2PB 34 pin Level 0 Slow Vertex Connector ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 Level 0 Slow Vertex bit 0 Noninv SV0NI 2 Level 0 Slow Vertex bit 0 Inv SV0I 3 Level 0 Slow Vertex bit 1 Noninv SV1NI 4 Level 0 Slow Vertex bit 1 Inv SV1I 5 Level 0 Slow Vertex bit 2 Noninv SV2NI 6 Level 0 Slow Vertex bit 2 Inv SV2I 7 Level 0 Slow Vertex bit 3 Noninv SV3NI 8 Level 0 Slow Vertex bit 3 Inv SV3I 9 Level 0 Slow Vertex bit 4 Noninv SV4NI 10 Level 0 Slow Vertex bit 4 Inv SV4I 11 Level 0 Slow Vertex bit 5 Noninv SV5NI 12 Level 0 Slow Vertex bit 5 Inv SV5I 13 Level 0 Slow Vertex bit 6 Noninv SV6NI 14 Level 0 Slow Vertex bit 6 Inv SV6I 15 Level 0 Slow Vertex bit 7 Noninv SV7NI 16 Level 0 Slow Vertex bit 7 Inv SV7I 17 Level 0 Slow Vertex bit 8 Noninv SV8NI 18 Level 0 Slow Vertex bit 8 Inv SV8I 19 Level 0 Slow Vertex bit 9 Noninv SV9NI 20 Level 0 Slow Vertex bit 9 Inv SV9I 21 Level 0 Slow Vertex bit 10 Noninv SV10NI 22 Level 0 Slow Vertex bit 10 Inv SV10I 23 Level 0 Slow Vertex bit 11 Noninv SV11NI 24 Level 0 Slow Vertex bit 11 Inv SV11I 25 Level 0 Slow Vertex bit 12 Noninv SV12NI 26 Level 0 Slow Vertex bit 12 Inv SV12I 27 Level 0 Slow Vertex bit 13 Noninv SV13NI 28 Level 0 Slow Vertex bit 13 Inv SV13I 29 Level 0 Slow Vertex bit 14 Noninv SV14NI 30 Level 0 Slow Vertex bit 14 Inv SV14I 31 Level 0 Slow Vertex bit 15 Noninv SV15NI 32 Level 0 Slow Vertex bit 15 Inv SV15I 33 Not Used ----- 34 Not Used ----- J2: PS-P2PB 96 pin DIN Ironics Connector ----------------------------------------------------------------- pin Signal Mnemonic Port ----------------------------------------------------------------- A 1 +5.0 V VCC ---- A 2 ExtEnb to TTL->ECL -> L15CT MTG Ch#7 ----- 10 A 3 Not Used ----- 11 A 4 Not Used ----- 12 A 5 Not Used ----- 13 A 6 Not Used ----- 14 A 7 Not Used ----- 15 A 8 Not Used ----- 16 A 9 Not Used ----- 17 A 10 Not Used ----- 20 A 11 Not Used ----- 21 A 12 Not Used ----- 22 A 13 Not Used ----- 23 A 14 Not Used ----- 24 A 15 Not Used ----- 25 A 16 Not Used ----- 26 A 17 Not Used ----- 27 A 18 Not Used ----- 30 A 19 Not Used ----- 31 A 20 Not Used ----- 32 A 21 Not Used ----- 33 A 22 Not Used ----- 34 A 23 Not Used ----- 35 A 24 Not Used ----- 36 A 25 Reset Path Select Card RESPS 37 A 26 Not Used ----- ---- A 27 Not Used ----- ---- A 28 Not Used ----- ---- A 29 Not Used ----- ---- A 30 Not Used ----- ---- A 31 Not Used ----- ---- A 32 Not Used ----- ---- B 1 +5.0 V VCC ---- B 2 Ground GND ---- B 3 Not Used ----- ---- B 4 Not Used ----- ---- B 5 Not Used ----- ---- B 6 Not Used ----- ---- B 7 Not Used ----- ---- B 8 Not Used ----- ---- B 9 Not Used ----- ---- B 10 Not Used ----- ---- B 11 Not Used ----- ---- B 12 Ground GND ---- B 13 +5.0 V VCC ---- B 14 Not Used ----- ---- B 15 Not Used ----- ---- B 16 Not Used ----- ---- B 17 Not Used ----- ---- B 18 Not Used ----- ---- B 19 Not Used ----- ---- B 20 Not Used ----- ---- B 21 Not Used ----- ---- B 22 Ground GND ---- B 23 Not Used ----- ---- B 24 Not Used ----- ---- B 25 Not Used ----- ---- B 26 Not Used ----- ---- B 27 Not Used ----- ---- B 28 Not Used ----- ---- B 29 Not Used ----- ---- B 30 Not Used ----- ---- B 31 Ground GND ---- B 32 +5.0 V VCC ---- C 1 Latched Slow Vertex bit 7 LSV7 67 C 2 Latched Slow Vertex bit 6 LSV6 66 C 3 Latched Slow Vertex bit 5 LSV5 65 C 4 Latched Slow Vertex bit 4 LSV4 64 C 5 Latched Slow Vertex bit 3 LSV3 63 C 6 Latched Slow Vertex bit 2 LSV2 62 C 7 Latched Slow Vertex bit 1 LSV1 61 C 8 Latched Slow Vertex bit 0 LSV0 60 C 9 Latched Slow Vertex bit 15 LSV15 57 C 10 Latched Slow Vertex bit 14 LSV14 56 C 11 Latched Slow Vertex bit 13 LSV13 55 C 12 Latched Slow Vertex bit 12 LSV12 54 C 13 Latched Slow Vertex bit 11 LSV11 53 C 14 Latched Slow Vertex bit 10 LSV10 52 C 15 Latched Slow Vertex bit 9 LSV9 51 C 16 Latched Slow Vertex bit 8 LSV8 50 C 17 Not Used ----- 47 C 18 Not Used ----- 46 C 19 Not Used ----- 45 C 20 Not Used ----- 44 C 21 "Something Happened" STNGHP 43 C 22 "That's Me" THATME 42 C 23 PAL pin 18 PSPAL18 41 C 24 PAL pin 19 PSPAL19 40 C 25 +5.0 V VCC ---- C 26 Not Used ----- ---- C 27 Not Used ----- ---- C 28 Not Used ----- ---- C 29 Not Used ----- ---- C 30 Not Used ----- ---- C 31 Not Used ----- ---- C 32 Not Used ----- ---- J3: PS-P2PB 34 pin Board to Board Bus Connector ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 -5.2 V VEE 2 -5.2 V VEE 3 -5.2 V VEE 4 -5.2 V VEE 5 Not Used ----- 6 Not Used ----- 7 L1.5 FW Cycle Underway-Noninv L15FWCYN 8 L1.5 FW Cycle Underway-Invert L15FWCYI 9 Not Used ----- 10 Not Used ----- 11 "That's Me" ECL-Noninv TMECLNIN 12 "That's Me" ECL-Invert TMECLINV 13 Not Used ----- 14 Not Used ----- 15 "ExtEnb to L15CT MTG Ch#7" ECL non ----- 16 "ExtEnb to L15CT MTG Ch#7" ECL inv ----- 17 Not Used ----- 18 Not Used ----- 19 Not Used ----- 20 Not Used ----- 21 Not Used ----- 22 Not Used ----- 23 Not Used ----- 24 Not Used ----- 25 Not Used ----- 26 Not Used ----- 27 Not Used ----- 28 Ground GND 29 Eng Cont Front End Busy ECFEBz 30 Ground GND 31 Buffered Hold Transfer BUFHT 32 Ground GND 33 >= 1 Term Needs to be Evaluated GE1_TNBE 34 Ground GND J4: PS-P2PB 12 pin Test Point Connector ----------------------------------------------------------- pin Signal (Current Assignment) Mnemonic ----------------------------------------------------------- 1 Test Point 1 ("That's Me") TP1 2 Ground GND 3 Test Point 2 (Del Hold Trans) TP2 4 Ground GND 5 Test Point 3 (GE1_TNBE) TP3 6 Ground GND 7 Test Point 4 (Hold Trans) TP4 8 Ground GND 9 Test Point 5 ("Something Happened") TP5 10 Ground GND 11 Test Point 6 (Currently Not Used) TP6 12 Ground GND Modifications _____________ On 17-MAY-1995 the ExtEnb to L15CT MTG Ch#7 was added to this card. This starts as Path Select Ironics Port #1 LSBit which arrives on this P2 Paddle card via pin A2. This signal then goes to U13 pin #7 i.e. the TTL input to a 10H124. The outputs from this section of U13 are pins #1 and #3. These outputs go to 510 Ohm pull downs to -5.2V and then to J3 pins 15 and 16. This signal goes to ExtEnb for Ch#7 on the L15CT MTG and is used to control when the L15CT MTG can send Transmit Trigger to the ERPB's.