Level 1.5 CalTrig Readout Control P2 Paddle Board Description --------------------------------------------------------------- First Release 27-SEP-1993 Latest Rev. 24-AUG-1994 This is a brief technical description of the hardware and logic involved in the RC-P2PB. Additional information is available in other L1.5 documentation. The Readout Control P2 Paddle Board (RC-P2PB) performs four functions: 1) TAS Protocol decoding 2) TAS Number latching 3) Front End Busy transmission, 4) signal level conversion and buffering It plugs into the P2 connector of an Ironics IV-1623 VMEbus Parallel I/O Board through the Backplane of the Level 1.5 CalTrig crate. There are three connectors on the board: P1 - 40-pin Universal Header connector with latches which carries the differential ECL Trigger Acquisition and Synchronization (TAS) signals, P2 - 96-pin DIN VME connector for communicating with the 68K Services computer through an Ironics IV-1623 Parallel I/O board P3 - 34-pin Universal Header connector with latches which acts as communication port between the P2 paddle Boards of the crate (called the Board to Board connector). Function: ========= 1) TAS Protocol (TASP) decoding: -------------------------------- The Readout Control P2 receives Start Digitize and Hold Transfer off of the TAS cable. It uses these to generate either Readout Required or Dump Event signals, which ever is appropriate. If Start Digitize goes low before Hold Transfer then Dump Event will be latched high. If Hold Transfer goes low before Start Digitize then Readout Required will be latched high. Readout Required and Dump Event are made available to the 68K Services computer through Ironics I/O ports. Logic: ------ The Start Digitize and Hold Transfer signals are read off the TAS cable and then converted to TTL. Each of these TTL signals acts as the input for a rising edge triggered D-Latch. Start Digitize is inverted and used as the clock for Hold Transfer to produce the Dump Event signal. Hold Transfer is inverted and used as the clock for Star Digitize to produce the Readout Required signal. Readout Required and Dump Event are output through Ironics ports. These outputs are cleared when Readout Complete is asserted through an input from another Ironics port. Timing: ------- Readout Required Dump Event ---------------- ---------- ________________ _________ H SD \___ SD \__________ L _________ ________________ H HT \__________ HT \___ L __ _________ H /SD _________________/ /SD __________/ L _________ __ H /HT __________/ /HT _________________/ L ____________________ ___________ H RORQ RORQ \________ L ___________ ____________________ H DUMP \________ DUMP L 2) TAS Number Latching: ----------------------- Readout Control reads the 16 bit differential ECL TAS number off of the TAS cable and converts them to TTL. The TTL TAS number is then latched at the rising edge of Hold Tranfser with the output going to two Ironics ports on the P2 connector. 3) Front End Busy transmission: ------------------------------- RC-P2PB makes a logical OR of the Readout Control Front End Busy from an Ironics port with the Engine Control Front End Busy from the Path Select P2 board. This is driven off board as Level 1.5 Calorimeter Front End Busy (differential ECL) which is sent to the Level 1 Frame Work over the TAS cable. 4) Signal Level Conversion and Buffering: ----------------------------------------- A TTL copy of Hold Transfer is buffered and driven off the board as Buffered Hold Transfer on the paddle board-to-paddle board bus. This is used by the Path Select and Term Select cards. Differential ECL copies of Start Digitize and >=1 Term Needs to be Evaluated are made available to the paddle board-to-paddle board bus. One TTL copy each of Slave Ready to VBD, VBD Done, MVME214 #1 Control, and MVME214 #2 is brought onto the Readout Control Card through Ironics ports, terminated, and then made available to the paddle board-to-paddle board bus as signal/ground pairs. P1: RC-P2PB 34 pin Trigger Acq. and Synch. Cable ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 Trig Aqc and Synch bit 0 Noninv TAS0NI 2 Trig Aqc and Synch bit 0 Inv TAS0I 3 Trig Aqc and Synch bit 1 Noninv TAS1NI 4 Trig Aqc and Synch bit 1 Inv TAS1I 5 Trig Aqc and Synch bit 2 Noninv TAS2NI 6 Trig Aqc and Synch bit 2 Inv TAS2I 7 Trig Aqc and Synch bit 3 Noninv TAS3NI 8 Trig Aqc and Synch bit 3 Inv TAS3I 9 Trig Aqc and Synch bit 4 Noninv TAS4NI 10 Trig Aqc and Synch bit 4 Inv TAS4I 11 Trig Aqc and Synch bit 5 Noninv TAS5NI 12 Trig Aqc and Synch bit 5 Inv TAS5I 13 Trig Aqc and Synch bit 6 Noninv TAS6NI 14 Trig Aqc and Synch bit 6 Inv TAS6I 15 Trig Aqc and Synch bit 7 Noninv TAS7NI 16 Trig Aqc and Synch bit 7 Inv TAS7I 17 Trig Aqc and Synch bit 8 Noninv TAS8NI 18 Trig Aqc and Synch bit 8 Inv TAS8I 19 Trig Aqc and Synch bit 9 Noninv TAS9NI 20 Trig Aqc and Synch bit 9 Inv TAS9I 21 Trig Aqc and Synch bit 10 Noninv TAS10NI 22 Trig Aqc and Synch bit 10 Inv TAS10I 23 Trig Aqc and Synch bit 11 Noninv TAS11NI 24 Trig Aqc and Synch bit 11 Inv TAS11I 25 Trig Aqc and Synch bit 12 Noninv TAS12NI 26 Trig Aqc and Synch bit 12 Inv TAS12I 27 Trig Aqc and Synch bit 13 Noninv TAS13NI 28 Trig Aqc and Synch bit 13 Inv TAS13I 29 Trig Aqc and Synch bit 14 Noninv TAS14NI 30 Trig Aqc and Synch bit 14 Inv TAS14I 31 Trig Aqc and Synch bit 15 Noninv TAS15NI 32 Trig Aqc and Synch bit 15 Inv TAS15I 33 Start Digitize Noninverted SDNIN 34 Start Digitize Inverted SDINV 35 Level 1.5 Cal Trig FEBz Noninvert L15CTFEBz 36 Level 1.5 Cal Trig FEBz Inverted L15CTFEBz 37 Hold Transfer Noninverted HTNIN 38 Hold Transfer Inverted HTINVI 39 Not Used ---- 40 Not Used ---- P2: RC-P2PB 96 pin DIN Ironics Connector ----------------------------------------------------------------- pin Signal Mnemonic Port ----------------------------------------------------------------- A 1 +5 V VCC ---- A 2 Not Used ----- 10 A 3 Not Used ----- 11 A 4 Not Used ----- 12 A 5 Not Used ----- 13 A 6 Not Used ----- 14 A 7 Not Used ----- 15 A 8 Not Used ----- 16 A 9 Not Used ----- 17 A 10 Slave Ready signal to VBD SRDY 20 A 11 Not Used ----- 21 A 12 Not Used ----- 22 A 13 Not Used ----- 23 A 14 Not Used ----- 24 A 15 Not Used ----- 25 A 16 Not Used ----- 26 A 17 Not Used ----- 27 A 18 Readout Required ROREQ 30 A 19 Dump Event DUMPE 31 A 20 Not Used ----- 32 A 21 Not Used ----- 33 A 22 VBD Done VDONE 34 A 23 Not Used ----- 35 A 24 Not Used ----- 36 A 25 Not Used ----- 37 A 26 Not Used ----- ---- A 27 Not Used ----- ---- A 28 Not Used ----- ---- A 29 Not Used ----- ---- A 30 Not Used ----- ---- A 31 Not Used ----- ---- A 32 Not Used ----- ---- B 1 +5.0 V VCC ---- B 2 Ground GND ---- B 3 Not Used ----- ---- B 4 Not Used ----- ---- B 5 Not Used ----- ---- B 6 Not Used ----- ---- B 7 Not Used ----- ---- B 8 Not Used ----- ---- B 9 Not Used ----- ---- B 10 Not Used ----- ---- B 11 Not Used ----- ---- B 12 Ground GND ---- B 13 +5.0 V VCC ---- B 14 Not Used ----- ---- B 15 Not Used ----- ---- B 16 Not Used ----- ---- B 17 Not Used ----- ---- B 18 Not Used ----- ---- B 19 Not Used ----- ---- B 20 Not Used ----- ---- B 21 Not Used ----- ---- B 22 Ground GND ---- B 23 Not Used ----- ---- B 24 Not Used ----- ---- B 25 Not Used ----- ---- B 26 Not Used ----- ---- B 27 Not Used ----- ---- B 28 Not Used ----- ---- B 29 Not Used ----- ---- B 30 Not Used ----- ---- B 31 Ground GND ---- B 32 +5.0 V VCC ---- C 1 Trig Acq and Synch bit 7 TAS7 67 C 2 Trig Acq and Synch bit 6 TAS6 66 C 3 Trig Acq and Synch bit 5 TAS5 65 C 4 Trig Acq and Synch bit 4 TAS4 64 C 5 Trig Acq and Synch bit 3 TAS3 63 C 6 Trig Acq and Synch bit 2 TAS2 62 C 7 Trig Acq and Synch bit 1 TAS1 61 C 8 Trig Acq and Synch bit 0 TAS0 60 C 9 Trig Acq and Synch bit 15 TAS15 57 C 10 Trig Acq and Synch bit 14 TAS14 56 C 11 Trig Acq and Synch bit 13 TAS13 55 C 12 Trig Acq and Synch bit 12 TAS12 54 C 13 Trig Acq and Synch bit 11 TAS11 53 C 14 Trig Acq and Synch bit 10 TAS10 52 C 15 Trig Acq and Synch bit 9 TAS9 51 C 16 Trig Acq and Synch bit 8 TAS8 50 C 17 Not Used ----- 47 C 18 Not Used ----- 46 C 19 Control MVME214 #2 CONT2 45 C 20 Control MVME214 #1 CONT1 44 C 21 Not Used ----- 43 C 22 Not Used ----- 42 C 23 Readout Control Front End Busy RCFEBz 41 C 24 Readout Control Clear RCDCLR 40 C 25 +5 V VCC ---- C 26 Not Used ----- ---- C 27 Not Used ----- ---- C 28 Not Used ----- ---- C 29 Not Used ----- ---- C 30 Not Used ----- ---- C 31 Not Used ----- ---- C 32 Not Used ----- ---- P3: RC-P2PB 34 pin Board to Board Bus Connector ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 -5.2 V VEE 2 -5.2 V VEE 3 -5.2 V VEE 4 -5.2 V VEE 5 Not Used ----- 6 Not Used ----- 7 ECL GE1T_NTBE Noninv GE1TEN 8 ECL GE1T_NTBE Invert GE1TEI 9 ECL Start Digitize Noninv STDIGN 10 ECL Start Digitize Invert STDIGI 11 Not Used ----- 12 Not Used ----- 13 Not Used ----- 14 Not Used ----- 15 Not Used ----- 16 Not Used ----- 17 Not Used ----- 18 Not Used ----- 19 Control MVME214 #2 output CON2OUT 20 Ground GND 21 Control MVME214 #1 output CON1OUT 22 Ground GND 23 VBD Done signal VDONE 24 Ground GND 25 Slave Ready signal to VBD SRDY 26 Ground GND 27 Not Used ----- 28 Ground GND 29 Eng Cont Front End Busy ECFEBz 30 Ground GND 31 Buffered Hold Transfer BUFHT 32 Ground GND 33 >= 1 Term Needs to be Evaluated GE1_TNBE 34 Ground GND