File: TERM_ANSWER_P2_CARD_DESCRIPTION.TXT Date: 28-JUL-1994 ****************************** * L1.5 Calorimeter Trigger * * * * Term Answer P2 Paddleboard * ****************************** General Introduction -------------------- This document describes the operation and design of the L1.5 Cal Trig Term Answer P2 Paddleboard. Description of the Term Answer Paddleboard ------------------------------------------- The Term Answer Paddleboard has the function of returning the L1.5 Calorimeter Trigger Term Answer and Done signals to the L1.5 Trigger Framework in Rack M103. A single Term Answer Paddleboard is used to service the 8 L1.5 Cal Trig Terms generated by one L1.5 Cal Trig crate. The 8 Term Answer and 8 Term Done signals are provided to the Term Answer Paddleboard via Ironics Ports. These Ironics ports are used for OUTPUT to the Term Answer Paddleboard. No Ironics Ports are used for INPUT from the Term Answer Paddleboard. The Term Answer Paddleboard processes Done signals and Answer signals differently. Both types of processing are described below. Term Answer Processing ---------------------- The Term Answers are received from Ironics Port 4. The assignment of data bits on Port 4 is as follows: Data Bit # Answer for Term # ---------- ----------------- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 The Term Answers are converted from TTL to ECL using 10H124 chips. The signal provided on the Ironics Port is always driven off from the Term Answer Paddleboard. A schematic of the Answer processing (for 1 of the 8 Answer signals) is provided below: .----------. | ECL->TTL | Term Answer | 10H124 | #i from | |--*--------> Term Answer #i NINV Ironics Port >---|TTL ECL| | (TTL) |IN OUT|O----*-----> Term Answer #i INV | | | | (Differential ECL) `----------' \ \ / / 470 \ \ 470 ohm / / ohm \ \ | | VEE -*--* Note that the "programming model" of this Ironics Port is simply that the mask of Term Answers should be written to this port (e.g. setting bit #3 to "0" indicates a positive Answer for L1.5 Cal Trig Term #3). Term Done Processing -------------------- The Term Dones are received from Ironics Port 5. The assignment of data bits on Port 5 is as follows: Data Bit # Done for Term # ---------- --------------- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 The Term Dones are used as the clock signals to "D" flip-flops (74ALS74), with one flip-flop used per Term Done. The "D" input of each flip-flop is tied to a logic "1". The "/Preset" input of each flip-flop is also tied to a logic "1" (i.e. the inactive state). The "/Reset" input of each flip-flop are tied to a common reset signal. This common reset signal will actually be the Hold Transfer signal. Thus, while Hold Transfer is at a logic LOW level, the Term Done outputs are also forced to logic LOW levels. When the Hold Transfer is at a logic HIGH level, each Term Done output will go high when the associated Ironics Port bit makes a low-to-high transition. A timing diagram of a single Done signal is provided below: _________ Hold Transfer ____/ \___ _ (note: Done from Ironics must make Done from Ironics XXXX\\\_/ XXXXXXXX a low-to-high transition while Hold Transfer is high to set the _____ Done to L1.5 TFW) Done to L1.5 TFW _________/ \__ A schematic of the Done processing (for 1 of the 8 Done signals) is provided below: "1" >--. | O .---------. | /S | .----------. | | | ECL->TTL | Term Done | 74ALS74 | | 10H124 | Term Done #i from | | | |--*--------> #i NINV Ironics Port >---|> Q|----|TTL ECL| | (TTL) | | |IN OUT|O----*-----> Term Done | | | | | | #i INV "1" >---|D /Q| `----------' \ \ | /R | / / `---------' 470 \ \ 470 Hold Transfer O ohm / / ohm from | \ \ Inter-P2 >------*---... | | Connector VEE -*--* (TTL) (common to all 8 Done Flip-Flops) Again note that the "programming model" of this Ironics Port is that the mask of Term Dones should be written to this port (e.g. setting bit #3 to "0" indicates that the Answer for Term #3 is valid). Note, however, that all bits on this Ironics Port must be returned to a logic 0 at some time BEFORE the L1.5 Cal Trig next reports to the L1.5 Trigger Framework. This is required to guarantee a low-to-high transition on the Done lines from the Ironics Port. Connectors on this card ----------------------- There are 3 connectors on this card: J1: 34-pin header with latches. This is the VEE and Inter-P2PB connector. J2: 96-pin DIN header. This is the connector which mates with the VME P2 connector. J3: 34-pin header with latches. This is the Term Answers and Dones to the Level 1.5 Trigger Framework connector. The pinouts of these connectors are as follows: ------------------------------------------------------------------------ J1: 34-pin connector: VEE and Inter-P2PB Connector ------------------------------------------------------------------------ Pin Function Mnemonic --- -------- -------- 1 VEE -5.2 V VEE 2 VEE -5.2 V VEE 3 VEE -5.2 V VEE 4 VEE -5.2 V VEE 5 Unused 6 Unused 7 Unused 8 Unused 9 Unused 10 Unused 11 Unused 12 Unused 13 Unused 14 Unused 15 Unused 16 Unused 17 Unused 18 Unused 19 Unused 20 Ground GROUND 21 Unused 22 Ground GROUND 23 Unused 24 Ground GROUND 25 Unused 26 Ground GROUND 27 Unused 28 Ground GROUND 29 Unused 30 Ground GROUND 31 Hold Transfer Input (TTL) HTTTLIN 32 Ground GROUND 33 Unused 34 Ground GROUND ------------------------------------------------------------------------ J2: 96-pin DIN connector: P2 Connector ------------------------------------------------------------------------ Pin Function Ironics Mnemonic --- -------- ------- -------- A1 VCC +5V VCC A2 Unused Port 1 Bit 0 IRP1B0 A3 Unused Port 1 Bit 1 IRP1B1 A4 Unused Port 1 Bit 2 IRP1B2 A5 Unused Port 1 Bit 3 IRP1B3 A6 Unused Port 1 Bit 4 IRP1B4 A7 Unused Port 1 Bit 5 IRP1B5 A8 Unused Port 1 Bit 6 IRP1B6 A9 Unused Port 1 Bit 7 IRP1B7 A10 Unused Port 2 Bit 0 IRP2B0 A11 Unused Port 2 Bit 1 IRP2B1 A12 Unused Port 2 Bit 2 IRP2B2 A13 Unused Port 2 Bit 3 IRP2B3 A14 Unused Port 2 Bit 4 IRP2B4 A15 Unused Port 2 Bit 5 IRP2B5 A16 Unused Port 2 Bit 6 IRP2B6 A17 Unused Port 2 Bit 7 IRP2B7 A18 Unused Port 3 Bit 0 IRP3B0 A19 Unused Port 3 Bit 1 IRP3B1 A20 Unused Port 3 Bit 2 IRP3B2 A21 Unused Port 3 Bit 3 IRP3B3 A22 Unused Port 3 Bit 4 IRP3B4 A23 Unused Port 3 Bit 5 IRP3B5 A24 Unused Port 3 Bit 6 IRP3B6 A25 Unused Port 3 Bit 7 IRP3B7 A26 Unused A27 Unused A28 Unused A29 Unused A30 Unused A31 Unused A32 Unused B1 VCC +5V VCC B2 Ground GROUND B3 Unused B4 Unused B5 Unused B6 Unused B7 Unused B8 Unused B9 Unused B10 Unused B11 Unused B12 Ground GROUND B13 VCC +5V VCC B14 Unused B15 Unused B16 Unused B17 Unused B18 Unused B19 Unused B20 Unused B21 Unused B22 Ground GROUND B23 Unused B24 Unused B25 Unused B26 Unused B27 Unused B28 Unused B29 Unused B30 Unused B31 Ground GROUND B32 VCC +5V VCC C1 Unused Port 6 Bit 7 IRP6B7 C2 Unused Port 6 Bit 6 IRP6B6 C3 Unused Port 6 Bit 5 IRP6B5 C4 Unused Port 6 Bit 4 IRP6B4 C5 Unused Port 6 Bit 3 IRP6B3 C6 Unused Port 6 Bit 2 IRP6B2 C7 Unused Port 6 Bit 1 IRP6B1 C8 Unused Port 6 Bit 0 IRP6B0 C9 L1.5 CT Term #7 Done Input Port 5 Bit 7 CTTDI7 C10 L1.5 CT Term #6 Done Input Port 5 Bit 6 CTTDI6 C11 L1.5 CT Term #5 Done Input Port 5 Bit 5 CTTDI5 C12 L1.5 CT Term #4 Done Input Port 5 Bit 4 CTTDI4 C13 L1.5 CT Term #3 Done Input Port 5 Bit 3 CTTDI3 C14 L1.5 CT Term #2 Done Input Port 5 Bit 2 CTTDI2 C15 L1.5 CT Term #1 Done Input Port 5 Bit 1 CTTDI1 C16 L1.5 CT Term #0 Done Input Port 5 Bit 0 CTTDI0 C17 L1.5 CT Term #7 Answer Input Port 4 Bit 7 CTTAI7 C18 L1.5 CT Term #6 Answer Input Port 4 Bit 6 CTTAI6 C19 L1.5 CT Term #5 Answer Input Port 4 Bit 5 CTTAI5 C20 L1.5 CT Term #4 Answer Input Port 4 Bit 4 CTTAI4 C21 L1.5 CT Term #3 Answer Input Port 4 Bit 3 CTTAI3 C22 L1.5 CT Term #2 Answer Input Port 4 Bit 2 CTTAI2 C23 L1.5 CT Term #1 Answer Input Port 4 Bit 1 CTTAI1 C24 L1.5 CT Term #0 Answer Input Port 4 Bit 0 CTTAI0 C25 VCC +5V VCC C26 Unused C27 Unused C28 Unused C29 Unused C30 Unused C31 Unused C32 Unused ------------------------------------------------------------------------ J3: 34-pin connector: Term Answers and Dones to L1.5 Trig FW Connector ------------------------------------------------------------------------ Pin Function Mnemonic --- -------- -------- 1 L1.5 Cal Trig Term #0 Answer Output NINV NCTTAO0 2 L1.5 Cal Trig Term #0 Answer Output INV ICTTAO0 3 L1.5 Cal Trig Term #1 Answer Output NINV NCTTAO1 4 L1.5 Cal Trig Term #1 Answer Output INV ICTTAO1 5 L1.5 Cal Trig Term #2 Answer Output NINV NCTTAO2 6 L1.5 Cal Trig Term #2 Answer Output INV ICTTAO2 7 L1.5 Cal Trig Term #3 Answer Output NINV NCTTAO3 8 L1.5 Cal Trig Term #3 Answer Output INV ICTTAO3 9 L1.5 Cal Trig Term #4 Answer Output NINV NCTTAO4 10 L1.5 Cal Trig Term #4 Answer Output INV ICTTAO4 11 L1.5 Cal Trig Term #5 Answer Output NINV NCTTAO5 12 L1.5 Cal Trig Term #5 Answer Output INV ICTTAO5 13 L1.5 Cal Trig Term #6 Answer Output NINV NCTTAO6 14 L1.5 Cal Trig Term #6 Answer Output INV ICTTAO6 15 L1.5 Cal Trig Term #7 Answer Output NINV NCTTAO7 16 L1.5 Cal Trig Term #7 Answer Output INV ICTTAO7 17 L1.5 Cal Trig Term #0 Done Output NINV NCTTDO0 18 L1.5 Cal Trig Term #0 Done Output INV NCCTDO0 19 L1.5 Cal Trig Term #1 Done Output NINV NCTTDO1 20 L1.5 Cal Trig Term #1 Done Output INV NCCTDO1 21 L1.5 Cal Trig Term #2 Done Output NINV NCTTDO2 22 L1.5 Cal Trig Term #2 Done Output INV NCCTDO2 23 L1.5 Cal Trig Term #3 Done Output NINV NCTTDO3 24 L1.5 Cal Trig Term #3 Done Output INV NCCTDO3 25 L1.5 Cal Trig Term #4 Done Output NINV NCTTDO4 26 L1.5 Cal Trig Term #4 Done Output INV NCCTDO4 27 L1.5 Cal Trig Term #5 Done Output NINV NCTTDO5 28 L1.5 Cal Trig Term #5 Done Output INV NCCTDO5 29 L1.5 Cal Trig Term #6 Done Output NINV NCTTDO6 30 L1.5 Cal Trig Term #6 Done Output INV NCCTDO6 31 L1.5 Cal Trig Term #7 Done Output NINV NCTTDO7 32 L1.5 Cal Trig Term #7 Done Output INV NCCTDO7 33 Unused 34 Unused