TERM_SELECT_P2_CARD_DESCRIPTION.TXT =================================== Rev. 9-AUG-1994 Latest Rev. 27-JUL-1994 This file describes the operation and design of the Term Select P2 Paddle Board. The Term Select P2 Paddle Board has two functions: 1) it determines which Level 1.5 Calorimeter Trigger algorithms will be used on the current event 2) generates the >=1 Term Needs to be Evaluated signal for the Readout Control and Path Select P2 Paddle Boards There are three connectors on the card. Their usage is as follows: P1: This is a 34 pin universal header with latches which brings the 16 bit differential ECL Specific Trigger Fired signal onto the card. P2: This is the 96 pin DIN VME P2 connector which allows communication with the 68K Services computer via an Ironics IV-1623 Parallel I/O board. P3: This is a 34 pin universal header with latches which provides access to the paddle board-to-paddle board bus as mixed TTL/ECL I/O. Functions ========= 1) Algorithm Selection ---------------------- The Algorithm Selection function of the Term Select P2 card has two modes of operation. "Mask" mode is the conditions under which the Term Select uses the Specific Trigger Fired mask as the SRAM address location of the desired Level 1.5 Calorimeter Trigger Algorithm Mask. This mode is selected by setting the MUX Select voltage low (ie. writing a "1" to Ironics port 5 bit 0). In "SRAM Programming" mode data can be written to the SRAM memory (via Ironics port 4) corresponding to to an SRAM address location which is supplied to the SRAM from the MUX from Ironics ports 2 and 3. This mode is selected by setting MUX Select voltage high (ie.writing a "0" to Ironics port 5 bit 0). When in Mask mode, the Term Select P2 receives the differential ECL Specific Trigger Fired Mask signal and converts it to TTL. The TTL Specific Trigger Fired signal is then latched by the MUX at the rising edge of the Buffered Hold Transfer signal from the Readout Control P2 card. This is given to a 64k X 8 SRAM which uses this address to select a preprogrammed 8 bit Level 1.5 Calorimeter Trigger algorithm mask, which is then sent to the 68K Services computer through an Ironics I/O port. The address which is presented to the SRAM can be read out through Ironics ports 1 and 6. 2) >=1 Term Needs to be Evaluated --------------------------------- The >=1 Term Needs to be Evaluated is generated by the Terms Select card by taking the OR of the 8 bits of the Level 1.5 Calorimeter Trigger Algorithm Mask. Therefore if any of the algorithm mask bits are high, >=1 Term Needs to be Evaluated is asserted over the paddle board-to-paddle board bus. This signal is also NANDed with a Force High signal and then NANDed with a Force Low signal so that the >=1 Term Needs to be Evaluated can be forced high or low for testing purposes. Ironics Ports and SRAM Programming ================================== The Term Select P2 card uses six Ironics port on its P2 connector for communicating with 68K Services computer. Two ports are used for reading output from the TS-P2PB, two ports are used for input to the TS-P2PB, one port can be used for either input or output, depending on mode of operation, and one port is used for control signals to the TS-P2PB. The Ironics Ports are used as follows: Port bit Function ----- --- ---------------------------------------------- 1 0:7 SRAM Address 0:7 6 0:7 SRAM Address 8:15 2 0:7 MUX Programming Address 0:7 3 0:7 MUX Programming Address 8:15 4 0:7 SRAM Programmming Data in / L1.5 CT Alg Mask out 5 Control signals to TS-P2PB 0 MUX_SEL: "0" MUX selects Spec Trig Fired data (Mask mode) "1" MUX selects SRAM programming data 1 /WE: "1" allows data to written into SRAM memory "0" allows Mask data to be read from SRAM only when /OE is "1" 2 /OE: "1" allows Mask data to be read from SRAM "0" allows data to be written to SRAM memory only when /WE is "1" 3 COMP_CLK: "0" latches data presented to the MUX during programming only when MUX Select is "1" 4:7 Not Used There are five vectors used on Ironics port 5 to program the SRAM: Vector binary | HEX Function ---------------- ------------------------------------------- 1111 0111 $F7 Latches the MUX data (SRAM address) 1111 1111 $FF Prepare to write to SRAM 1111 1011 $FB Write to SRAM 1111 1101 $FD Read data from SRAM 1111 1100 $FC Output is enabled, /WE is disabled and Specific Trigger Fired data addresses the SRAM The SRAM is loaded by the VME bus using the Ironics card. The steps in programming are as follows: 1. Generate a 64k data set for the card as desired. 2. Write $FF to Ironics port 5. This resets to the computer clock used in programming. 3. Write the least significant 8 bits of the MUX Programming Address to Ironics port 2 and the most significant 8 bits to Ironics port 3. 4. Write $F7 to Ironics port 5. This causes the MUX to latch the programming addresses which the SRAM will see. This address can also be read out through Ironics ports 1 and 6. 5. Write the Level 1.5 Calorimeter Trigger Algorithm Mask to Ironics port 4. 6. Write $FB to Ironics port 5. This puts the SRAM into "write data from port 4 to memory" mode. 7. Write $FF to Ironics port 5. This takes the SRAM out of "write" mode and makes it ready for new data. 8. Repeat steps 3 through 7 for each address location. 9. Write $FC to Ironics port 5. This causes the MUX to select data from Specific Trigger Fired to present to the SRAM. The value of an SRAM address location can be checked by the following steps: 1. Write $FF to Ironics port 2. Write the least significant 8 bits of the MUX Programming Address to Ironics port 2 and the most significant 8 bits to Ironics port 3. 3. Write $F7 to Ironics port 5. This causes the MUX to latch the programming addresses which the SRAM will see. This address can also be read out through Ironics ports 1 and 6. 4. Write $FB to Ironics port 5. This causes the SRAM to write the value of the memory location selected in step 2 to Ironics port 4. 5. Write $FC to Ironics port 5. This causes the MUX to select data from Specific Trigger Fired to present to the SRAM. P1: TS-P2PB 34 pin Specific Trigger Fired Cable ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 Spec Trigger Fired bit 0 Noninv STF0NI 2 Spec Trigger Fired bit 0 Inv STF0I 3 Spec Trigger Fired bit 1 Noninv STF1NI 4 Spec Trigger Fired bit 1 Inv STF1I 5 Spec Trigger Fired bit 2 Noninv STF2NI 6 Spec Trigger Fired bit 2 Inv STF2I 7 Spec Trigger Fired bit 3 Noninv STF3NI 8 Spec Trigger Fired bit 3 Inv STF3I 9 Spec Trigger Fired bit 4 Noninv STF4NI 10 Spec Trigger Fired bit 4 Inv STF4I 11 Spec Trigger Fired bit 5 Noninv STF5NI 12 Spec Trigger Fired bit 5 Inv STF5I 13 Spec Trigger Fired bit 6 Noninv STF6NI 14 Spec Trigger Fired bit 6 Inv STF6I 15 Spec Trigger Fired bit 7 Noninv STF7NI 16 Spec Trigger Fired bit 7 Inv STF7I 17 Spec Trigger Fired bit 8 Noninv STF8NI 18 Spec Trigger Fired bit 8 Inv STF8I 19 Spec Trigger Fired bit 9 Noninv STF9NI 20 Spec Trigger Fired bit 9 Inv STF9I 21 Spec Trigger Fired bit 10 Noninv STF10NI 22 Spec Trigger Fired bit 10 Inv STF10I 23 Spec Trigger Fired bit 11 Noninv STF11NI 24 Spec Trigger Fired bit 11 Inv STF11I 25 Spec Trigger Fired bit 12 Noninv STF12NI 26 Spec Trigger Fired bit 12 Inv STF12I 27 Spec Trigger Fired bit 13 Noninv STF13NI 28 Spec Trigger Fired bit 13 Inv STF13I 29 Spec Trigger Fired bit 14 Noninv STF14NI 30 Spec Trigger Fired bit 14 Inv STF14I 31 Spec Trigger Fired bit 15 Noninv STF15NI 32 Spec Trigger Fired bit 15 Inv STF15I 33 Not Used ----- 34 Not Used ----- P2: TS-P2PB 96 pin DIN Ironics Connector ----------------------------------------------------------------- pin Signal I/O Mnemonic Port ----------------------------------------------------------------- A 1 +5 V VCC ---- A 2 SRAM Address bit 0 O SRAM0 10 A 3 SRAM Address bit 1 O SRAM1 11 A 4 SRAM Address bit 2 O SRAM2 12 A 5 SRAM Address bit 3 O SRAM3 13 A 6 SRAM Address bit 4 O SRAM4 14 A 7 SRAM Address bit 5 O SRAM5 15 A 8 SRAM Address bit 6 O SRAM6 16 A 9 SRAM Address bit 7 O SRAM7 17 A 10 MUX Programming Address bit 0 I MXPA0 20 A 11 MUX Programming Address bit 1 I MXPA1 21 A 12 MUX Programming Address bit 2 I MXPA2 22 A 13 MUX Programming Address bit 3 I MXPA3 23 A 14 MUX Programming Address bit 4 I MXPA4 24 A 15 MUX Programming Address bit 5 I MXPA5 25 A 16 MUX Programming Address bit 6 I MXPA6 26 A 17 MUX Programming Address bit 7 I MXPA7 27 A 18 MUX Programming Address bit 8 I MXPA8 30 A 19 MUX Programming Address bit 9 I MXPA9 31 A 20 MUX Programming Address bit 10 I MXPA10 32 A 21 MUX Programming Address bit 11 I MXPA11 33 A 22 MUX Programming Address bit 12 I MXPA12 34 A 23 MUX Programming Address bit 13 I MXPA13 35 A 24 MUX Programming Address bit 14 I MXPA14 36 A 25 MUX Programming Address bit 15 I MXPA15 37 A 26 Not Used ----- ---- A 27 Not Used ----- ---- A 28 Not Used ----- ---- A 29 Not Used ----- ---- A 30 Not Used ----- ---- A 31 Not Used ----- ---- A 32 Not Used ----- ---- B 1 +5.0 V VCC ---- B 2 Ground GND ---- B 3 Not Used ----- ---- B 4 Not Used ----- ---- B 5 Not Used ----- ---- B 6 Not Used ----- ---- B 7 Not Used ----- ---- B 8 Not Used ----- ---- B 9 Not Used ----- ---- B 10 Not Used ----- ---- B 11 Not Used ----- ---- B 12 Ground GND ---- B 13 +5.0 V VCC ---- B 14 Not Used ----- ---- B 15 Not Used ----- ---- B 16 Not Used ----- ---- B 17 Not Used ----- ---- B 18 Not Used ----- ---- B 19 Not Used ----- ---- B 20 Not Used ----- ---- B 21 Not Used ----- ---- B 22 Ground GND ---- B 23 Not Used ----- ---- B 24 Not Used ----- ---- B 25 Not Used ----- ---- B 26 Not Used ----- ---- B 27 Not Used ----- ---- B 28 Not Used ----- ---- B 29 Not Used ----- ---- B 30 Not Used ----- ---- B 31 Ground GND ---- B 32 +5.0 V VCC ---- C 1 SRAM Address bit 15 O SRAM15 67 C 2 SRAM Address bit 14 O SRAM14 66 C 3 SRAM Address bit 13 O SRAM13 65 C 4 SRAM Address bit 12 O SRAM12 64 C 5 SRAM Address bit 11 O SRAM11 63 C 6 SRAM Address bit 10 O SRAM10 62 C 7 SRAM Address bit 9 O SRAM9 61 C 8 SRAM Address bit 8 O SRAM8 60 C 9 Not Used ----- 57 C 10 Not Used ----- 56 C 11 Not Used ----- 55 C 12 Not Used ----- 54 C 13 Computer Clock (to MUX) I COMPCLK 53 C 14 SRAM /Output Enable I /OE 52 C 15 SRAM /Write Enable I /WE 51 C 16 MUX Select I MUXSEL 50 C 17 L1.5 Cal Trg Alg Mask bit 7 I/O ALGM7 47 C 18 L1.5 Cal Trg Alg Mask bit 6 I/O ALGM6 46 C 19 L1.5 Cal Trg Alg Mask bit 5 I/O ALGM5 45 C 20 L1.5 Cal Trg Alg Mask bit 4 I/O ALGM4 44 C 21 L1.5 Cal Trg Alg Mask bit 3 I/O ALGM3 43 C 22 L1.5 Cal Trg Alg Mask bit 2 I/O ALGM2 42 C 23 L1.5 Cal Trg Alg Mask bit 1 I/O ALGM1 41 C 24 L1.5 Cal Trg Alg Mask bit 0 I/O ALGM0 40 C 25 +5 V VCC ---- C 26 Not Used ----- ---- C 27 Not Used ----- ---- C 28 Not Used ----- ---- C 29 Not Used ----- ---- C 30 Not Used ----- ---- C 31 Not Used ----- ---- C 32 Not Used ----- ---- P3: RC-P2PB 34 pin Board to Board Bus Connector ----------------------------------------------------------- pin Signal Mnemonic ----------------------------------------------------------- 1 -5.2 V VEE 2 -5.2 V VEE 3 -5.2 V VEE 4 -5.2 V VEE 5 Not Used ----- 6 Not Used ----- 7 Not Used ----- 8 Not Used ----- 9 Not Used ----- 10 Not Used ----- 11 Not Used ----- 12 Not Used ----- 13 Not Used ----- 14 Not Used ----- 15 Not Used ----- 16 Not Used ----- 17 Not Used ----- 18 Not Used ----- 19 Not Used ----- 20 Ground GND 21 Not Used ----- 22 Ground GND 23 Force GE1_TNBE High I FRCHI 24 Ground GND 25 Force GE1_TNBE Low I FRCLO 26 Ground GND 27 Not Used ----- 28 Ground GND 29 Not Used ----- 30 Ground GND 31 Buffered Hold Transfer I BUFHT 32 Ground GND 33 >= 1 Term Needs to be Evaluated O GE1_TNBE 34 Ground GND