VME Address Map of the Shared Dual Port Memories in the Hydra-II and MVME135 ----------------------------------------- Rev. 13-JUL-1994 We are using A24 VME addressing with Hydra II VME base addresses of: $00A0 0000 for Hydra II number A, $00B0 0000 for Hydra II number B, and $00C0 0000 for Hydra II number C. The Services 68K has a VME base address of $0006 0000. All four of these memory blocks are 32K bytes (8K longwords) long, and have identical Memory Maps. ---------------------------------------------------- SHARED DUAL PORT MEMORY AS USED IN THE L1.5 CAL TRIG ---------------------------------------------------- DSP Address [in hex] VME Address [in hex] Function (longword addresses) (byte addresses) -------- -------------------- -------------------- Universal Parameter Block 8000 0000 - 8000 001f 00*0 0000 - 00*0 007f Frame Term Parameter Block 8000 0020 - 8000 011f 00*0 0080 - 00*0 047f Local Term Parameter Block 8000 0120 - 8000 021f 00*0 0480 - 00*0 087f Global Term Parameter Block 8000 0220 - 8000 031f 00*0 0900 - 00*0 0c7f LDSP A2 Ref Sets [-20..-19] 8000 0320 - 8000 045f 00A0 0c80 - 00A0 117f LDSP A3 Ref Sets [-18..-15] 8000 0460 - 8000 059f 00A0 1180 - 00A0 167f LDSP A4 Ref Sets [-14..-11] 8000 05a0 - 8000 06df 00A0 1680 - 00A0 1b7f LDSP A1 Ref Sets [-10..-7 ] 8000 06e0 - 8000 081f 00A0 1b80 - 00A0 207f LDSP B3 Ref Sets [ -6..-3 ] 8000 0820 - 8000 095f 00B0 2080 - 00B0 257f LDSP B4 Ref Sets [ -2..+2 ] 8000 0960 - 8000 0a9f 00B0 2580 - 00B0 2a7f LDSP B1 Ref Sets [ +3..+6 ] 8000 0aa0 - 8000 0bdf 00B0 2a80 - 00B0 2f7f LDSP C3 Ref Sets [ +7..+10] 8000 0be0 - 8000 0d1f 00C0 2f80 - 00C0 347f LDSP C4 Ref Sets [+11..+14] 8000 0d20 - 8000 0e5f 00C0 3480 - 00C0 397f LDSP C1 Ref Sets [+15..+18] 8000 0e60 - 8000 0f9f 00C0 3980 - 00C0 3e7f LDSP C2 Ref Sets [+19..+20] 8000 0fa0 - 8000 10df 00C0 3e80 - 00C0 437f Unallocated for now 8000 10e0 - 8000 1e9f 00*0 4380 - 00*0 787f 68K Status to TCC 8000 1e60 - 8000 1e9f 0006 7980 - 0006 7a7f DSP Monitoring Information 8000 1ea0 - 8000 1ebf 00*0 7a80 - 00*0 7aff LDSP A2 inter-DSP Status 8000 1ec0 - 8000 1ec7 00A0 7b00 - 00A0 7b1f LDSP A3 inter-DSP Status 8000 1ec8 - 8000 1ecf 00A0 7b20 - 00A0 7b3f LDSP A4 inter-DSP Status 8000 1ed0 - 8000 1ed7 00A0 7b40 - 00A0 7b5f LDSP A1 inter-DSP Status 8000 1ed8 - 8000 1edf 00A0 7b60 - 00A0 7b7f LDSP B3 inter-DSP Status 8000 1ee0 - 8000 1ee7 00B0 7b80 - 00B0 7b9f LDSP B4 inter-DSP Status 8000 1ee8 - 8000 1eef 00B0 7ba0 - 00B0 7bbf LDSP B1 inter-DSP Status 8000 1ef0 - 8000 1ef7 00B0 7bc0 - 00B0 7bdf LDSP C3 inter-DSP Status 8000 1ef8 - 8000 1eff 00C0 7be0 - 00C0 7bff LDSP C4 inter-DSP Status 8000 1f00 - 8000 1f07 00C0 7c00 - 00C0 7c1f LDSP C1 inter-DSP Status 8000 1f08 - 8000 1f0f 00C0 7c20 - 00C0 7c3f LDSP C2 inter-DSP Status 8000 1f10 - 8000 1f17 00C0 7c40 - 00C0 7c5f GDSP B2 inter-DSP Status 8000 1f18 - 8000 1f1f 00B0 7c60 - 00B0 7c7f LDSP A2 Status to 68K 8000 1f20 - 8000 1f27 00A0 7c80 - 00A0 7c9f LDSP A3 Status to 68K 8000 1f28 - 8000 1f2f 00A0 7ca0 - 00A0 7cbf LDSP A4 Status to 68K 8000 1f30 - 8000 1f37 00A0 7cc0 - 00A0 7cdf LDSP A1 Status to 68K 8000 1f38 - 8000 1f3f 00A0 7ce0 - 00A0 7cff LDSP B3 Status to 68K 8000 1f40 - 8000 1f47 00B0 7d00 - 00B0 7d1f LDSP B4 Status to 68K 8000 1f48 - 8000 1f4f 00B0 7d20 - 00B0 7d3f LDSP B1 Status to 68K 8000 1f50 - 8000 1f57 00B0 7d40 - 00B0 7d5f LDSP C3 Status to 68K 8000 1f58 - 8000 1f5f 00C0 7d60 - 00C0 7d7f LDSP C4 Status to 68K 8000 1f60 - 8000 1f67 00C0 7d80 - 00C0 7d9f LDSP C1 Status to 68K 8000 1f68 - 8000 1f6f 00C0 7da0 - 00C0 7dbf LDSP C2 Status to 68K 8000 1f70 - 8000 1f77 00C0 7dc0 - 00C0 7ddf GDSP B2 Status to 68K 8000 1f78 - 8000 1f7f 00B0 7de0 - 00B0 7dff 68K Status (to all DSPs) 8000 1f80 - 8000 1f8f 00*0 7e00 - 00*0 7e3f LDSP A2 Status to TCC 8000 1f90 - 8000 1f97 00A0 7e40 00A0 7e5f LDSP A3 Status to TCC 8000 1f98 - 8000 1f9f 00A0 7e60 00A0 7e7f LDSP A4 Status to TCC 8000 1fa0 - 8000 1fa7 00A0 7e80 00A0 7e9f LDSP A1 Status to TCC 8000 1fa8 - 8000 1faf 00A0 7ea0 00A0 7ebf LDSP B3 Status to TCC 8000 1fb0 - 8000 1fb7 00B0 7ec0 00B0 7edf LDSP B4 Status to TCC 8000 1fb8 - 8000 1fbf 00B0 7ee0 00B0 7eff LDSP B1 Status to TCC 8000 1fc0 - 8000 1fc7 00B0 7f00 00B0 7e1f LDSP C3 Status to TCC 8000 1fc8 - 8000 1fcf 00C0 7f20 00C0 7e3f LDSP C4 Status to TCC 8000 1fd0 - 8000 1fd7 00C0 7f40 00C0 7e5f LDSP C1 Status to TCC 8000 1fd8 - 8000 1fdf 00C0 7f60 00C0 7e7f LDSP C2 Status to TCC 8000 1fe0 - 8000 1fe7 00C0 7f80 00C0 7e9f GDSP B2 Status to TCC 8000 1fe8 - 8000 1fef 00B0 7fa0 00B0 7ebf TCC Status (to all DSPs) 8000 1ff0 - 8000 1fff 00*0 7fc0 00*0 7eff * Note that some blocks must appear in all 3 Hydra cards. Recall that the VME memory map of all 3 Hydra cards (plus the MVME135) is identical.