DMA List Structure for the L1.5 Cal Trig ---------------------------------------- 17-MAY-1995 This file describes the DMA Lists used in the L1.5 Cal Trig. It is broken up into 3 parts: 1. Level 1 (ERPB) Data -> Local DSP's 2. Local-to-Global Data Transfer 3. Data Block -> MVME214 1. Level 1 (ERPB) Data -> Local DSP's --------------- All Local DSP's --------------- All Local DSP's have 4 DMA Lists (except for the "end" LDSP's which only have 2) used for importing Level 1 (ERPB) Data. The Lists are structured as follows: .---> Rack_1_EM_DMA_List [G,I] (in L_DMACMN) | | `---------' .---> Rack_1_Tot_DMA_List [G,I] (in L_DMACMN) | | `---------' .---> Rack_2_EM_DMA_List [G,I] (in L_DMACMN) | | `---------' .---> Rack_2_Tot_DMA_List [G,I] (in L_DMACMN) | | `---------' Each of these DMA Lists proceeds automatically (it does not wait to be kicked but is always ready to go). The CPU is interrupted when each List completes. 2. Local-to-Global Data Transfer --------------------------- LDSP A1, A4, B1, B4, C1, C4 --------------------------- These LDSP's have no Previous DSP. They only need to worry about transferring data to the Next DSP. They have a single "chain" of DMA Lists: .---> LG_Next_DMA_List, which is composed of: | LG_Count_DMA_List [H,I] (in L_DMACMN) | | | | normal | | MFP | V | | LG_Object_DMA_List | [H,I] (in L_DMACMN) | | | +---------' | | | | LG_MFP_DMA_List, which is composed of: | MFP_Object_DMA_List [H,NI] (in L_DMACMN) | MFP_Et_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E1_Data_DMA_List [G,NI] (in L_DMACMN) | MFP_T1_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_T2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Hdr_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Set_DMA_List [G,NI] (in L_DMACMN) | MFP_DC_DMA_List [G,I] (in L_DSP_xx) | | `----------------' The LG_Next_DMA_List needs to be "kicked." It is "kicked" as soon as this LDSP has assembled the information to be transferred. There is no need to wait for information to arrive from a Previous DSP (because there is no Previous DSP). Once LG_Next_DMA_List has been "kicked," it runs only to the completion of LG_Count_DMA_List, where the CPU is interrupted and the list halts. The CPU needs to "kick" this list again to cause the transfer to continue with either the LG_Object_DMA_List or the LG_MFP_DMA_List. In either case, the list chosen (whether a single link or multiple links) runs to completion, interrupts the CPU, and automatically re-loads the LG_Next_DMA_List. During normal events, the CPU is interrupted after LG_Object_DMA_List. During MFP events, the CPU is interrupted after MFP_DC_DMA_List. ----------- LDSP A3, C3 ----------- These LDSP's have a single Previous DSP. Thus they need to worry about receiving data from the single Previous DSP and also sending data to the Next DSP. The transfer to the Next DSP cannot occur until all data from the Previous DSP has arrived. They then have two distinct chains of DMA Lists: .---> LG_Pr_4_DMA_List, composed of: | LG_Pr_4_Count_DMA_List [G,I] (in L_DSP_xx) | | | | normal | | MFP | V | | LG_Pr_4_Object_DMA_List | [H,I] (in L_DSP_xx) | | | +---------' | | V | LG_MFP_Pr_4_DMA_List, composed of: | LG_MFP_P4_OL_DMA_List [H,NI] (in L_DSP_xx) | LG_MFP_Pr_4_Data_DMA_List [G,I] (in L_DSP_xx) | | `----------------' .---> LG_Next_DMA_List, which is composed of: | LG_Count_DMA_List [H,I] (in L_DMACMN) | | | | normal | | MFP | V | | LG_Object_DMA_List | [H,I] (in L_DMACMN) | | | +---------' | | | | LG_MFP_DMA_List, which is composed of: | MFP_Object_DMA_List [H,NI] (in L_DMACMN) | MFP_Et_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E1_Data_DMA_List [G,NI] (in L_DMACMN) | MFP_T1_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_T2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Hdr_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Set_DMA_List [G,NI] (in L_DMACMN) | MFP_DC_DMA_List [G,NI] (in L_DSP_xx) | MFP_Prv_to_Nxt_DMA_List [G,I] (in L_DSP_xx) | | `----------------' The LG_Pr_4_DMA_List proceeds automatically (it does not wait to be kicked but is always ready to go). But, it halts after completion of the LG_Pr_4_Count_DMA_List and interrupts the CPU. The CPU then manually "kicks" this list, which continues with either LG_Pr_4_Object_DMA_List or LG_MFP_Pr_4_DMA_List and follows the rest of the links automatically (including re-loading the LG_Pr_4_DMA_List). During normal events the CPU is interrupted after LG_Pr_4_Object_DMA_List finishes. During MFP events, the CPU is interrupted after LG_MFP_Pr_4_DMA_List. The LG_Next_DMA_List needs to be "kicked." It is "kicked" as soon as this LDSP has assembled the information to be transferred. This includes waiting for the LG_Pr_4_DMA_List to finish. Once LG_Next_DMA_List has been "kicked," it runs only to the completion of LG_Count_DMA_List, where the CPU is interrupted and the list halts. The CPU needs to "kick" this list again to cause the transfer to continue with either the LG_Object_DMA_List or the LG_MFP_DMA_List. In either case, the list chosen (whether a single link or multiple links) runs to completion, interrupts the CPU, and automatically re-loads the LG_Next_DMA_List. During normal events, the CPU is interrupted after LG_Object_DMA_List. During MFP events, the CPU is interrupted after MFP_Prv_to_Nxt_DMA_List events, the CPU is interrupted after MFP_DC_DMA_List. ----------- LDSP A2, C2 ----------- These LDSP's have two Previous DSP's. Thus they need to worry about receiving data from both Previous DSP's and also sending data to the Next DSP. The transfer to the Next DSP cannot occur until all data from the Previous DSP's has arrived. They then have three distinct chains of DMA Lists: .---> LG_Pr_1_DMA_List, composed of: | LG_Pr_1_Count_DMA_List [G,I] (in L_DSP_xx) | | | | normal | | MFP | V | | LG_Pr_1_Object_DMA_List | [H,I] (in L_DSP_xx) | | | +---------' | | V | LG_MFP_Pr_1_DMA_List, composed of: | LG_MFP_P1_OL_DMA_List [H,NI] (in L_DSP_xx) | LG_MFP_Pr_1_Data_DMA_List [G,I] (in L_DSP_xx) | | `----------------' .---> LG_Pr_3_DMA_List, composed of: | LG_Pr_3_Count_DMA_List [G,I] (in L_DSP_xx) | | | | normal | | MFP | V | | LG_Pr_3_Object_DMA_List | [H,I] (in L_DSP_xx) | | | +---------' | | V | LG_MFP_Pr_3_DMA_List, composed of: | LG_MFP_P3_OL_DMA_List [H,NI] (in L_DSP_xx) | LG_MFP_Pr_3_Data_DMA_List [G,I] (in L_DSP_xx) | | `----------------' .---> LG_Next_DMA_List, which is composed of: | LG_Count_DMA_List [H,I] (in L_DMACMN) | | | | normal | | MFP | V | | LG_Object_DMA_List | [H,I] (in L_DMACMN) | | | +---------' | | | | LG_MFP_DMA_List, which is composed of: | MFP_Object_DMA_List [H,NI] (in L_DMACMN) | MFP_Et_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E1_Data_DMA_List [G,NI] (in L_DMACMN) | MFP_T1_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_E2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_T2_Head_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Hdr_DMA_List [G,NI] (in L_DMACMN) | MFP_Ref_Set_DMA_List [G,NI] (in L_DMACMN) | MFP_DC_DMA_List [G,NI] (in L_DSP_xx) | MFP_Prv_to_Nxt_DMA_List [G,I] (in L_DSP_xx) | | `----------------' The LG_Pr_%_DMA_Lists proceed automatically (they donot wait to be kicked but are always ready to go). But, they halt after completion of the LG_Pr_%_Count_DMA_List and interrupt the CPU. The CPU then manually "kicks" these lists, which continue with either LG_Pr_%_Object_DMA_List or LG_MFP_Pr_%DMA_List and follow the rest of the links automatically (including re-loading the LG_Pr_%_DMA_List). During normal events the CPU is interrupted after LG_Pr_%_Object_DMA_Lists finishe. During MFP events, the CPU is interrupted after LG_MFP_Pr_%_DMA_List. The LG_Next_DMA_List needs to be "kicked." It is "kicked" as soon as this LDSP has assembled the information to be transferred. This includes waiting for the LG_Pr_%4_DMA_Lists to finish. Once LG_Next_DMA_List has been "kicked," it runs only to the completion of LG_Count_DMA_List, where the CPU is interrupted and the list halts. The CPU needs to "kick" this list again to cause the transfer to continue with either the LG_Object_DMA_List or the LG_MFP_DMA_List. In either case, the list chosen (whether a single link or multiple links) runs to completion, interrupts the CPU, and automatically re-loads the LG_Next_DMA_List. During normal events, the CPU is interrupted after LG_Object_DMA_List. During MFP events, the CPU is interrupted after MFP_Prv_to_Nxt_DMA_List events, the CPU is interrupted after MFP_DC_DMA_List. ---- GDSP ---- The Global DSP has 4 Previous DSP's. It has to worry about receiving data from these 4 Previous DSP's. It uses 4 distinct chains of DMA Lists .---> LDSP_A1234_DMA_List, composed of: | LDSP_A1234_Count_DMA_List [G,I] (in G_DSP_B2) | | | | normal | | MFP | V | | LDSP_A1234_Object_DMA_List | [H,I] (in G_DSP_B2) | | | +---------' | | V | LDSP_A1234_MFP_DMA_List, composed of: | MFP_A1234_Obj_DMA_List [H,NI] (in G_DSP_B2) | MFP_A1234_Data_DMA_List [G,I] (in G_DSP_B2) | | `----------------' .---> LDSP_B1_DMA_List, composed of: | LDSP_B1_Count_DMA_List [G,I] (in G_DSP_B2) | | | | normal | | MFP | V | | LDSP_B1_Object_DMA_List | [H,I] (in G_DSP_B2) | | | +---------' | | V | LDSP_B1_MFP_DMA_List, composed of: | MFP_B1_Obj_DMA_List [H,NI] (in G_DSP_B2) | MFP_B1_Data_DMA_List [G,I] (in G_DSP_B2) | | `----------------' .---> LDSP_B34_DMA_List, composed of: | LDSP_B34_Count_DMA_List [G,I] (in G_DSP_B2) | | | | normal | | MFP | V | | LDSP_B34_Object_DMA_List | [H,I] (in G_DSP_B2) | | | +---------' | | V | LDSP_B34_MFP_DMA_List, composed of: | MFP_B34_Obj_DMA_List [H,NI] (in G_DSP_B2) | MFP_B34_Data_DMA_List [G,I] (in G_DSP_B2) | | `----------------' .---> LDSP_C1234_DMA_List, composed of: | LDSP_C1234_Count_DMA_List [G,I] (in G_DSP_B2) | | | | normal | | MFP | V | | LDSP_C1234_Object_DMA_List | [H,I] (in G_DSP_B2) | | | +---------' | | V | LDSP_C1234_MFP_DMA_List, composed of: | MFP_C1234_Obj_DMA_List [H,NI] (in G_DSP_B2) | MFP_C2_Data_DMA_List [G,NI] (in G_DSP_B2) | MFP_C134_Data_DMA_List [G,I] (in G_DSP_B2) | | `----------------' Each of these DMA Lists proceeds automatically (they do not wait to be kicked but are always ready to go). But, they halt and interrupt the CPU after the completion of LDSP_x_Count_DMA_List. They require the CPU to kick them before they continue with either LDSP_x_Object_DMA_List or MFP_x_Obj_DMA_List. Once kicked, they complete automatically, following all of the links in the chain (including reloading the L_DSP_x_DMA_List). For normal events, the CPU is interrupted after LDSP_x_Object_DMA_List completes. For MFP events, the CPU is interrupted after MFP_x_Data_DMA_List completes. Note that the link from Hydra C is different than the other links. This is because Hydra C emits its Mark and Force Pass data NOT in ascending eta order, but in a funny order. Specifically, the MFP data for LDSP C2 (the highest eta) comes first, then the MFP data for the other 3 LDSP's on Hydra C, in normal ascending eta order. This is done to simplify the transfer from LDSP C2's point of view. 3. Data Block -> MVME214 Transfer ---- GDSP ---- The Global DSP transfers data to the MVME214. It uses a single chain of DMA Lists to perform this function. .---> OLs_to_214_DMA_List [H,NI] (in G_DSP_B2) | | \ | normal | ---------\ | V | | Normal_DeBug_Sect_DMA_List | [G,I] (in G_DSP_B2) | | | +---------' /----------/ | | MFP | V | MFP_to_214_DMA_List [G,I] (in G_DSP_B2) | | `----------------' The OLs_to_214_DMA_List needs to be "kicked" by the CPU. It is not kicked until the CPU has The OLs_to_214_DMA_List needs to be "kicked." It is "kicked" as soon as the GDSP has assembled the information to be transferred. This requires waiting for the incoming DMA Lists (described above) to complete. Once the chain has been "kicked," it runs to completion, following all links. During normal events, the CPU is interrupted after Normal_DeBug_Sect_DMA_List finishes. During MFP events, the CPU is interrupted after MFP_to_214_DMA_List finishes.