CTFE to ERPB to CRC Timing - MTG Control ----------------------------------------------- Rev. 19-MAY-1995 This file gives the background information and the details about the setup of the timing control of the data transfer from the CTFE to the ERPB and then to the CRC. The description of the initial setup is given below. This initial setup will be modified for actual production physics running. Details of these required modifications will be added to this file later. CTFE Background and Initial Setup for L15CT ------------------------------------------- Timing & Sync Signals F and G are used for the X Clock Signal and the 2X Clock Signal. These are the only Timing Signals necessary to sequence the CTFE Card through its normal operation for each beam crossing. The Total Et Latches are updated on the positive edge of the 2X Clock when the X Clock is high. The EM Et and HD Veto Comparator Latches are also updated on the positive edge of the 2X Clock when the X Clock is High. The Energy Lookup Memory registered PROM's are clocked by all positive edges of the 2X Clock signal. As currently running (16-JUN-1994 using Cal Trig MTG PROM 1 SN#M, PROM 2 SN#L, PROM 3 SN#K and PROM 4 SN#M) the Total Et Latch is loaded twice per beam crossing; first with Total Et data and second with EM Et data. The details of this function are described below: Cal Trig MTG PROM 1 has the 2X_Clock (Ch #2) and the X_Clock (Ch #3) both go high for a second time. They go high for ticks #65 and #66. Note that this is not only after L1 Cal Trig Tier 2 has grabbed all of the data from the CTFE's for this beam crossing but this is in fact after the L1 FW IML has clocked. Thus this should be completely safe. It also, like every other timing signal in the Cal Trig, will need to be re-thought about for 400/132/19 ns bunch spacing. Cal Trig MTG PROM 2 has all 6 of the Map Select signals (Ch #9:#14) stay high until tick #70. This keeps the CTFE Lookup PROM's aimed at their second lookup for a longer period of time (they formerly fell at tick #52). The second lookup is needed to read out the EM Et data. Holding these 6 Map Select lines high for a longer period of time should not cause any trouble. ERPB Control Background ----------------------- This section describes how the 8 timing and control lines going to each ERPB actually control the card. There are 5 lines which are used to control the ERPB card: ERPB_Capture_Clock: This signal should typically be high, but should pulse low twice during each beam crossing (once to capture Total Et data, once to capture EM Et data). It runs all of the time (except during ERPB LCA loading). ERPB_Select_TotEt/EMEt: This signal goes high to indicate that ERPBs should latch Total Et data, and low to indicate that ERPBs should latch EM Et data. It runs all of the time (except during ERPB LCA loading) ERPB_Store_Enable_BAR: This signal is normally low (which enables the ERPBs to STORE new EM and Total data), and it goes high for one full beam crossing after a beam crossing which caused a trigger. The use of this channel will change when we implement double-buffering in the ERPBs. ERPB_Latch_Enable_BAR: This signal is normally high (which disables the ERPBs from transferring their recently stored CTFE data into their transmit registers), and it goes low for one full beam crossing after a beam crossing which caused a trigger (i.e. it is the INVERSE of ERPB_Latch_Enable_BAR). The use of this channel will change when we implement double-buffering in the ERPBs. ERPB_Transmit_Trigger: This signal is typically low. It goes high for one microsecond after data has been transferred into the transmit registers. A pulse on this signal initiates the transfer of the L1 CTFE data (stored in the ERPBs) to the L1.5 Cal Trig. Initial setup of the MTG to Control the ERPB's ---------------------------------------------- This MTG that controls the ERPB's is called the ERPB MTG. It is located in the CRC Crate in rack M124. It is accessed via CBus=3, BBA=88, MBA=89, CA=35. The 53 MHz clock and the Once per Turn Marker that are used to synchronize the ERPB MTG do not come directly from the Master Clock. Rather the ERPB MTG is synchronized from the Monitor outputs on the Cal Trig MTG in rack M114. The cables that carry the 53 MHz and the Once per Turn Marker from M114 to M124 are about 40 nsec long. To make the ERPB MTG run in sync with the other MTG's its Preset Register will be loaded with a value 1 higher than the other Preset Registers. This should put the ERPB MTG within one tick of the other MTG's. Note that this different preset value means that nothing should happen or change during the first couple of ticks of the ERPB MTG PROM's. The Terminal Count Register should also be programmed with a value 1 higher than used for all other MTGs. Thus the following values are loaded into the ERPB MTG control registers. Function Value Register Address Loaded Resulting Setup ----------- -------- ------ ----------------------------------------- PreSet LSB 33 101 Load the PROM Address Counter PreSet PreSet MSB 34 0 Register with a value of 101. Termnl LSB 35 143 Load the PROM Address Counter Terminal Termnl MSB 36 2 Count Register with 655 i.e. 143 + 2*256. Control Reg 37 22 Select External Clock and either Beam Crossing or Terminal Count can preset PROM Address counter. ERPB MTG Channel Assignments: Channels #1:#8 are the "master" channels. Channels #9:#16 feed the |eta| = 1:8 section. Channels #17:#24 feed the |eta| = 9:16 section. Channels #25:#32 feed the |eta| = 17:20 section. There are 5 channels that control the actual running operation of ERPB's in each section and 3 channels that control the loading of the logic cell arrays in each section. These channels that control the loading of the logic cell arrays are not "mastered". This leaves three spare channels in the "master" section for future use in generating complex control signals. Channel PAL Load Number Function Type Value ------- ------------------------------------------------ -------- ----- 1 Master the ERPB_Capture_Clock signal. This clock MTGBit2 12 is normally high and it goes low twice during each beam crossing cycle. It goes low for ticks: 50,51,52 and 78,79,80. This signal runs all of the time. 2 Master the ERPB_Select_TotEt/EMEt signal. This MTGBit2 12 signal is high for the ERPB to load Tot Et data and it is low to load EM Et data. This signal runs all of the time. It goes up at tick 20 and comes down at tick 63. 3 Master the ERPB_Store_Enable_Bar signal. When MTGBit7 10 this signal is low then the ERPB's will capture new data from the CTFE's on the falling edge of the ERPB_Capture_Clock. This signal is normally LOW and it goes HIGH for the beam crossing following a beam crossing that you want to readout through the ERPB's. The MTGBit7 PAL is just a latch that "updates" from a pulse in the PROM. We will use the BITOUT from ERPB MTG Channel #8 (i.e. a one beam crossing version of "That's Me" which will become active at tick #4 of the beam crossing immediately following the beam crossing which is to be read out) as the EXTBIT to this Channel. The PROM for this channel will pulse high for ticks #11 and #12 of the timing pattern. 4 Master the ERPB_Latch_Enable_Bar signal. When MTGBit7 10 signal is low and the ERPB_Select_TotEt/EMEt signal is high then on the falling edge of the ERPB_Capture_Clock, data is loaded into the Transmit Registers on the ERPB's. This signal is normally HIGH and it goes LOW for the beam crossing following a beam crossing that you want to readout through the ERPB's. The MTGBit7 PAL is just a latch that "updates" from a pulse in the PROM. We will use an INVERTED BITOUT from ERPB MTG Channel #8 (i.e. a one beam crossing version of "That's Me" which will become active at tick #4 of the beam crossing immediately following the beam crossing which is to be read out) as the EXTBIT to this Channel. The PROM for this channel will pulse high for ticks #11 and #12 of the timing pattern. 5 Master the ERPB_Transmit_Trigger signal. When MTGBit2 4 this signal goes high for 1 usec then the ERPB's will begin sending data to the CRC's. We will use the BITOUT from ERPB MTG Channel #7 (i.e. a delayed one beam crossing version of the output of MTG Channel #8) which will become active at tick #75 of the beam crossing immediately following the beam crossing which is to be read out as the EXTENB to this Channel. The BITOUT from this Channel will be high from ticks #45 through #71 of the 2nd beam crossing following the beam crossing which is to be read out. The PROM for this Channel will go up at tick #45 and down at tick #72. 6 Spare for future "master" signal use. MTGBit2 9 This Channel is not used, it is programmed to generate a DC LOW output. 7 Spare for future "master" signal use. MTGBit15 This Channel is used as a delay loop. The EXTBIT of this Channel comes from the BITOUT of Channel #8. first 0 The BITOUT of this Channel is a one-beam-crossing then 4 version of "That's Me" which becomes active at tick #75 of the beam crossing immediately following the beam crossing which is to be read out. The PROM pattern in this Channel goes up at tick #75 and down at tick #77. The ExtEnb for this channel comes from 68K_Service via the Path Select Ironics card Port #1 LSBit. When ExtEnb is active then this PAL immediately sends out its one BX long pulse on its BitOut line. When ExtEnb is inactive then this PAL "remembers" if it has received an incomming trigger on its ExtBit input and if it has received an input trigger then it will generate a one BX long output pulse on its BitOut as soon as it is re-enabled on its ExtEnb pin and it receives a PROM timing pulse. 8 Spare for future "master" signal use. MTGBit8 10 This Channel is used as a delay loop. The EXTBIT of this Channel comes from the "That's Me" output of the Path Select P2 Paddleboard. the BITOUT of this Channel is a one-beam-crossing version of "That's Me" which becomes active at tick #4 of the beam crossing immediately following the beam crossing which is to be read out. The PROM pattern in this Channel goes up at tick #4 and down at tick #6. 9 Drive ERPB_Capture_Clock signal to |eta| 1:8 Bit2 10 10 Drive ERPB_Select_TotEt/EMEt signal to |eta| 1:8 Bit2 10 11 Drive ERPB_Store_Enable_Bar signal to |eta| 1:8 Bit2 10 12 Drive ERPB_Latch_Enable_Bar signal to |eta| 1:8 Bit2 10 13 Drive ERPB_Transmit_Trigger signal to |eta| 1:8 Bit2 10 14 Load the Logic Cell Array signal 1 to |eta| 1:8 Bit2 25 15 Load the Logic Cell Array signal 2 to |eta| 1:8 Bit2 25 16 Load the Logic Cell Array signal 3 to |eta| 1:8 Bit2 25 17 Drive ERPB_Capture_Clock signal to |eta| 9:16 Bit2 10 18 Drive ERPB_Select_TotEt/EMEt signal to |eta| 9:16 Bit2 10 19 Drive ERPB_Store_Enable_Bar signal to |eta| 9:16 Bit2 10 20 Drive ERPB_Latch_Enable_Bar signal to |eta| 9:16 Bit2 10 21 Drive ERPB_Transmit_Trigger signal to |eta| 9:16 Bit2 10 22 Load the Logic Cell Array signal 1 to |eta| 9:16 Bit2 25 23 Load the Logic Cell Array signal 2 to |eta| 9:16 Bit2 25 24 Load the Logic Cell Array signal 3 to |eta| 9:16 Bit2 25 25 Drive ERPB_Capture_Clock signal to |eta| 17:20 Bit2 10 26 Drive ERPB_Select_TotEt/EMEt signal to |eta| 17:20 Bit2 10 27 Drive ERPB_Store_Enable_Bar signal to |eta| 17:20 Bit2 10 28 Drive ERPB_Latch_Enable_Bar signal to |eta| 17:20 Bit2 10 29 Drive ERPB_Transmit_Trigger signal to |eta| 17:20 Bit2 10 30 Load the Logic Cell Array signal 1 to |eta| 17:20 Bit2 25 31 Load the Logic Cell Array signal 2 to |eta| 17:20 Bit2 25 32 Load the Logic Cell Array signal 3 to |eta| 17:20 Bit2 25 In the above it is assumed that the "master" channel outputs are connected to the External Bit Inputs of the "driver" channels. Schematic Diagram of the "chained" ERPB MTG signals --------------------------------------------------- .------. EXT | MTG | BIT "That's Me" >-----| Ch.8 |---------. BIT | BIT8 | OUT | | PAL | | ROM | | | HI for ROM >-----| | | ticks 4:5 IN | | | `------' | | .--------------------------------------' | | .------. | EXT | MTG | BIT *---------------------| Ch.3 |------------> MASTER Store_Enable_BAR | BIT | BIT7 | OUT | | PAL | | ROM | | | HI for ROM >-----| | | ticks 11:12 IN | | | `------' | | | | . .------. | |\ EXT | MTG | BIT *----| O--------------| Ch.4 |------------> MASTER Latch_Enable_BAR | |/ BIT | BIT7 | OUT | ' | PAL | | ROM | | | HI for ROM >-----| | | ticks 11:12 IN | | | `------' | | | | .------. | ExtBit | MTG | BIT `---------------------| Ch.7 |---------. | BIT15| OUT | From 68k | PAL | | Ser via ExtEnb | | | Term Sel >----------->| | | Ironics | | | Port #1 LSBit | | | | | | ROM | | | HI for ROM >-----| | | ticks 75:76 IN | | | `------' | | .--------------------------------------' | | .------. | EXT | MTG | BIT `---------------------| Ch.5 |------------> MASTER Transmit_Trigger BIT | BIT2 | OUT | PAL | ROM | | HI for ROM >-----| | ticks 45:71 IN | | `------' Level 1.5 Cal Trig ERPB MTG Timing Patch Panel ---------------------------------------------- Timing Input Connector on Distributor Distributor Cap Signal ERPB ERPB MTG Signal Name Cap Pin No. Name & Alias Signal Name and Master Channel Number ------------- ------------- ----------- --------------------------- 1- 2 no connection ............................................... 3- 4 MTG_0 Setup_0 Input_Clk Ch#1 ERPB_Capture_Clock 5- 6 no connection ............................................... 7- 8 MTG_1 Setup_1 Total Ch#2 ERPB_Select_TotEt/EMEt 9-10 MTG_2 Setup_2 /Store Ch#3 ERPB_Store_Enable_Bar 11-12 MTG_3 Setup_3 /Latch Ch#4 ERPB_Latch_Enable_Bar 13-14 MTG_4 Setup_4 (not used) (not available) 15-16 no connection ............................................... 17-18 MTG_5 Setup_5 (not used) (not available) 19-20 no connection ............................................... 21-22 MTG_6 Setup_6 XMIT_Trig Ch#5 ERPB_Transmit_Trigger 23-24 MTG_7 Setup_7 (not used) (not mastered, made locally) 25-26 MTG_8 Dist_ADR (not used) (not mastered, made locally) 27-28 MTG_9 /Dist_STB (not used) (not mastered, made locally) 29-30 MTG_X (not used) (not available) 31-32 MTG_Y (not used) (not available) 33-34 no connection ............................................... Wiring of the ERPB MTG output to the ERPB Input and Cable Connectors to the Distributor Cap Cards --------------------------------------------------------------- Distributor Distributor Distributor ERPB MTG ERPB MTG Connector Connector Connector Output Ch No Input Ch No |Eta| 1:8 |Eta| 9:16 |Eta| 17:20 and Pin No's. and Function Pin Numbers Pin Numbers Pin Numbers --------------- -------------- ----------- ----------- ----------- Ch #1 1- 2 Ch #9 ExtBit - - - Ch #2 3- 4 Ch #10 ExtBit - - - Ch #3 5- 6 Ch #11 ExtBit - - - Ch #4 7- 8 Ch #12 ExtBit - - - Ch #5 9-10 Ch #13 ExtBit - - - Ch #6 11-12 - - - - Ch #7 13-14 - - - - Ch #8 15-16 - - - - Ch #9 17-18 - -- 3- 4 - - Ch #10 19-20 - 7- 8 - - Ch #11 21-22 - 9-10 - - Ch #12 23-24 - 11-12 - - Ch #13 25-26 - 21-22 - - Ch #14 27-28 - 23-24 - - Ch #15 29-30 - 25-26 - - Ch #16 31-32 - 27-28 - - Ch #17 33-34 - -- - -- 3- 4 - Ch #18 35-36 - - 7- 8 - Ch #19 37-38 - - 9-10 - Ch #20 39-40 - - 11-12 - Ch #21 41-42 - - 21-22 - Ch #22 43-44 - - 23-24 - Ch #23 45-46 - - 25-26 - Ch #24 47-48 - - 27-28 - Ch #25 49-50 - -- - -- - -- 3- 4 Ch #26 51-52 - - - 7- 8 Ch #27 53-54 - - - 9-10 Ch #28 55-56 - - - 11-12 Ch #29 57-58 - - - 21-22 Ch #30 59-60 - - - 23-24 Ch #31 61-62 - - - 25-26 Ch #32 63-64 - - - 27-28 As built the connector on this patch panel that is cabled to the ERPB-MTG ExtBit Ext_Enb inputs for channels 1:16 has the inverting signals on TOP. Thus all signals that are brought to this connector on this patch panel need to be inverted. Loading the Logic Cell Arrays ----------------------------- The signal names are the following: Load_LCA_1 This is the MIDDLE signal on Steve Pier's CONF_00.tim timing diagram and is carried on DIST Cap Timing input cable pins 23-24 named MTG_7. Load_LCA_2 This is the BOTTOM signal on Steve Pier's CONF_00.tim timing diagram and is carried on DIST Cap Timing input cable pins 25-26 named MTG_8. Load_LCA_3 This is the TOP signal on Steve Pier's CONF_00.tim timing diagram and is carried on DIST Cap Timing input cable pins 27-28 named MTG_9. Stable state before loading is: All three lines are high. To Load the LCA's: Bring signals Load_LCA_1 and Load_LCA_2 low. Wait 3 usec and bring signal Load_LCA_3 low. Wait 3 usec and bring signal Load_LCA_3 high. loads a 0 Wait 3 usec and bring signal Load_LCA_1 high. Wait 3 usec and bring signal Load_LCA_3 low. Wait 3 usec and bring signal Load_LCA_3 high. loads a 1 Wait 3 usec and bring signal Load_LCA_2 high to finish. All three signals are back in the high state.