VSB Timing Measurements 20-JUL-1994 This file contains timing measurements made of various VSB activities using the Motorola MVME-135 and Ariel Hydra-II VSB masters, and a Motorola MVME-214 VME/VSB memory module as a VSB slave. The two masters were set up in the "normal" way, i.e. the 135 was Crate Controller. 1) Timing measurements of DSP VSB DMA transfers: A. First VSB DMA data transfer taken from file taken from file DS_ONLYW.VSB DS_ONL2W.VSB ------------ ------------ Action Time Delta Time Delta ------ ---- ------ ---- ----- Address settled on VSB 0 ns 0 ns PAS* falling edge 185 ns 185 ns 235 ns 235 ns AC rising edge 270 ns 85 ns 320 ns 85 ns Address removed from VSB 285 ns 15 ns 355 ns 15 ns ACK* falling edge 485 ns 200 ns 535 ns 200 ns PAS* rising edge 580 ns 95 ns 630 ns 95 ns [next address presented 610 ns] 660 ns] ACK* rising edge 615 ns 35 ns 665 ns 35 ns B. All subsequent VSB DMA data transfers Address settled on VSB 0 ns 0 ns PAS* falling edge 275 ns 275 ns 275 ns 275 ns AC rising edge 355 ns 80 ns 355 ns 80 ns Address removed from VSB 370 ns 15 ns 370 ns 15 ns ACK* falling edge 570 ns 200 ns 570 ns 200 ns PAS* rising edge 665 ns 95 ns 665 ns 95 ns [next address presented 695 ns] 695 ns] ACK* rising edge 700 ns 35 ns 700 ns 35 ns Note that the first DMA data transfer is faster than all others. The major difference is in the delay between the address appearing on the VSB backplane and the falling edge of PAS*. The address-to-PAS*-valid delay for the first transfer was 185 ns about 50% of the time and 235 ns about 50% of the time. These times are 50 ns apart, i.e. one C40 H1 clock cycle. Using a RPTS instruction to move the data produced the same results. 2) Timing measurements of 68K transfers. For this test I tried to make the 68K transfers go as fast as possible, by using a loop around 60 MOVE.L Dx,(Ax) instructions. The whole thing should have fit into the cache, which was enabled. taken from file 68_ONLYW.VSB ------------ Action Time Delta ------ ---- ------ Address settled on VSB 0 ns PAS* falling edge 135 ns 135 ns AC rising edge 215 ns 80 ns Address removed from VSB 230 ns 15 ns ACK* falling edge 425 ns 200 ns PAS* rising edge 575 ns 95 ns ACK* rising edge 600 ns 35 ns [next address presented 605 ns] I looked at several transfers from this file. They were all identical within +/- 5 ns. The major difference between 68K-based and DSP-based VSB cycles is the delay between address settled on VSB and PAS* rising edge. Recall that the MVSB2400 chip requires an AS* signal from the "on-board logic" in order to generate a PAS*. It is possible that the Hydra-II is for some reason slower to generate this AS* signal to the MVSB2400 chip. Changing "fair" mode makes no difference to these timings (there is no reason that it should). 3) Timing measurements of bus mastership transfer requests A. 68K-to-DSP with 68K quiet, DSP makes 1 data transfer after it gets mastership. taken from file 68_DS_MX.VSB ------------ Action Time Delta ------ ---- ------ BREQ* falling edge 0 ns BUSY* rising edge 505 ns 505 ns BREQ* rising edge \ 670 ns 135 ns BUSY* rising edge / Address settled on VSB 700 ns 30 ns PAS* falling edge 745 ns 45 ns AC rising edge 825 ns 80 ns Address removed from VSB 860 ns 35 ns ACK* falling edge 955 ns 95 ns PAS* rising edge 1070 ns 115 ns ACK* rising edge 1100 ns 30 ns B. DSP-to-68K with DSP quiet, 68K makes 1 data transfer after it gets mastership. taken from file DS_68_MX.VSB ------------ Action Time Delta ------ ---- ------ BREQ* falling edge 0 ns BUSY* rising edge 315 ns 315 ns BUSY* rising edge 450 ns 135 ns BREQ* rising edge 455 ns 5 ns Address settled on VSB 480 ns 25 ns PAS* falling edge 520 ns 40 ns AC rising edge 605 ns 85 ns Address removed from VSB 620 ns 15 ns ACK* falling edge 815 ns 95 ns PAS* rising edge 985 ns 170 ns ACK* rising edge 1020 ns 35 ns C. DSP-to-68K-to-DSP with DSP performing DMA accesses. 68K writes one longword inbetween DSP DMA accesses. taken from file 68INTRDS.VSB ------------ Action Time Delta Comment ------ ---- ------ -------- Address settled on VSB DSP-source DMA write (DSP-based DMA write) 0 ns begins BREQ* falling edge 120 ns 120 ns 68K requests bus before PAS* falling edge 280 ns 160 ns drives PAS* low AC rising edge 360 ns 120 ns Address removed from VSB 370 ns 10 ns BUSY* rising edge 430 ns 50 ns DSP gives up the bus BUSY* falling edge \ 68K becomes bus master BREQ* rising edge > 570 ns 140 ns at the same time the ACK* falling edge / slave responds to DSP PAS* rising edge 670 ns 100 ns DSP(?) finishes cycle ACK* rising edge 700 ns 30 ns Slave acknowledges Address settled on VSB 68K-sourced write (68K-based write) 780 ns 80 ns begins PAS* falling edge 820 ns 40 ns AC rising edge 900 ns 80 ns Address removed from VSB 920 ns 20 ns BREQ* falling edge 970 ns 50 ns DSP requests bus after ACK* falling edge 1115 ns 145 ns 68K drives PAS* low PAS* rising edge 1255 ns 140 ns 68K finishes cycle ACK* rising edge 1290 ns 35 ns Slave acknowledges BUSY* rising edge 1300 ns 10 ns 68K gives up the bus BREQ* rising edge \ 1470 ns 170 ns DSP becomes the bus BUSY* falling edge / master Address settled on VSB DSP-sourced DMA write (DSP-based DMA write) 1500 ns 30 ns begins PAS* falling edge 1550 ns 50 ns AC rising edge 1620 ns 70 ns Address removed from VSB 1640 ns 20 ns ACK* falling edge 1840 ns 200 ns PAS* rising edge 1970 ns 130 ns DSP finishes cycle ACK* rising edge 2000 ns 30 ns Slave acknowledges Note that the Mastership transfer from the DSP to the 68K occurs simultaneously with a DSP DMA write. This DMA write took NO MORE TIME than DSP DMA write which do NOT have a simultaneous Mastership transfer. Also note that the DSP gave up bus mastership while a VSB cycle was still in progress (i.e. while PAS* was active [low]). The cycle was still concluded in an apparently legal manner, presumably by the DSP. The 68K DOES NOT begin its VSB write cycle until the DSP's cycle concludes (even though the 68K becomes bus master before the conclusion of this cycle). According to the VSB Rev. C specification, (Permission 3.3), a Master may release the Data Transfer Bus either during or after its last data transfer. That is, this operation is legal according to the VSB specification. Also, Section 4.4 of the MVSB2400 chip User's Manual indicates that the Requester will not assert MYBUS* to the on-board logic until both BGIN* has been asserted and PAS* has been negated. When the DSP re-requests bus mastership from the 68K, note that the 68K does not actually release mastership until AFTER it has finished its (single) data transfer (i.e. not during the transfer). This is also legal according to the VSB spec. It is not clear why the 68K acts differently. It may be because it is the system controller, or it may have to do with when the competing requester requests the bus. Note that the 68K had requested the bus before the DSP had driven PAS* low, while the DSP requested the bus after the 68K had driven PAS* low. I ran this test several times, but never saw a transaction different from the one described above. Finally, note that the delay between valid address and PAS* for the DSP-sourced DMA transfer immediately following the mastership transfer to the DSP was very short. This helps offset the time spent in transferring mastership between the 68K and the DSP. It appears that both mastership transfers are "for free." The transfer from DSP-to-68K occurs during a data transfer cycle, so it is clearly not costing time. The transfer from 68K-to-DSP occurs after a data transfer cycle (at a cost of 180 ns), but the subsequent DSP data transfer is about 200 ns shorter due mostly to a reduction in the address-to-PAS* delay).