Setup of the VSB Masters for the Level 15 Calorimeter Trigger --------------------------------------------------------------- Rev. 23-JUNE-1994 Setup of the MVME135 -------------------- The MVME135 is setup as the Controller of the VSB. The MVME135 or any of the three Hydra-II's can become the Master of the VSB. For the MVME135 the only setup required is to load its MVSB2400 Control Status Register. This register is located at address $FFFA0000 and can be loaded directly by the 68020 on the MVME135. It should be loaded as a 16 bit word. Value Bit Name R or RW Loaded Function --- ------ ------- -------- ------------------------------------- D0 SCON* RW 0 Clearing to 0 enables operation as the VSB bus Controller. D1 N.C. - 0 No Connection, bit is not defined. D2 BLOCKEN* RW 1 Clearing to 0 enables block transfers. D3 TEN* RW 1 Clearing to 0 enables 68010 mode. D4 BOUNCE RW 0 Clearing to 0 disables address bounce mode. D5 READONLY* RW 1 Clearing to 0 enables readonly mode. D6 MASTEREN* RW 0 Clearing to 0 enables enables the MVSB2400 to request to become VSB Master when it needs to. D7 N.C. - 0 No Connection, bit is not defined. D8 ENTO0* RW 1 These two bits enable the VSB bus Master D9 ENTO1* RW 0 to timeout after 128 usec. D10 FAIR* RW 0 Clearing to 0 enables the "Fair mode" of requesting the VSB bus. D11 WRERR* R 1 If this bit is a 0 then the most recent error was an attempt to write when in readonly mode. Reading this register set this bit to a 1. D12 TIMEOUT* R 1 If this bit is a 0 then the most recent error was a bus timeout. Reading this register set this bit to a 1. D13 ASACK0* R 1 These bit reflect the state of the VSB D14 ASACK1* R 1 ASACK0* and ASACK1* at the time of the last bus error. D15 ERR* R 1 If this bit is a 0 then the VSB ERR* signal has been asserted during the course of a VSB cycle. Reading this register set this bit to a 1. Thus it looks like loading the 16 bit word $F92C into location $FFFA0000 is the proper setup for the MVME135. Setup of the Hydra-II's ----------------------- The Hydra-II card also uses a MVSB2400 chip to implement the VSB bus. In addition to the functionality provided by the MVSB2400 chip the Hydra-II also has a VSB Transfer Control Register as part of its VSB setup. Note that the VSB Transfer Control Register is not part of the MVSB2400 chip. On the Hydra-II the VSB bus is selected by activating Local Strobe 0 (*LSTRB0) of DSP#2. For normal operation the Local Memory Interface Control Register (MICR) of DSP#2 must be set to 1DCC4000h. DSP addresses in the range 0030 0000h through 3FFF FFFFh are mapped to VSB addresses in the range $00C0 0000 through $FFFF FFFC . The lowest two address bits of the VSB bus (A0, A1) are supplied by the VSB Transfer Control Register. Local address bit 0 of DSP#2 is connected to VSB bus address bit 2 and so on. On the Hydra-II card the VSB bus is controlled by two registers: the Hydra-II VSB Transfer Control Register (VSBTCR) and the MVSB2400 Control and Status Register. The Hydra-II's VSB Transfer Control Register The VSBTCR has 8 read-write bits and 3 read only bits. These are listed below along with the typical values that we need to load for operation in the L15 Cal Trig. Value Bit Name R or RW Loaded Function --- ------ ------- -------- ------------------------------------- D0 SIZE0 RW 0 These bits determine the size of the VSB D1 SIZE1 RW 0 data transfer. 0,0 --> Quad-Byte. D2 SPACE0* RW 0 These bits select the VSB Address Space. D3 SPACE1* RW 0 0,0 --> the default "system address space". D4 VSBEN RW 0 Clearing this bit to 0 disables the VSB or 1 interface. Setting this bit to a 1 enables all DSP#2 *LSTRB0's to generate VSB cycles. D5 VSBA0 RW 0 VSB address lines A0 and A1 should be set D6 VSBA1 RW 0 to 0 for aligned quad-byte transfers. D7 ADREN RW 0 Clearing this bit to 0 disables access to the MVSB2400 Address Decode Register. We never want to access this register. D8 GA0 R 0 These are readonly locations where the D9 GA1 R 0 DSP#2 can read the Geographic Address of D10 GA2 R 0 the VSB Slot that it is plugged into. Because we will only use aligned quad-byte transfers and because we never want to change the MVSB2400 Address Decode Register, it looks like the only two values that we will ever need to load into the Hydra-II's VSB Transfer Control register are: 0000 0010h to enable the Hydra-II to generate VSB cycles when its DSP#2 Local Strobe 0 goes active. And 0000 0000h to prevent the Hydra-II from generating VSB cycles when its DSP#2 Local Strobe 0 goes active. Note that the VSBTCR is cleared to all 0's whenever the Hydra-II is reset. This disables the Hydra-II from generating any VSB bus cycles. The process of loading (or reading from) the VSB Transfer Control Register is rather cumbersome. Basically the DSP#2 IIOF0 line is taken low, then any access to DSP#2 addresses 00300000h through 3FFFFFFFh will result in an access to the VSBTCR. The steps to do this are: Bit 0 (FUNC0) of the IIF Reg must be cleared to a 0 ---> IIOF0 is I/O pin. Bit 1 (TYPE0) of the IIF Reg must be set to a 1 ---> IIOF0 is an output pin. Bit 2 (FLAG0) of the IIF Reg must be cleared to a 0 ---> IIOF0 output low. The VSBTCR does not generate an acknowledge when accessed so the Local MICR must be modified to use the DSP's wait-state generator during the VSBTCR access. Thus change the Local Memory Interface Control Register from 1DCC4000h to 1DCC4010h for the VSBTCR access. Once the above steps are taken then any DSP#2 access to the address range 00300000h through 3FFFFFFFh will result in an access to the VSB Transfer Control Register. Lets always use address 3ffe8000h (i.e. the same address used for the MVSB2400 Control-Status Register) for the VSBTCR. This has the advantage that the VSBTCR is at a valid VSB address. This is important, because reading an INVALID VSB address can cause the VSB2400 (and the whole VSB bus) to hang if the MVSB2400 is not programmed to time out if the VSB cycle does not complete within some fixed time. Also there may be other ways to hang the VSB bus when invalid VSB locations are addressed (i.e. problems granting bus mastership, etc.). After the access to the VSBTCR the original value in the Local MICR must be restored and the original value in the IIF Register must be restored. Questions about access to the VSBTCR: Because the Local MICR is changed for the duration of the access to the VSBTCR, must the code that is making this access execute from the DSP's Global SRAM ?? The Hydra-II's MVSB2400 Control and Status Register The setup of the MVSB2400 Control and Status Register on the Hydra-II is similar to the setup on the MVME135 card. The principal difference is that we do not want the MVSB2400's on the Hydra-II's to be enabled to be the VSB bus Controllers. Thus bit 0 of this MVSB2400 Status and Control Register should always be loaded with a 1. Additionally, the ENTO0* and ENTO1* signals are not used on non-Controller VSB interfaces. They can be programmed to any value, the value we choose is both high (i.e. never time out). See the WARNING on page 4-17 of the MVSB2400 VSBchip User's Manual. Thus it looks like loading the value 0000 FB2D h into location 3FFE 8000 h is the proper setup for the Hydra-II's. Note that the address of the MVSB2400 Status and Control Register ( i.e. $FFFA0000 ) when shifted two places to map into a DSP#2 address becomes 3FFE 8000h. I expect that the VSB bus needs to be enabled as described above before the MVSB2400 Status and Control Register is loaded. Also note that the Hydra-II's MVSB2400's are reset whenever the DSP#2 is reset. It is extremely important to avoid attempting VSB bus cycles before the MVSB2400 CSR is programmed. Recall that the VSB bus can hang if the MVSB2400 is not programmed to generate time-outs (and an invalid VSB access is attempted). Since there is no reason to attempt VSB cycles before the CSR is programmed let's NEVER do this. Note that a non-obvious way to generate VSB cycles is to have a MEM(ory) window in the simulator looking at VSB addresses. Many simulator functions (even something as seemingly harmless as re-sizing or moving a window) cause the simulator to update all of the information visible on the screen (including the data in a MEM(ory) window, which requires reading the specified memory locations and thus generating VSB cycles).