******************************* * M103 PATCH PANEL * * FOR THE * * LEVEL 1.5 TRIGGER FRAMEWORK * ******************************* 22-APR-1992 15-JUN-1992 GENERAL DESCRIPTION ------------------- This file is the mechanical and electrical specification for the patch panel in rack M103. This patch panel is used by the Level 1.5 Trigger Framework both to communicate with the Level 1 Trigger Framework and as a front-to-back passthrough panel. DETAILED DESCRIPTION OF EACH SECTION ------------------------------------ 1. Level 1.5 Input Terms (ANSWER/DONE) to Receiving MTG The Level 1.5 Trigger Framework receives 32 input Terms from Level 1.5 Subsystems (e.g. Muon or TRD). Each Term consists of an ANSWER signal and a DONE signal. These signals are transmitted as differential ECL signals. The current definition reserves the 16 Level 1.5 Terms 0..15 for the Muon Level 1.5 Subsystem, and leaves the 16 Level 1.5 Terms 16..31 free for use by other subsystems. The current definition also requires the 16 Muon Level 1.5 Term 0..15 ANSWER signals to be transmitted on a 34-conductor Twist'n'Flat cable, and the 16 Muon Level 1.5 Term 0..15 DONE signals to be transmitted on a separate 34-conductor Twist'n'Flat cable. See the formal definition of the Level 1.5 Trigger Framework - Level 1.5 Muon Subsystem interface for the complete specification. These signals must be combined on one 64-pin AMP header for transmittal via a 64-conductor Twist'n'Flat cable to one of the 64-pin AMP input connectors on the Receiving MTG. Current thought is that the 16 Level 1.5 Terms 16..32, which are currently free for use by other subsystems, should be received and mapped in identical fashion. The patch panel must therefore map 16 Level 1.5 Term ANSWER signals from a single 34-pin AMP header and 16 Level 1.5 Term DONE signals from another 34-pin AMP header to a 64-pin AMP header, in a fashion suitable for input to an MTG. This mapping must be done twice, as described above. The wrapping is done with wire-wrap wire connecting the pins as described below. Following is a chart which describes the required mapping for the Level 1.5 Terms 0..15 (the Level 1.5 Muon terms). MAPPING OF LEVEL 1.5 TERMS 0..15 ANSWER AND DONE TO RECEIVING MTG ================================================================= J1: 64-PIN J2: 34-PIN J3: 34-PIN HEADER FOR HEADER CONTAINING HEADER CONTAINING ENABLE AND BIT LEVEL 1.5 TERM LEVEL 1.5 TERM TO RECEIVING DONE SIGNALS FROM ANSWER SIGNALS FROM MTG CHAN 1..16 LEVEL 1.5 SUBSYSTEMS LEVEL 1.5 SUBSYSTEMS -------------- -------------------- -------------------- J1-63 (NENA1) J2-1 (Term 0 Done NINV) J1-64 (IENA1) J2-2 (Term 0 Done INV) J1-61 (NBIT1) J3-1 (Term 0 Ans NINV) J1-62 (IBIT1) J3-2 (Term 0 Ans INV) J1-59 (NBIT2) J3-3 (Term 1 Ans NINV) J1-60 (IBIT2) J3-4 (Term 1 Ans INV) J1-57 (NENA2) J2-3 (Term 1 Done NINV) J1-58 (IENA2) J2-4 (Term 1 Done INV) J1-55 (NENA3) J2-5 (Term 2 Done NINV) J1-56 (IENA3) J2-6 (Term 2 Done INV) J1-53 (NBIT3) J3-5 (Term 2 Ans NINV) J1-54 (IBIT3) J3-6 (Term 2 Ans INV) J1-51 (NBIT4) J3-7 (Term 3 Ans NINV) J1-52 (IBIT4) J3-8 (Term 3 Ans INV) J1-49 (NENA4) J2-7 (Term 3 Done NINV) J1-50 (IENA4) J2-8 (Term 3 Done INV) J1-47 (NENA5) J2-9 (Term 4 Done NINV) J1-48 (IENA5) J2-10 (Term 4 Done INV) J1-45 (NBIT5) J3-9 (Term 4 Ans NINV) J1-46 (IBIT5) J3-10 (Term 4 Ans INV) J1-43 (NBIT6) J3-11 (Term 5 Ans NINV) J1-44 (IBIT6) J3-12 (Term 5 Ans INV) J1-41 (NENA6) J2-11 (Term 5 Done NINV) J1-42 (IENA6) J2-12 (Term 5 Done INV) J1-39 (NENA7) J2-13 (Term 6 Done NINV) J1-40 (IENA7) J2-14 (Term 6 Done INV) J1-37 (NBIT7) J3-13 (Term 6 Ans NINV) J1-38 (IBIT7) J3-14 (Term 6 Ans INV) J1-35 (NBIT8) J3-15 (Term 7 Ans NINV) J1-36 (IBIT8) J3-16 (Term 7 Ans INV) J1-33 (NENA8) J2-15 (Term 7 Done NINV) J1-34 (IENA8) J2-16 (Term 7 Done INV) J1-31 (NENA9) J2-17 (Term 8 Done NINV) J1-32 (IENA9) J2-18 (Term 8 Done INV) J1-29 (NBIT9) J3-17 (Term 8 Ans NINV) J1-30 (IBIT9) J3-18 (Term 8 Ans INV) J1-27 (NBIT10) J3-19 (Term 9 Ans NINV) J1-28 (IBIT10) J3-20 (Term 9 Ans INV) J1-25 (NENA10) J2-19 (Term 9 Done NINV) J1-26 (IENA10) J2-20 (Term 9 Done INV) J1-23 (NENA11) J2-21 (Term 10 Done NINV) J1-24 (IENA11) J2-22 (Term 10 Done INV) J1-21 (NBIT11) J3-21 (Term 10 Ans NINV) J1-22 (IBIT11) J3-22 (Term 10 Ans INV) J1-19 (NBIT12) J3-23 (Term 11 Ans NINV) J1-20 (IBIT12) J3-24 (Term 11 Ans INV) J1-17 (NENA12) J2-23 (Term 11 Done NINV) J1-18 (IENA12) J2-24 (Term 11 Done INV) J1-15 (NENA13) J2-25 (Term 12 Done NINV) J1-16 (IENA13) J2-26 (Term 12 Done INV) J1-13 (NBIT13) J3-25 (Term 12 Ans NINV) J1-14 (IBIT13) J3-26 (Term 12 Ans INV) J1-11 (NBIT14) J3-27 (Term 13 Ans NINV) J1-12 (IBIT14) J3-28 (Term 13 Ans INV) J1-9 (NENA14) J2-27 (Term 13 Done NINV) J1-10 (IENA14) J2-28 (Term 13 Done INV) J1-7 (NENA15) J2-29 (Term 14 Done NINV) J1-8 (IENA15) J2-30 (Term 14 Done INV) J1-5 (NBIT15) J3-29 (Term 14 Ans NINV) J1-6 (IBIT15) J3-30 (Term 14 Ans INV) J1-3 (NBIT16) J3-31 (Term 15 Ans NINV) J1-4 (IBIT16) J3-32 (Term 15 Ans INV) J1-1 (NENA16) J2-31 (Term 15 Done NINV) J1-2 (IENA16) J2-32 (Term 15 Done INV) The mapping of Level 1.5 Terms 16..31 to the Receiving MTG input is identical to the above mapping. Following is the mapping of Level 1.5 Terms 16..31 to the Receiving MTG input. MAPPING OF LEVEL 1.5 TERMS 16..32 ANSWER AND DONE TO RECEIVING MTG ================================================================== J4: 64-PIN J5: 34-PIN J6: 34-PIN HEADER FOR HEADER CONTAINING HEADER CONTAINING ENABLE AND BIT LEVEL 1.5 TERM LEVEL 1.5 TERM TO RECEIVING DONE SIGNALS FROM ANSWER SIGNALS FROM MTG CHAN 17..32 LEVEL 1.5 SUBSYSTEMS LEVEL 1.5 SUBSYSTEMS --------------- -------------------- -------------------- J4-63 (NENA17) J5-1 (Term 16 Done NINV) J4-64 (IENA17) J5-2 (Term 16 Done INV) J4-61 (NBIT17) J6-1 (Term 16 Ans NINV) J4-62 (IBIT17) J6-2 (Term 16 Ans INV) J4-59 (NBIT18) J6-3 (Term 17 Ans NINV) J4-60 (IBIT18) J6-4 (Term 17 Ans INV) J4-57 (NENA18) J5-3 (Term 17 Done NINV) J4-58 (IENA18) J5-4 (Term 17 Done INV) J4-55 (NENA19) J5-5 (Term 18 Done NINV) J4-56 (IENA19) J5-6 (Term 18 Done INV) J4-53 (NBIT19) J6-5 (Term 18 Ans NINV) J4-54 (IBIT19) J6-6 (Term 18 Ans INV) J4-51 (NBIT20) J6-7 (Term 19 Ans NINV) J4-52 (IBIT20) J6-8 (Term 19 Ans INV) J4-49 (NENA20) J5-7 (Term 19 Done NINV) J4-50 (IENA20) J5-8 (Term 19 Done INV) J4-47 (NENA21) J5-9 (Term 20 Done NINV) J4-48 (IENA21) J5-10 (Term 20 Done INV) J4-45 (NBIT21) J6-9 (Term 20 Ans NINV) J4-46 (IBIT21) J6-10 (Term 20 Ans INV) J4-43 (NBIT22) J6-11 (Term 21 Ans NINV) J4-44 (IBIT22) J6-12 (Term 21 Ans INV) J4-41 (NENA22) J5-11 (Term 21 Done NINV) J4-42 (IENA22) J5-12 (Term 21 Done INV) J4-39 (NENA23) J5-13 (Term 22 Done NINV) J4-40 (IENA23) J5-14 (Term 22 Done INV) J4-37 (NBIT23) J6-13 (Term 22 Ans NINV) J4-38 (IBIT23) J6-14 (Term 22 Ans INV) J4-35 (NBIT24) J6-15 (Term 23 Ans NINV) J4-36 (IBIT24) J6-16 (Term 23 Ans INV) J4-33 (NENA24) J5-15 (Term 23 Done NINV) J4-34 (IENA24) J5-16 (Term 23 Done INV) J4-31 (NENA25) J5-17 (Term 24 Done NINV) J4-32 (IENA25) J5-18 (Term 24 Done INV) J4-29 (NBIT25) J6-17 (Term 24 Ans NINV) J4-30 (IBIT25) J6-18 (Term 24 Ans INV) J4-27 (NBIT26) J6-19 (Term 25 Ans NINV) J4-28 (IBIT26) J6-20 (Term 25 Ans INV) J4-25 (NENA26) J5-19 (Term 25 Done NINV) J4-26 (IENA26) J5-20 (Term 25 Done INV) J4-23 (NENA27) J5-21 (Term 26 Done NINV) J4-24 (IENA27) J5-22 (Term 26 Done INV) J4-21 (NBIT27) J6-21 (Term 26 Ans NINV) J4-22 (IBIT27) J6-22 (Term 26 Ans INV) J4-19 (NBIT28) J6-23 (Term 27 Ans NINV) J4-20 (IBIT28) J6-24 (Term 27 Ans INV) J4-17 (NENA28) J5-23 (Term 27 Done NINV) J4-18 (IENA28) J5-24 (Term 27 Done INV) J4-15 (NENA29) J5-25 (Term 28 Done NINV) J4-16 (IENA29) J5-26 (Term 28 Done INV) J4-13 (NBIT29) J6-25 (Term 28 Ans NINV) J4-14 (IBIT29) J6-26 (Term 28 Ans INV) J4-11 (NBIT30) J6-27 (Term 29 Ans NINV) J4-12 (IBIT30) J6-28 (Term 29 Ans INV) J4-9 (NENA30) J5-27 (Term 29 Done NINV) J4-10 (IENA30) J5-28 (Term 29 Done INV) J4-7 (NENA31) J5-29 (Term 30 Done NINV) J4-8 (IENA31) J5-30 (Term 30 Done INV) J4-5 (NBIT31) J6-29 (Term 30 Ans NINV) J4-6 (IBIT31) J6-30 (Term 30 Ans INV) J4-3 (NBIT32) J6-31 (Term 31 Ans NINV) J4-4 (IBIT32) J6-32 (Term 31 Ans INV) J4-1 (NENA32) J5-31 (Term 31 Done NINV) J4-2 (IENA32) J5-32 (Term 31 Done INV) 2. Level 1.5 SpecTrig DONE/ANS and L1 ST Fired to the L1.5 Veto/Conf MTG The 16 time-multiplexed Level 1.5 Specific Trigger 0..15 DONE/ANSWER signals, and the 16 corresponding Level 1 Specific Trigger 0..15 Fired signals must be mapped in parallel to each of the two input connectors of an MTG. Since the connectors are identical, and the signals they will receive are also identical, we will only do the mapping in wire wrap once and use a cable which has two connectors in parallel at the MTG end. This mapping is identical to the mapping described above. Following is the mapping of Level 1.5 Specific Trigger 0..15 DONE/ANSWER signals and the 16 corresponding Level 1 Specific Trigger 0..15 Fired signals to the Veto/Confirm MTG. MAPPING OF L1.5 ST DONE/ANSWER AND L1 ST FIRED TO L1.5 VETO/CONF ============================================================= J7: 64-PIN HEADER FOR ENABLE AND BIT TO VETO/CONF MTG CHANNELS J8: 34-PIN J9: 34-PIN 1..16 AND HEADER CONTAINING HEADER CONTAINING 17..32 IN LEVEL 1 SPEC TRIG LEVEL 1.5 SPEC TRIG PARALLEL FIRED SIGNALS DONE/ANSWER SIGNALS -------------- ----------------- ------------------ J7-63 (NENA1/17) J9-1 (L15 ST 0 D/A NINV) J7-64 (IENA1/17) J9-2 (L15 ST 0 D/A INV) J7-61 (NBIT1/17) J8-1 (ST 0 Fired NINV) J7-62 (IBIT1/17) J8-2 (ST 0 Fired INV) J7-59 (NBIT2/18) J8-3 (ST 1 Fired NINV) J7-60 (IBIT2/18) J8-4 (ST 1 Fired INV) J7-57 (NENA2/18) J9-3 (L15 ST 1 D/A NINV) J7-58 (IENA2/18) J9-4 (L15 ST 1 D/A INV) J7-55 (NENA3/19) J9-5 (L15 ST 2 D/A NINV) J7-56 (IENA3/19) J9-6 (L15 ST 2 D/A INV) J7-53 (NBIT3/19) J8-5 (ST 2 Fired NINV) J7-54 (IBIT3/19) J8-6 (ST 2 Fired INV) J7-51 (NBIT4/20) J8-7 (ST 3 Fired NINV) J7-52 (IBIT4/20) J8-8 (ST 3 Fired INV) J7-49 (NENA4/20) J9-7 (L15 ST 3 D/A NINV) J7-50 (IENA4/20) J9-8 (L15 ST 3 D/A INV) J7-47 (NENA5/21) J9-9 (L15 ST 4 D/A NINV) J7-48 (IENA5/21) J9-10 (L15 ST 4 D/A INV) J7-45 (NBIT5/21) J8-9 (ST 4 Fired NINV) J7-46 (IBIT5/21) J8-10 (ST 4 Fired INV) J7-43 (NBIT6/22) J8-11 (ST 5 Fired NINV) J7-44 (IBIT6/22) J8-12 (ST 5 Fired INV) J7-41 (NENA6/22) J9-11 (L15 ST 5 D/A NINV) J7-42 (IENA6/22) J9-12 (L15 ST 5 D/A INV) J7-39 (NENA7/23) J9-13 (L15 ST 6 D/A NINV) J7-40 (IENA7/23) J9-14 (L15 ST 6 D/A INV) J7-37 (NBIT7/23) J8-13 (ST 6 Fired NINV) J7-38 (IBIT7/23) J8-14 (ST 6 Fired INV) J7-35 (NBIT8/24) J8-15 (ST 7 Fired NINV) J7-36 (IBIT8/24) J8-16 (ST 7 Fired INV) J7-33 (NENA8/24) J9-15 (L15 ST 7 D/A NINV) J7-34 (IENA8/24) J9-16 (L15 ST 7 D/A INV) J7-31 (NENA9/25) J9-17 (L15 ST 8 D/A NINV) J7-32 (IENA9/25) J9-18 (L15 ST 8 D/A INV) J7-29 (NBIT9/25) J8-17 (ST 8 Fired NINV) J7-30 (IBIT9/25) J8-18 (ST 8 Fired INV) J7-27 (NBIT10/26) J8-19 (ST 9 Fired NINV) J7-28 (IBIT10/26) J8-20 (ST 9 Fired INV) J7-25 (NENA10/26) J9-19 (L15 ST 9 D/A NINV) J7-26 (IENA10/26) J9-20 (L15 ST 9 D/A INV) J7-23 (NENA11/27) J9-21 (L15 ST 10 D/A NINV) J7-24 (IENA11/27) J9-22 (L15 ST 10 D/A INV) J7-21 (NBIT11/27) J8-21 (ST 10 Fired NINV) J7-22 (IBIT11/27) J8-22 (ST 10 Fired INV) J7-19 (NBIT12/28) J8-23 (ST 11 Fired NINV) J7-20 (IBIT12/28) J8-24 (ST 11 Fired INV) J7-17 (NENA12/28) J9-23 (L15 ST 11 D/A NINV) J7-18 (IENA12/28) J9-24 (L15 ST 11 D/A INV) J7-15 (NENA13/29) J9-25 (L15 ST 12 D/A NINV) J7-16 (IENA13/29) J9-26 (L15 ST 12 D/A INV) J7-13 (NBIT13/29) J8-25 (ST 12 Fired NINV) J7-14 (IBIT13/29) J8-26 (ST 12 Fired INV) J7-11 (NBIT14/30) J8-27 (ST 13 Fired NINV) J7-12 (IBIT14/30) J8-28 (ST 13 Fired INV) J7-9 (NENA14/30) J9-27 (L15 ST 13 D/A NINV) J7-10 (IENA14/30) J9-28 (L15 ST 13 D/A INV) J7-7 (NENA15/31) J9-29 (L15 ST 14 D/A NINV) J7-8 (IENA15/31) J9-30 (L15 ST 14 D/A INV) J7-5 (NBIT15/31) J8-29 (ST 14 Fired NINV) J7-6 (IBIT15/31) J8-30 (ST 14 Fired INV) J7-3 (NBIT16/32) J8-31 (ST 15 Fired NINV) J7-4 (IBIT16/32) J8-32 (ST 15 Fired INV) J7-1 (NENA16/32) J9-31 (L15 ST 15 D/A NINV) J7-2 (IENA16/32) J9-32 (L15 ST 15 D/A INV)