TITLE Cable Receiver Card Token Grabber PATTERN CRC Token Grabber Revision 3 REVISION 3.01 AUTHOR Level 1.5 Calorimeter Trigger (Steve Gross) COMPANY MSU HEP DATE 18-MAR-1994 ; The detailed description of this device is at the end of this file. CHIP CRCToken PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 CtrClock /NC_AK_1 /NC_AK_2 /NC_AK_3 /NC_AK_4 NC_In_5 NC_In_6 NC_ClkIn ;9 10 11 12 13 14 15 16 VMERESET GND /Glob_OE /CtrBit_3 /CtrBit_2 /CtrBit_1 /CtrBit_0 /CREQ_4 ;17 18 19 20 /CREQ_3 /CREQ_2 /CREQ_1 Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For both latched and unlatched outputs, this is equivalent to ; programmable polarity (since the 16V8 does not have SET and RESET ; inputs on the D-latches in the macrocells). EQUATIONS ; /Glb_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). CtrBit_0 := /CtrBit_0 ; Count Register 0 + VMERESET ; Bit value 1 ; Recall that this is a synchronous ; counter. The following "previous ; state" Counter values should cause ; a "next state" with CtrBit_0 = 1: ; 0, 2, 4, 6, 8, 10, 12, 14 ; This term is always output enabled ; and fed back to the matrix. It is ; clocked by the common clock on pin 1 ; This term is also forced to 1 by ; VMERESET CtrBit_1 := /CtrBit_1 * CtrBit_0 ; Count Register 1 + CtrBit_1 * /CtrBit_0 ; Bit value 2 + VMERESET ; Recall that this is a synchronous ; counter. The following "previous ; state" Counter values should cause ; a "next state" with CtrBit_1 = 1: ; 1, 2, 5, 6, 9, 10, 13, 14 ; This term is always output enabled ; and fed back to the matrix. It is ; clocked by the common clock on pin 1 ; This term is also forced to 1 by ; VMERESET CtrBit_2 := /CtrBit_2 * CtrBit_1 * CtrBit_0 ; Count Register 2 + CtrBit_2 * /CtrBit_1 ; Bit Value 4 + CtrBit_2 * /CtrBit_0 + VMERESET ; Recall that this is a synchronous ; counter. The following "previous ; state" Counter values should cause ; a "next state" with CtrBit_2 = 1: ; 3, 4, 5, 6, 11, 12, 13, 14 ; This term is always output enabled ; and fed back to the matrix. It is ; clocked by the common clock on pin 1 ; This term is also forced to 1 by ; VMERESET CtrBit_3 := /CtrBit_3 * CtrBit_2 * CtrBit_1 * CtrBit_0 ; Count Reg 3 + CtrBit_3 * /CtrBit_2 ; Bit Value 8 + CtrBit_3 * /CtrBit_1 + CtrBit_3 * /CtrBit_0 + VMERESET ; Recall that this is a synchronous ; counter. The following "previous ; state" Counter values should cause ; a "next state" with CtrBit_3 = 1: ; 7, 8, 9, 10, 11, 12, 13, 14 ; This term is always output enabled ; and fed back to the matrix. It is ; clocked by the common clock on pin 1 ; This term is also forced to 1 by ; VMERESET CREQ_1 = GND ; This is the CREQ_1 term. It is CREQ_1.TRST = /CtrBit_3 ; set to "0" and output enabled ; when the Counter MSB is low. ; Half of the time it should ; be output enabled. Recall that ; the actual output is inverted ; so when CREQ_1 is output enabled ; the /CREQ_1 pin is driven HIGH. ; It is not output enabled when ; VMERESET is active. CREQ_2 = GND ; This is the CREQ_2 term. It is CREQ_2.TRST = /CtrBit_3 ; set to "0" and output enabled ; when the Counter MSB is low. ; Half of the time it should ; be output enabled. Recall that ; the actual output is inverted ; so when CREQ_2 is output enabled ; the /CREQ_2 pin is driven HIGH. ; It is not output enabled when ; VMERESET is active. CREQ_3 = GND ; This is the CREQ_3 term. It is CREQ_3.TRST = /CtrBit_3 ; set to "0" and output enabled ; when the Counter MSB is low ; Half of the time it should ; be output enabled. Recall that ; the actual output is inverted ; so when CREQ_3 is output enabled ; the /CREQ_3 pin is driven HIGH. ; It is not output enabled when ; VMERESET is active. CREQ_4 = GND ; This is the CREQ_4 term. It is CREQ_4.TRST = /CtrBit_3 ; set to "0" and output enabled ; when the Counter MSB is low. ; Half of the time it should ; be output enabled. Recall that ; the actual output is inverted ; so when CREQ_4 is output enabled ; the /CREQ_4 pin is driven HIGH. ; It is not output enabled when ; VMERESET is active. ; ; Description of the CRC Token Grabber Revision 3 ; ; This circuit uses a 16V8 type of PAL. There are some special ; connections required to plug this 16V8 PAL into a Token Grabber ; PAL socket on the CRC. ; The following table shows the connections used with this CRCTOK device. ; ; Pin Signal Description PCB Connection ; --- ---------------------------- ---------------------------------- ; ; 1 Counter Clock This pin should be tied to pin #7 ; on the CRC. ; ; 2 /CACK_1 This pin should be tied to the ; /CRDY signal from Comm Port #1 ; It is not used in this PAL. ; ; 3 /CACK_2 This pin should be tied to the ; /CRDY signal from Comm Port #2 ; It is not used in this PAL. ; ; 4 /CACK_3 This pin should be tied to the ; /CRDY signal from Comm Port #3 ; It is not used in this PAL. ; ; 5 /CACK_4 This pin should be tied to the ; /CRDY signal from Comm Port #4 ; It is not used in this PAL. ; ; 6 Not Connected Not connected to any PCB signal ; ; 7 Not Connected Not connected to any PCB signal ; ; 8 Grabber Clock This pin should be tied to the ; Grabber Clock on the PCB. It ; should also be tied to pin #1. ; ; 9 VMERESET This pin should be tied to the ; VME RESET signal from the VME ; backplane through a "jumper wire" ; ; 10 Device GROUND This pin should be tied to the ; PCB GROUND plane ; ; 11 Glob_OE This pin should be tied LOW on the ; CRC PCB. ; ; 12 /Counter Bit 0 Not connected to any PCB signal ; ; 13 /Counter Bit 1 Not connected to any PCB signal ; ; 14 /Counter Bit 2 Not connected to any PCB signal ; ; 15 /Counter Bit 3 Not connected to any PCB signal ; ; 16 /CREQ_4 This pin should be tied to the ; /CSTRB signal for EM Copy #1 via ; a series-terminating resistor, and ; also a resistor to VEE ; ; 17 /CREQ_3 This pin should be tied to the ; /CSTRB signal for EM Copy #2 via ; a series-terminating resistor, and ; also a resistor to VEE ; ; 18 /CREQ_2 This pin should be tied to the ; /CSTRB signal for Tot Copy #1 via ; a series-terminating resistor, and ; also a resistor to VEE ; ; 19 /CREQ_1 This pin should be tied to the ; /CSTRB signal for Tot Copy #2 via ; a series-terminating resistor, and ; also a resistor to VEE ; ; 20 Device Vcc This pin should be tied to the ; PCB VCC plane ; ; ; Operation of the CRC Token Grabber Revision 3 PAL ; ------------------------------------------------- ; ; This PAL simply consists of a divide-by-16 counter and some output ; drivers. When the MSB of the counter is low, the output drivers will ; try to force a high (+5V) on the /CREQ lines to the 'C40. This should ; not bother the C40, because the /CREQ line from the 'C40 only goes low ; when it is trying to request a token. ; ; When the MSB of the counter is high, the output drivers will shut off. ; An external resistor to VEE will try to pull the /CREQ line to the 'C40 ; low in order to request the token. If we already have the token, the 'C40 ; will not notice this token request, because it is driving the /CREQ line ; high. If we do not have the token, the 'C40 will try to give us the token. ; We will accept the token when the counter MSB goes low and we drive +5 ; onto the /CREQ line. ; ; Schematic of PAL-to-C40 connection ; ---------------------------------- ; ) ; CRC side ( Hydra side ; ) ; ( +5.0V ; ) ----- ; ( | ; *** CRC *** ) / ; ( \ ; \ ) / .----- ; |\ 750 ohm ( \ | C40 ; | \ ) | | ; "0"---------------------| O----\/\/\/\----*-(-----*------| /CREQ ; | / | ) | ; |/| \ ( | ; / | / | ; | \ `------ ; | / 8100 ohm ; Counter MSB ----' \ ; | ; | ; ----- ; -4.5V ; ; ; Following is the SIMULATION data for the CRC Token Grabber PAL ; SIMULATION ; Enable tracing of several signals TRACE_ON VMERESET CtrBit_0 CtrBit_1 CtrBit_2 CtrBit_3 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Enable global OE (done in wiring on PCB) SETF Glob_OE ; Set the inputs to the normal quiescent state SETF /VMERESET /CtrClock ; Enable VMERESET SETF VMERESET ; Clock VMERESET in. The Flip-Flops should all be set to 1 SETF CtrClock SETF /CtrClock ; Check the Counter Flip-Flops: Count should be 1111 CHECK CtrBit_3 CtrBit_2 CtrBit_1 CtrBit_0 ; Now provide another clock. VMERESET is still active so count should ; remain 1111 SETF CtrClock SETF /CtrClock CHECK CtrBit_3 CtrBit_2 CtrBit_1 CtrBit_0 ; OK now disable VMERESET SETF /VMERESET ; Start Counting: should count from 0000 to 1111 and then back to 0000 ; Go to 0000, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 /CtrBit_2 /CtrBit_1 /CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0001, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 /CtrBit_2 /CtrBit_1 CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0010, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 /CtrBit_2 CtrBit_1 /CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0011, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 /CtrBit_2 CtrBit_1 CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0100, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 CtrBit_2 /CtrBit_1 /CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0101, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 CtrBit_2 /CtrBit_1 CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0110, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 CtrBit_2 CtrBit_1 /CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 0111, all /CREQ lines should be high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 CtrBit_2 CtrBit_1 CtrBit_0 /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Go to 1000, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 /CtrBit_2 /CtrBit_1 /CtrBit_0 ; Go to 1001, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 /CtrBit_2 /CtrBit_1 CtrBit_0 ; Go to 1010, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 /CtrBit_2 CtrBit_1 /CtrBit_0 ; Go to 1011, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 /CtrBit_2 CtrBit_1 CtrBit_0 ; Go to 1100, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 CtrBit_2 /CtrBit_1 /CtrBit_0 ; Go to 1101, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 CtrBit_2 /CtrBit_1 CtrBit_0 ; Go to 1110, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 CtrBit_2 CtrBit_1 /CtrBit_0 ; Go to 1111, all /CREQ lines should not be driven and can't be checked SETF CtrClock SETF /CtrClock CHECK CtrBit_3 CtrBit_2 CtrBit_1 CtrBit_0 ; Go back to 0000, verify that all /CREQ lines go high SETF CtrClock SETF /CtrClock CHECK /CtrBit_3 /CtrBit_2 /CtrBit_1 /CtrBit_0 CHECK /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 TRACE_OFF