TITLE Cable Receiver Card Strobe Clipper PATTERN CRC Strobe Clipper REVISION 1.05 AUTHOR Level 1.5 Calorimeter Trigger (Steve Gross) COMPANY MSU HEP DATE 22-NOV-1993 ; The detailed description of this device is at the end of this file. ; IMPORTANT NOTE: There is a bug in the AMD PALASM-2 simulator which ; the simulator to incorrectly handle the case when the ; output of a registered pin is undefined. This appears ; in Vector #2 of the .JDC file, which corresponds to the ; "setting the quiescent inputs" line of the SIMULATION ; section of this .PDS (the second SETF statement). I ; have edited the .JDC file generated by this .PDS. I ; changed pins 16-19 in Vector #2 from L (as chosen by the ; simulation software) to X (as they in fact are). Recall ; L = output low, X = output undefined. CHIP CRCStrob PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD /CRDY_1 /CRDY_2 /CRDY_3 /CRDY_4 NC1 NC2 STROBEIN ;9 10 11 12 13 14 15 16 VMERESET GND /Glob_OE /RESET_4 /RESET_3 /RESET_2 /RESET_1 /CSTRB_4 ;17 18 19 20 /CSTRB_3 /CSTRB_2 /CSTRB_1 Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. RESET_1 := VMERESET + CRDY_1 ; This term is the term used to reset RESET_1.CLKF = GND ; the CSTRB_1 latch. When either RESET_1.TRST = Vcc ; /CRDY_1 goes low, or VMERESET goes RESET_1.SETF = Vcc ; high, the CSTRB_1 latch will be RESET_1.RSTF = Vcc ; reset, forcing /CSTRB_1 high. ; This term is not clocked, and it ; is always output-enabled and fed ; back to the matrix. RESET_2 := VMERESET + CRDY_2 ; This term is the term used to reset RESET_2.CLKF = GND ; the CSTRB_2 latch. When either RESET_2.TRST = Vcc ; /CRDY_2 goes low, or VMERESET goes RESET_2.SETF = Vcc ; high, the CSTRB_2 latch will be RESET_2.RSTF = Vcc ; reset, forcing /CSTRB_2 high. ; This term is not clocked, and it ; is always output-enabled and fed ; back to the matrix. RESET_3 := VMERESET + CRDY_3 ; This term is the term used to reset RESET_3.CLKF = GND ; the CSTRB_3 latch. When either RESET_3.TRST = Vcc ; /CRDY_3 goes low, or VMERESET goes RESET_3.SETF = Vcc ; high, the CSTRB_3 latch will be RESET_3.RSTF = Vcc ; reset, forcing /CSTRB_3 high. ; This term is not clocked, and it ; is always output-enabled and fed ; back to the matrix. RESET_4 := VMERESET + CRDY_4 ; This term is the term used to reset RESET_4.CLKF = GND ; the CSTRB_4 latch. When either RESET_4.TRST = Vcc ; /CRDY_4 goes low, or VMERESET goes RESET_4.SETF = Vcc ; high, the CSTRB_4 latch will be RESET_4.RSTF = Vcc ; reset, forcing /CSTRB_4 high. ; This term is not clocked, and it ; is always output-enabled and fed ; back to the matrix. CSTRB_1 := Vcc ; This term is the CSTRB_1 term. It CSTRB_1.CLKF = /STROBEIN ; goes high on the falling edge of CSTRB_1.TRST = Vcc ; STROBEIN unless prevented by the CSTRB_1.SETF = GND ; RESET_1 signal. It remains high CSTRB_1.RSTF = RESET_1 ; until forced low by RESET_1. ; The /CSTRB_1 term to the C40 Comm ; Port is the inverted CSTRB_1 line. CSTRB_2 := Vcc ; This term is the CSTRB_2 term. It CSTRB_2.CLKF = /STROBEIN ; goes high on the falling edge of CSTRB_2.TRST = Vcc ; STROBEIN unless prevented by the CSTRB_2.SETF = GND ; RESET_2 signal. It remains high CSTRB_2.RSTF = RESET_2 ; until forced low by RESET_2. ; The /CSTRB_2 term to the C40 Comm ; Port is the inverted CSTRB_2 line. CSTRB_3 := Vcc ; This term is the CSTRB_3 term. It CSTRB_3.CLKF = /STROBEIN ; goes high on the falling edge of CSTRB_3.TRST = Vcc ; STROBEIN unless prevented by the CSTRB_3.SETF = GND ; RESET_3 signal. It remains high CSTRB_3.RSTF = RESET_3 ; until forced low by RESET_3. ; The /CSTRB_3 term to the C40 Comm ; Port is the inverted CSTRB_3 line. CSTRB_4 := Vcc ; This term is the CSTRB_4 term. It CSTRB_4.CLKF = /STROBEIN ; goes high on the falling edge of CSTRB_4.TRST = Vcc ; STROBEIN unless prevented by the CSTRB_4.SETF = GND ; RESET_4 signal. It remains high CSTRB_4.RSTF = RESET_4 ; until forced low by RESET_4. ; The /CSTRB_4 term to the C40 Comm ; Port is the inverted CSTRB_4 line. ; Description of this CRC Strobe Clipper PAL ; ; This circuit uses a 16RA8 type of PAL. ; ; Pin Signal Description PCB Connection ; --- ---------------------------- ---------------------------------- ; ; 1 PreLoad Register (low active) This pin should be tied HIGH. ; ; 2 /CRDY_1 This pin should be tied to the ; /CRDY signal from DSP #1 ; ; 3 /CRDY_2 This pin should be tied to the ; /CRDY signal from DSP #2 ; ; 4 /CRDY_3 This pin should be tied to the ; /CRDY signal from DSP #3 ; ; 5 /CRDY_4 This pin should be tied to the ; /CRDY signal from DSP #4 ; ; 6 Not Connected Not connected to any PCB signal ; ; 7 Not Connected Not connected to any PCB signal ; ; 8 STROBEIN This pin should be tied to the ; Strobe_In signal from the ERPB ; ; 9 VMERESET This pin should be tied to the ; VME RESET signal from the VME ; backplane through a "jumper wire" ; ; 10 Device GROUND This pin should be tied to the ; PCB GROUND plane ; ; 11 Global Output Enable (low active) This pin should be tied LOW. ; ; 12 /RESET_4 Not connected to any PCB signal ; ; 13 /RESET_3 Not connected to any PCB signal ; ; 14 /RESET_2 Not connected to any PCB signal ; ; 15 /RESET_1 Not connected to any PCB signal ; ; 16 /CSTRB_4 This pin should be tied to the ; /CSTRB signal to DSP #4 through ; a series-terminating resistor ; ; 17 /CSTRB_3 This pin should be tied to the ; /CSTRB signal to DSP #3 through ; a series-terminating resistor ; ; 18 /CSTRB_2 This pin should be tied to the ; /CSTRB signal to DSP #2 through ; a series-terminating resistor ; ; 19 /CSTRB_1 This pin should be tied to the ; /CSTRB signal to DSP #1 through ; a series-terminating resistor ; ; ; 20 Device Vcc This pin should be tied to the ; PCB VCC plane ; ; ; ; This PAL performs the Level 1.5 Cal Trig CRC Strobe Clipper logic. ; ; A timing diagram of the functionality required from one "channel" of ; this device (which is composed of 4 identical "channels") is shown ; below: ; ; _____ ; VMERESET ___/ \___________________________________________________ ; ; ________ ________ ; STROBEIN XXXXXXX______/ \________________/ \____________ ; ; ____________________ _____________________ ______ ; /CSTRB_n XXXX \___/ \___/ ; ; ___________________ _____________________ ____ ; /CRDY_n XXXXXXX \___/ \___/ ; ; SIMULATION ; --------Enable tracing of several signals TRACE_ON VMERESET STROBEIN /CSTRB_1 /CRDY_1 /CSTRB_2 /CRDY_2 /CSTRB_3 /CRDY_3 /CSTRB_4 /CRDY_4 ; --------Disable preload, enable global OE (done in wiring on PCB) SETF /Pre_LD Glob_OE ; --------Set the inputs to the normal "quiescent" state SETF /VMERESET /STROBEIN /CRDY_1 /CRDY_2 /CRDY_3 /CRDY_4 ; The outputs should all be "unknown" at this time because the FF's have ; not been initialized. The outputs cannot be checked until the FF's have ; been initialized. The test vectors created by the simulator cannot ; correctly handle this condition, and must be edited by hand. See the ; note at the top of this file. ; --------Initialize the Flip-Flops by activating the VMERESET signal ; First activate VMERESET SETF VMERESET ; Now all of the /CSTRB signals should be HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; Now deactivate VMERESET SETF /VMERESET ; Now check that all of the /CSTRB signals should remain HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; --------Now cause all /CSTRB outputs to go low simultaneously ; by providing a LOW-to-HIGH-to-LOW pulse on STROBEIN ; First activate STROBEIN SETF STROBEIN ; The /CSTRB outputs should still be HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; Now deactivate STROBEIN. SETF /STROBEIN ; This falling edge on STROBEIN should have caused all /CSTRB outputs to ; become LOW CHECK CSTRB_1 CSTRB_2 CSTRB_3 CSTRB_4 ; --------Now cause the /CSTRB outputs to return high individually ; by setting the respective /CRDY input low ; Channel #1 SETF CRDY_1 CHECK /CSTRB_1 CSTRB_2 CSTRB_3 CSTRB_4 ; Channel #2 SETF CRDY_2 CHECK /CSTRB_1 /CSTRB_2 CSTRB_3 CSTRB_4 ;Channel #3 SETF CRDY_3 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 CSTRB_4 ;Channel #4 SETF CRDY_4 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; --------Now return the /CRDY inputs to their quiescent HIGH state, ; checking the /CSTRB outputs at each step. The /CSTRB ; outputs should not change ;Channel #1 SETF /CRDY_1 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #2 SETF /CRDY_2 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #3 SETF /CRDY_3 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #4 SETF /CRDY_4 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; --------Now the device should be ready for a second cycle, I will ; test the chip with the /CRDY lines going low in a different ; order than the last test ; --------Now cause all /CSTRB outputs to go low simultaneously ; by providing a LOW-to-HIGH-to-LOW pulse on STROBEIN ; First activate STROBEIN SETF STROBEIN ; The /CSTRB outputs should still be HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; Now deactivate STROBEIN. SETF /STROBEIN ; This falling edge on STROBEIN should have caused all /CSTRB outputs to ; become LOW CHECK CSTRB_1 CSTRB_2 CSTRB_3 CSTRB_4 ; --------Now cause the /CSTRB outputs to return high individually ; by setting the respective /CRDY input low ; Channel #4 SETF CRDY_4 CHECK CSTRB_1 CSTRB_2 CSTRB_3 /CSTRB_4 ; Channel #3 SETF CRDY_3 CHECK CSTRB_1 CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #2 SETF CRDY_2 CHECK CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #1 SETF CRDY_1 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; --------Now return the /CRDY inputs to their quiescent HIGH state, ; checking the /CSTRB outputs at each step. The /CSTRB ; outputs should not change ;Channel #2 SETF /CRDY_2 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #4 SETF /CRDY_4 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #1 SETF /CRDY_1 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ;Channel #3 SETF /CRDY_3 CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; --------Finally check that the VMERESET signal can force all ; /CSTRB outputs high ; First activate STROBEIN SETF STROBEIN ; The /CSTRB outputs should still be HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; Now deactivate STROBEIN. SETF /STROBEIN ; This falling edge on STROBEIN should have caused all /CSTRB outputs to ; become LOW CHECK CSTRB_1 CSTRB_2 CSTRB_3 CSTRB_4 ; Now apply a VMERESET signal SETF VMERESET ; Check to see that all /CSTRB outputs have become HIGH CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 ; Now remove the VMERESET and verify that all /CSTRB outputs remain HIGH SETF /VMERESET CHECK /CSTRB_1 /CSTRB_2 /CSTRB_3 /CSTRB_4 TRACE_OFF