TITLE Cable Receiver Card Token Grabber PATTERN CRC Token Grabber REVISION 1.05 AUTHOR Level 1.5 Calorimeter Trigger (Steve Gross) COMPANY MSU HEP DATE 22-NOV-1993 ; The detailed description of this device is at the end of this file. CHIP CRCToken PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD /CACK_1 /CACK_2 /CACK_3 /CACK_4 NC1 NC2 CLOCKIN ;9 10 11 12 13 14 15 16 VMERESET GND /Glob_OE /CACK_4DY /CACK_3DY /CACK_2DY /CACK_1DY /CREQ_4 ;17 18 19 20 /CREQ_3 /CREQ_2 /CREQ_1 Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. CACK_1DY := CACK_1 ; This term is the 1st Delay of the CACK_1DY.CLKF = CLOCKIN ; inverted /CACK signal from the CACK_1DY.TRST = Vcc ; DSP channel #1. It will go low CACK_1DY.SETF = GND ; on the first clock rising edge CACK_1DY.RSTF = VMERESET ; while /CACK_1 is high. It will ; also go low if VMERESET goes high. ; It is always output-enabled and ; fed-back to the matrix. CACK_2DY := CACK_2 ; This term is the 1st Delay of the CACK_2DY.CLKF = CLOCKIN ; inverted /CACK signal from the CACK_2DY.TRST = Vcc ; DSP channel #2. It will go low CACK_2DY.SETF = GND ; on the first clock rising edge CACK_2DY.RSTF = VMERESET ; while /CACK_2 is high. It will ; also go low if VMERESET goes high. ; It is always output-enabled and ; fed-back to the matrix. CACK_3DY := CACK_3 ; This term is the 1st Delay of the CACK_3DY.CLKF = CLOCKIN ; inverted /CACK signal from the CACK_3DY.TRST = Vcc ; DSP channel #3. It will go high CACK_3DY.SETF = GND ; on the first clock rising edge CACK_3DY.RSTF = VMERESET ; while /CACK_3 is high. It will ; also go low if VMERESET goes high. ; It is always output-enabled and ; fed-back to the matrix. CACK_4DY := CACK_4 ; This term is the 1st Delay of the CACK_4DY.CLKF = CLOCKIN ; inverted /CACK signal from the CACK_4DY.TRST = Vcc ; DSP channel #4. It will go low CACK_4DY.SETF = GND ; on the first clock rising edge CACK_4DY.RSTF = VMERESET ; while /CACK_4 is high. It will ; also go low if VMERESET goes high. ; It is always output-enabled and ; fed-back to the matrix. CREQ_1 := /CACK_1DY ; This term is the /CREQ output CREQ_1.CLKF = /CLOCKIN ; for DSP channel #1. It goes high CREQ_1.TRST = Vcc ; on the first clock FALLING edge CREQ_1.SETF = GND ; after CACK_1DY goes low. CREQ_1.RSTF = VMERESET ; It also goes low if VMERESET goes ; high. ; It is always output-enabled. ; This signal is inverted to become ; the /CREQ_1 output pin CREQ_2 := /CACK_2DY ; This term is the /CREQ output CREQ_2.CLKF = /CLOCKIN ; for DSP channel #2. It goes high CREQ_2.TRST = Vcc ; on the first clock FALLING edge CREQ_2.SETF = GND ; after CACK_2DY goes low. CREQ_2.RSTF = VMERESET ; It also goes low if VMERESET goes ; high. ; It is always output-enabled. ; This signal is inverted to become ; the /CREQ_2 output pin CREQ_3 := /CACK_3DY ; This term is the /CREQ output CREQ_3.CLKF = /CLOCKIN ; for DSP channel #3. It goes high CREQ_3.TRST = Vcc ; on the first clock FALLING edge CREQ_3.SETF = GND ; after CACK_3DY goes low. CREQ_3.RSTF = VMERESET ; It also goes low if VMERESET goes ; high. ; It is always output-enabled. ; This signal is inverted to become ; the /CREQ_3 output pin CREQ_4 := /CACK_4DY ; This term is the /CREQ output CREQ_4.CLKF = /CLOCKIN ; for DSP channel #4. It goes high CREQ_4.TRST = Vcc ; on the first clock FALLING edge CREQ_4.SETF = GND ; after CACK_4DY goes low. CREQ_4.RSTF = VMERESET ; It also goes low if VMERESET goes ; high. ; It is always output-enabled. ; This signal is inverted to become ; the /CREQ_4 output pin ; Description of this CRC Token Grabber PAL ; ; This circuit uses a 16RA8 type of PAL. ; ; Pin Signal Description PCB Connection ; --- ---------------------------- ---------------------------------- ; ; 1 Preload Register (low active) This pin should be tied HIGH ; ; 2 /CACK_1 This pin should be tied to the ; /CACK signal from DSP #1 and ; also pulled up to +5V through ; a 10K ohm resistor ; ; 3 /CACK_2 This pin should be tied to the ; /CACK signal from DSP #2 and ; also pulled up to +5V through ; a 10K ohm resistor ; ; 4 /CACK_3 This pin should be tied to the ; /CACK signal from DSP #3 and ; also pulled up to +5V through ; a 10K ohm resistor ; ; 5 /CACK_4 This pin should be tied to the ; /CACK signal from DSP #4 and ; also pulled up to +5V through ; a 10K ohm resistor ; ; 6 Not Connected Not connected to any PCB signal ; ; 7 Not Connected Not connected to any PCB signal ; ; 8 CLOCKIN This pin should be connected to ; the PAL clock (crystal oscillator) ; ; 9 VMERESET This pin should be tied to the ; VME RESET signal from the VME ; backplane through a "jumper wire" ; ; 10 Device GROUND This pin should be tied to the ; PCB GROUND plane ; ; 11 Global Output Enable (low active) This pin should be tied LOW. ; ; 12 /CACK_4DY Not connected to any PCB signal ; ; 13 /CACK_3DY Not connected to any PCB signal ; ; 14 /CACK_2DY Not connected to any PCB signal ; ; 15 /CACK_1DY Not connected to any PCB signal ; ; 16 /CREQ_4 This pin should be tied to the ; /CREQ signal to DSP #4 through ; a current-limiting resistor ; ; 17 /CREQ_3 This pin should be tied to the ; /CREQ signal to DSP #3 through ; a current-limiting resistor ; ; 18 /CREQ_2 This pin should be tied to the ; /CREQ signal to DSP #2 through ; a current-limiting resistor ; ; 19 /CREQ_1 This pin should be tied to the ; /CREQ signal to DSP #1 through ; a current-limiting resistor ; ; ; 20 Device Vcc This pin should be tied to the ; PCB VCC plane ; ; ; ; This PAL performs the Level 1.5 Cal Trig CRC Token Grabber logic. ; ; ; This PAL has 4 identical "channels." Below I describe the function of ; one "channel" of the PAL. ; ; The purpose of this PAL is to retrive the token from a TI TMS320C40 ; DSP Comm Port. This will force the Comm Port into "input mode," i.e. ; the Comm Port will receive data. ; ; This PAL will continually try to "force" the 'C40 Comm Port into ; "input mode." If at any time the 'C40 Comm Port enters "output mode" ; (for example via a 'C40 hardware reset), the Token Grabber PAL will ; automatically try to retrieve the token from the 'C40 Comm Port (i.e. ; the Token Grabber does not require any signal other than the 'C40 ; /CACK signal to initiate a token request. ; ; Note that the Token Grabber does make use of the VMERESET signal. When ; VMERESET is asserted (i.e. when the VME backplane SYSRESET* signal is ; low), the Token Grabber's /CREQ output is forced high. This is only ; done to provide a consistent state of the /CREQ line during the system ; reset. Recall that the 'C40s will be resetting at this time also. ; ; There are 2 cases to consider: ; ; I. The 'C40 port is already in "input" mode (i.e. it doesn't have the ; token). ; ; II. The 'C40 port is in "output" mode (i.e. it has the token) ; ; Timing diagrams for both cases are shown below: ; (naming convention: /CREQ is the /CREQ signal created by the ; Token Grabber PAL ; /CREQ' is the /CREQ signal created/monitored ; by the 'C40 Comm Port (recall that this signal ; is pulled up to VCC through a 10K ohm resistor ; on the Hydra-II) ; /CACK is the /CACK signal monitored by the ; Token Grabber PAL ; /CACK' is the /CACK signal created/monitored ; by the 'C40 Comm Port (recall that this signal ; is pulled up to VCC through a 10K ohm resistor ; on the CRC card) ; ; I. The 'C40 port is in "input" mode (i.e. it doesn't have the token) ; ; _____ _____ _____ _____ _____ _____ ; CLOCK _/ \_____/ \_____/ \_____/ \_____/ \_____/ \__ ; _____ ; VMERESET _/ \___________________________________________________________ ; ___________________________________________________________________ ; /CREQ' ; ______________ ; /CREQ XXX \_________________________________________________ ; ; /CACK' ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ ; ___________________________________________________________________ ; /CACK ; ; ; II. The 'C40 port is in "output" mode (i.e. it has the token) ; ; _____ _____ _____ _____ _____ _____ ; CLOCK _/ \_____/ \_____/ \_____/ \_____/ \_____/ \__ ; _____ ; VMERESET _/ \___________________________________________________________ ; ________________ ; /CREQ' ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ ; ______________ ___________ ; /CREQ XXX \_______________________/ \_____________ ; __________________________ _ ; /CACK' \_______________/ ZZZZZZZZZZZZZZZZZZZZZZZ ; __________________________ ________________________ ; /CACK \_______________/ ; ; Note that in the "steady state" (i.e at the end of processing) the ; response is identical for both Case I and Case II. This is as it should ; be, since after Case II processing, the Token Grabber has "forced" the ; 'C40 into "input mode." ; ; Note also that in the steady state, the 'C40 treats /CREQ as an output ; and /CACK as an input. The pull-up resistor on the CRC holds /CACK high ; which is what the 'C40 would like to see (i.e. what the 'C40 would see ; if it were attached to another 'C40). The CRC is holding its /CREQ ; output LOW, while the 'C40 is holding its /CREQ output HIGH. The ; contention is solved by the presence of a current-limiting resistor ; between the 'C40 /CREQ pin and the Token Grabber /CREQ pin. SIMULATION ; --------Enable tracing of several signals TRACE_ON CLOCKIN VMERESET /CACK_1 /CACK_1DY /CREQ_1 /CACK_2 /CACK_2DY /CREQ_2 /CACK_3 /CACK_3DY /CREQ_3 /CACK_4 /CACK_4DY /CREQ_4 ; --------Enable global OE (done in wiring on PCB) SETF Glob_OE /Pre_LD ; --------Set the inputs to the normal "quiescent" state SETF /VMERESET /CLOCKIN /CACK_1 /CACK_2 /CACK_3 /CACK_4 ; The outputs should be "unknown" at this time because the flip-flops ; have not been initialized. Initialize the flip-flops using the ; VMERESET signal SETF VMERESET ; The outputs should now all be forced HIGH. Check this CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Now de-assert the VMERESET signal SETF /VMERESET ; --------Now test for Case I: interfacing to a DSP channel which is ; already in input mode. [/CREQ (DSP) is a DSP output and ; is forced high by the DSP. /CACK (DSP) is a DSP input and is ; pulled up through a resistor on the CRC card. ; Test all channels simultaneously. The input conditions have already ; been set up, so I will provide a clock RISING edge SETF CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK signals ; (i.e. the pins labelled /CACK_xDY) should remain high, and the ; /CREQ outputs should also remain high. Check this CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; The DSP Comm Ports sees no change at /CACK and thus makes no change ; in its output. I will provide a clock FALLING edge SETF /CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK signals ; (i.e. the pins labelled /CACK_xDY) should remain high, and the ; the /CREQ outputs should go low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Again the DSP Comm Ports see no change at /CACK and thus make no ; changes in their outputs. Note however that the Token Grabber is ; trying to force the /CREQ lines low, while the Comm Ports are trying ; to force the /CREQ lines high. The voltage difference is taken care ; of by putting a current-limiting resistor between the pins. ; I will provide another clock rising edge. The conditions should not ; change SETF CLOCKIN CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; I will provide another clock falling edge. The conditions should not ; change SETF /CLOCKIN CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; These conditions should now remain until either the Token Grabber ; is reset, or the DSP is reset. ; Reset the Token Grabber SETF VMERESET ; Check to see that the RESET occured. All outputs should be high CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; Now de-assert the VMERESET signal SETF /VMERESET ; --------Test Case II: DSP Comm Port is in "output mode." ; [/CREQ (DSP) is an input to the DSP and is pulled high ; on the Hydra card. /CACK (DSP) is an output from the ; DSP and is forced high by the DSP]. Test each channel ; individually. The input conditions have already been ; set up. ; Begin the transaction in parallel for all channels with a clock ; rising edge SETF CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK signals ; (i.e. the pins labelled /CACK_xDY) should remain high, and the ; /CREQ outputs should all still be high. Check this CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 /CREQ_2 /CREQ_3 /CREQ_4 ; The DSP Comm Ports sees no change at /CREQ and thus makes no change ; in its output. I will provide a clock FALLING edge SETF /CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK signals ; (i.e. the pins labelled /CACK_xDY) should remain high, and the ; the /CREQ outputs should also be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now the DSP comm Ports see a change at /CREQ. Sometime later, the ; DSP Comm Port will force its /CACK output low in response to the ; change in /CREQ. ; Here I will treat each Comm Port individually ; Channel #1 ; First illustrate the delay in the response of DSP Channel #1 with ; a clock pulse. No outputs should change SETF CLOCKIN SETF /CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK signals ; (i.e. the pins labelled /CACK_xDY) should remain high, and the ; the /CREQ outputs should also be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #1 SETF CACK_1 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the (inverted) "1st Delay" of the inverted /CACK for Channel #1 ; should go low, and the (inverted) "1st Delay" of the inverted /CACK for ; all other channels should remain high. ; The /CREQ outputs should all remain low CHECK CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now provide a clock FALLING edge SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #1 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #1 should become high, ; while the /CREQ output for all other channels should be low CHECK CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Sometime later, the DSP Comm Port will force its /CACK line high. ; Illustrate this delay with a clock pulse SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #1 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #1 should remain high, ; while the /CREQ output for all other channels should remain low CHECK CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #1 SETF /CACK_1 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #1 should become ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should remain high. The /CREQ output for Channel #1 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK /CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; The /CACK signal is now an input to the DSP (and is pulled up through ; a resistor on the CRC. It will always remain high. The /CREQ signal ; is now an output from the DSP. The DSP will force it high. After ; a clock FALLING edge, the Token Grabber will try to force the /CREQ ; signal low. The voltage difference is again taken up by a current- ; limiting resistor. SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for all channels should ; remain high. The /CREQ output for Channel #1 should become low, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now test Channel #2 ; First illustrate the delay in the response of DSP Channel #2 with ; a clock pulse. No outputs should change SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK should still be low but now ; the /CREQ outputs should also be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #2 SETF CACK_2 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #2 should be high, ; and the "1st Delay" of the inverted /CACK for all other channels should ; be low. The /CREQ outputs should all remain low CHECK /CACK_1DY CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now provide a clock FALLING edge SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #2 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #2 should become high, ; while the /CREQ output for all other channels should be low CHECK /CACK_1DY CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 /CREQ_2 CREQ_3 CREQ_4 ; Sometime later, the DSP Comm Port will force its /CACK line high. ; Illustrate this delay with a clock pulse SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #2 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #2 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 /CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #2 SETF /CACK_2 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #2 should become ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should remain high. The /CREQ output for Channel #2 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 /CREQ_2 CREQ_3 CREQ_4 ; The /CACK signal is now an input to the DSP (and is pulled up through ; a resistor on the CRC. It will always remain high. The /CREQ signal ; is now an output from the DSP. The DSP will force it high. After ; a clock FALLING edge, the Token Grabber will try to force the /CREQ ; signal low. The voltage difference is again taken up by a current- ; limiting resistor. SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for all channels should ; remain high. The /CREQ output for Channel #2 should become low, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now test Channel #3 ; First illustrate the delay in the response of DSP Channel #3 with ; a clock pulse. No outputs should change SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK should still be low but now ; the /CREQ outputs should also be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #3 SETF CACK_3 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #3 should be high, ; and the "1st Delay" of the inverted /CACK for all other channels should ; be low. The /CREQ outputs should all remain low CHECK /CACK_1DY /CACK_2DY CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now provide a clock FALLING edge SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #3 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #3 should become high, ; while the /CREQ output for all other channels should be low CHECK /CACK_1DY /CACK_2DY CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 /CREQ_3 CREQ_4 ; Sometime later, the DSP Comm Port will force its /CACK line high. ; Illustrate this delay with a clock pulse SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #3 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #3 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 /CREQ_3 CREQ_4 ; Now show the response of DSP Channel #3 SETF /CACK_3 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #3 should become ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should remain high. The /CREQ output for Channel #3 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 /CREQ_3 CREQ_4 ; The /CACK signal is now an input to the DSP (and is pulled up through ; a resistor on the CRC. It will always remain high. The /CREQ signal ; is now an output from the DSP. The DSP will force it high. After ; a clock FALLING edge, the Token Grabber will try to force the /CREQ ; signal low. The voltage difference is again taken up by a current- ; limiting resistor. SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for all channels should ; remain high. The /CREQ output for Channel #3 should become low, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now test Channel #4 ; First illustrate the delay in the response of DSP Channel #4 with ; a clock pulse. No outputs should change SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK should still be low but now ; the /CREQ outputs should also be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now show the response of DSP Channel #4 SETF CACK_4 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #4 should be high, ; and the "1st Delay" of the inverted /CACK for all other channels should ; be low. The /CREQ outputs should all remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 ; Now provide a clock FALLING edge SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #4 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #4 should become high, ; while the /CREQ output for all other channels should be low CHECK /CACK_1DY /CACK_2DY /CACK_3DY CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 /CREQ_4 ; Sometime later, the DSP Comm Port will force its /CACK line high. ; Illustrate this delay with a clock pulse SETF CLOCKIN SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #4 should remain ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should be low. The /CREQ output for Channel #4 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 /CREQ_4 ; Now show the response of DSP Channel #4 SETF /CACK_4 ; Now provide a clock RISING edge SETF CLOCKIN ; Now the "1st Delay" of the inverted /CACK for Channel #4 should become ; high, and the "1st Delay" of the inverted /CACK for all other channels ; should remain high. The /CREQ output for Channel #4 should remain high, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 /CREQ_4 ; The /CACK signal is now an input to the DSP (and is pulled up through ; a resistor on the CRC. It will always remain high. The /CREQ signal ; is now an output from the DSP. The DSP will force it high. After ; a clock FALLING edge, the Token Grabber will try to force the /CREQ ; signal low. The voltage difference is again taken up by a current- ; limiting resistor. SETF /CLOCKIN ; Now the "1st Delay" of the inverted /CACK for all channels should ; remain high. The /CREQ output for Channel #4 should become low, ; while the /CREQ output for all other channels should remain low CHECK /CACK_1DY /CACK_2DY /CACK_3DY /CACK_4DY CHECK CREQ_1 CREQ_2 CREQ_3 CREQ_4 TRACE_OFF