Board:          FMLN
Function:       Px, Py Overflow Detection Logic
Author:         Steve Gross
Date:           25-JUL-1991 
Semiconductor-device:         Cypress CY100E302 (16P4-type)

    This is  the EQN  file, in  SPRINT  format, for  the  Px/Py Overflow
    Detection PAL which resides on the FMLN card


    This section defines the equations which are implemented in this PAL.

    This  PAL  must  examine  a  24-bit,  2's  complement   input, which
represents either the  signed Px or signed Py  value formed by the Third
Tier CAT3s, and determine whether it has exceeded the range which can be
handled by the Threshold Lookup RAM. That RAM can only examine 9 bits of
Px and 9 bits of Py. Recall that  the scale for momentum sums is 1 bit =
1/2 GeV.  Therefore, 9 bits  can represent  a range of  -128 GeV..+127.5
GeV. The highest MPt threshold can  therefore be 127.5 GeV (see FMLN.TXT
for a further description of the FMLN card). Px or Py values outside the
range -128  GeV..+127.5  GeV are  guaranteed to  exceed all  permissible
thresholds. 

    In brief, this overflow sensing  is performed by determining whether
the signed  24-bit  quantity is  simply a  sign-extended  9-bit quantity
(with the sign  bit as the 9th  bit). Recall that  this is equivalent to
saying that all bits 9..24 must  have the same value, whether 0 or 1. If
this is true, than the 24-bit quantity is "in range." 

    A table is  presented below  which will clarify  the logic needed to
perform this overflow sensing:

                | O |       Px or Py Bits         | AND of   |
    Px or Py    | v |                             | NOT of   | AND of  
                | e |   222221111111111           | bits     | bits    
      (Gev)     | r |   432109876543210987654321  | 9..24    | 9..24    
    --------------------------------------------------------------------
 +4194303.5     | 1 |   011111111111111111111111  |    0     |     0   
         .      | . |              .              |    .     |     .   
         .      | . |              .              |    .     |     .   
     +128.0     | 1 |   000000000000000100000000  |    0     |     0   
     +127.5     | 0 |   000000000000000011111111  |    1     |     0   
         .      | . |              .              |    .     |     .   
         .      | . |              .              |    .     |     .   
       +1.0     | 0 |   000000000000000000000010  |    1     |     0   
       +0.5     | 0 |   000000000000000000000001  |    1     |     0   
        0.0     | 0 |   000000000000000000000000  |    1     |     0   
       -0.5     | 0 |   111111111111111111111111  |    0     |     1   
       -1.0     | 0 |   111111111111111111111110  |    0     |     1   
         .      | . |              .              |    .     |     .   
         .      | . |              .              |    .     |     .   
     -128.0     | 0 |   111111111111111100000000  |    0     |     1   
     -128.5     | 1 |   111111111111111011111111  |    0     |     0   
         .      | . |              .              |    .     |     .   
         .      | . |              .              |    .     |     .   
 -4194304.0     | 1 |   100000000000000000000000  |    0     |     0   

    It is now  clear that an  overflow  condition DOES  NOT exist if and
only if either the AND of bits  9..24 is 1 OR the AND of the NOT of bits
9..24 is 1. That is: 

           /Pxy_Overflow =    (Pxy[9]  * Pxy[10]  * ... * Pxy[24]) 
                            + (/Pxy[9] * /Pxy[10] * ... * /Pxy[24])  

    This is  conveniently  a  sum-of-products  which is  appropriate for
generating PAL fuse maps using SPRINT software.

    Although no parentheses are used in the following EQUATIONS section,
the precedence of operations is  such that the ANDs are performed before
the ORs, so that the correct logic is implemented.

    Note that each PAL  generates both an  active-high and an active-low
OVERFLOW signal (see PIN LIST), for ease of circuit implementation.


    This section  describes the PIN  LIST. This PIN  LIST corresponds to
the design of the FMLN card in design engineer.


device e302;
Pxy9            11 
Pxy10           10 
Pxy11            9
Pxy12            8
PxyOvf1          5
/PxyOvf2         7
Pxy13           22 
Pxy14            4
Pxy15            3
Pxy16            2
Pxy17            1
Pxy18           23
Pxy19           13
Pxy20           21
Pxy21           17
PxyOvf3         18
/PxyOvf4        20
Pxy22           16
Pxy23           15
Pxy24           14
GND              6
VEE             12

start            ' Start of Equations
    
PxyOvf1 /=
                 Pxy9  * Pxy10 * Pxy11 * Pxy12 * Pxy13 *
                 Pxy14 * Pxy15 * Pxy16 * Pxy17 * Pxy18 *
                 Pxy19 * Pxy20 * Pxy21 * Pxy22 * Pxy23 * 
                 Pxy24
               +
                 /Pxy9  * /Pxy10 * /Pxy11 * /Pxy12 * /Pxy13 *
                 /Pxy14 * /Pxy15 * /Pxy16 * /Pxy17 * /Pxy18 *
                 /Pxy19 * /Pxy20 * /Pxy21 * /Pxy22 * /Pxy23 *
                 /Pxy24;


/PxyOvf2 =
                 Pxy9  * Pxy10 * Pxy11 * Pxy12 * Pxy13 *
                 Pxy14 * Pxy15 * Pxy16 * Pxy17 * Pxy18 *
                 Pxy19 * Pxy20 * Pxy21 * Pxy22 * Pxy23 * 
                 Pxy24
               +
                 /Pxy9  * /Pxy10 * /Pxy11 * /Pxy12 * /Pxy13 *
                 /Pxy14 * /Pxy15 * /Pxy16 * /Pxy17 * /Pxy18 *
                 /Pxy19 * /Pxy20 * /Pxy21 * /Pxy22 * /Pxy23 *
                 /Pxy24;


PxyOvf3 /=
                 Pxy9  * Pxy10 * Pxy11 * Pxy12 * Pxy13 *
                 Pxy14 * Pxy15 * Pxy16 * Pxy17 * Pxy18 *
                 Pxy19 * Pxy20 * Pxy21 * Pxy22 * Pxy23 * 
                 Pxy24
               +
                 /Pxy9  * /Pxy10 * /Pxy11 * /Pxy12 * /Pxy13 *
                 /Pxy14 * /Pxy15 * /Pxy16 * /Pxy17 * /Pxy18 *
                 /Pxy19 * /Pxy20 * /Pxy21 * /Pxy22 * /Pxy23 *
                 /Pxy24;


/PxyOvf4 =
                 Pxy9  * Pxy10 * Pxy11 * Pxy12 * Pxy13 *
                 Pxy14 * Pxy15 * Pxy16 * Pxy17 * Pxy18 *
                 Pxy19 * Pxy20 * Pxy21 * Pxy22 * Pxy23 * 
                 Pxy24
               +
                 /Pxy9  * /Pxy10 * /Pxy11 * /Pxy12 * /Pxy13 *
                 /Pxy14 * /Pxy15 * /Pxy16 * /Pxy17 * /Pxy18 *
                 /Pxy19 * /Pxy20 * /Pxy21 * /Pxy22 * /Pxy23 *
                 /Pxy24;

                 ' End of Pal Equations
'Vectors

vector 1111HNL1111N10111HNL111N
vector 0000HNL0001N00000HNL000N
vector 0000LNH0000N00000LNH000N
vector 1111LNH1111N11111LNH111N
vector 1111HNL1110N11111HNL111N
vector 0000HNL0000N01000HNL000N
vector 0000HNL0010N00000HNL000N
vector 0000HNL0100N00000HNL000N
vector 0000HNL1000N00000HNL000N
vector 0000HNL0000N00000HNL010N
vector 0001HNL0000N00000HNL000N
vector 0010HNL0000N00000HNL000N
vector 0100HNL0000N00000HNL000N
vector 1000HNL0000N00000HNL000N
vector 0000HNL0000N00000HNL001N
vector 0000HNL0000N10000HNL000N
vector 0000HNL0000N00000HNL100N
vector 0000HNL0000N00001HNL000N
vector 0000HNL0000N00010HNL000N
vector 0000HNL0000N00100HNL000N

end