MTG Move to 6 Crossings on 6 Crossings -------------------------------------------- Rev. 6-March-1992 First think about how Carmen Rotolo sets up his Master Clock: ------------------------------------------------------------- This is how to think about the layout of a "Clock File" for the Master Clock. The starting address in Carmen's RAM is a 1 not a 0. At the beginning of Carmen's RAM you think that the P6 crossing has already just happend and that you are now going to count your way up to the P1 crossing. There will be 184 empty RF buckets between the P6 crossing and the P1 crossing. The P1 crossing will occure on the 185th address in the RAM. There will then be 185 empty RF buckets and then the P2 crossing (i.e. the P2 crossing will occure 186 addresses after the P1 crossing or the 371st address used in the RAM). The P6 beam crossing happens at the 1113 address in the RAM. Crossing Carmen RAM Address ---------- -------------------- P1 185 P2 371 P3 556 P4 742 P5 927 P6 1113 Now think about how to setup the L1 MTG's and how to write the Timing Specification Files: ----------------------------------------------------------------------- The L1 MTG's run on a 26.552 MHz clock not the 53.104 MHz clock of Carmen's Master Clock system. The problem is that there is an odd number of 53 MHz clock cycles between beam crossings. This would result in either 92.5 of the 26 MHz clock cycles or else 93 of the 26 MHz clock cycles. The way around this is to always use 92 of the MTG's 26 MHz clock cycles in a beam crossing cycle. The first positive edge of the 26 MHz clock will occur during the Master Clock cycle where there is a beam crossing. This is followed by 91 additional positive 26 MHz clock edges and then the 26 MHz clock goes low and stays low until the next beam crossing. The 26 MHz clock will be low for either 1 cycle of 54 MHz RF (185 RF buckets) or else it will be low for 2 cycles of 54 MHz RF (186 buckets). Details about what to tell Carmen's Master Clock to get it to make the 26 MHz Clock for the MTG's and the once per turn Beam Crossing Marker for the L1 Trigger MTG's. -------------------------------------------------------------------------- ! Master Clock Signals for the ! Level 1 Trigger Framework and the Calorimeter Trigger ! for use with 6 bunches on 6 bunches 3.5 usec Timing ! Rev. 5-March-1992 ! First assign the value of the L1 Trigger Offset. ! A value of -6 compensates for the 65 feet cables from the Master ! Clock to the L1 MTG cards and for the 1 "tick" delay in the MTG's. Assign L1_Trig_OffSet = -6 ! Now program the P6 Marker pulse. This is the once per accelerator ! turn "beam crossing" marker to all of the L1 MTG cards. Set T10 Up Clk_T0_6+L1_Trig_Offset-1 For 2 ! Now program the L1 Bunch Clock for all 6 bunches. For 6 on 6 operation ! there are always 92 "ticks" of the L1 Bunch Clock (i.e. both the 185 RF ! bucket and 186 RF bucket crossings have 92 "ticks" of the L1 Bunch Clock. ! L1 Bunch Clock to process the P1 crossing Set T0 Up Clk_T0_1+L1_Trig_Offset+0 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+2 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+4 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+6 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+8 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+10 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+12 For 1 . . . Set T0 Up Clk_T0_1+L1_Trig_Offset+176 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+178 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+180 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+182 For 1 ! L1 Bunch Clock to process the P2 crossing Set T0 Up Clk_T0_2+L1_Trig_Offset+0 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+2 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+4 For 1 . . Set T0 Up Clk_T0_2+L1_Trig_Offset+178 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+180 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+182 For 1 . Details about the relation of the 26 MHz clock edges and the "Once per turn Beam Crossing Marker" required to get the MTG's to make an accurate Preset Load with good timing noise margins. ---------------------------------------------------------------------------- Timing of an "Ideal" Beam Crossing Reset Signal (Counter PreSet) ---------------------------------------------------------------- +---- Reset Here | 54 Mhz V ------- ------- ------- ------- ------- ------- --- ^ | ^ | ^ | ^ | ^ | ^ | ^ | | | | | | | | | | | | | ---- ------- ------- ------- ------- ------- ------- ---- ------------- ------------- ------------- | 26 ^ | ^ | ^ | | MHz | | | | | | ------------- ------------- ------------- --- Once per Turn ------------------------- Beam Crossing | | Reset (PreSet) | | ---------------------------- --------------------------- Timing of an "Real" Beam Crossing Reset Signal (Counter PreSet) Case Shown is an Odd Number of 54 MHz Cycles Since the Last Beam Crossing ------------------------------------------------------------------------- +---- Reset Here | 54 Mhz V ------- ------- ------- ------- ------- ------- --- ^ | ^ | ^ | ^ | ^ | ^ | ^ | | | | | | | | | | | | | ---- ------- ------- ------- ------- ------- ------- ------------- ------------- ------------- ^ 26 | ^ | ^ | | MHz | | | | | ---- ------------------------- ------------- --- Once per Turn ------------------------- Beam Crossing | | Reset (PreSet) | | ---------------------------- --------------------------- Relative Timing Delay of the MTG Rev B Accelerator Clock Input and the Beam Crossing Reset Input ------------------------------------------------------------- Accelerator Clock Input Received by a 10H115 0.7 nsec min 1.5 nsec max Mux Select by a 10H174 0.7 nsec min 2.7 nsec max -------------- -------------- Acc Clk delivered to 10H016's 1.4 nsec min 4.2 nsec max Beam Crossing Reset Received by a 10H115 0.7 nsec min 1.5 nsec max Logic Gated by a 10H104 0.7 nsec min 2.0 nsec max Logic Gated by a 10H104 0.7 nsec min 2.0 nsec max -------------- -------------- BX Reset delivered to 10H016's 2.1 nsec min 5.5 nsec max Thus if both Reset and Clock arrive at the input to the MTG at the same time then Reset will arrive at the 10H016 counters somewhere between as early as 2.1 nsec before the Clock to as late as 4.1 nsec after the Clock. The 10H016 counter require that the /PE signal arriver and is stable at least 2.5 nsec before the active clock edge and that this signal remain stable for at least 0.5 nsec after the active clock edge. Detailed list of what PROM's need to be made and/or changed. Reference all the Timing Specification Files to dated Timing Diagrams --------------------------------------------------------------------- 4 PROM's for the Framework Main Timing MTG 4 PROM's for the Calorimeter Trigger MTG 4 PROM's for the Direct-In-Test-Trigger MTG (all 4 are the same) 4 PROM's for the Hold Transfer MTG (all 4 are the same) 4 PROM's for the Start Digitization MTG (3 are the same) The following indicates the instructions that are necessary in the MTG Timing Specification File in order to repeat the timing patterns. This is shown for 6 on 6 beam crossings. ---------------------------------------------------------------------- Note: 1. We start counting MTG addresses at xx0 where as Carmen starts counting his master clock files at 1. We will continue to start our files at "0" because all of our diagrams are made that way. Typically a good "xx0" place to start the timing pattern is 100. Recall that all numeric data in an MTG Timing Specification File is in decimal. It is a good idea if the data in the timing pattern is established before the starting address (i.e. typically before address 100) and if it continues unchanged for a few addresses after the last address normally "played". 2. Also note that there are 2 halves to a PROM in an MTG. One or the other half is selected by a bit in the MTG board Control Status Register. The first half runs from address 0 through 1023. The second half runs from address 1024 through 2047. The MTG can not "play" a pattern that splits across halves (i.e. all of a timing pattern must be in one half or the other). ; ; Now repeat these timing patters for all 6 beam ; crossings that are in a turn around the accelerator. Process the Event Data from the Nth Beam Crossing ----------------- ; MTG PROM Addresses 100 through 191 service the P6 crossing Repeat Channel #1, Starting_with 100 Through 191 Copied_to 192 ; P1 crossing Repeat Channel #1, Starting_with 100 Through 191 Copied_to 284 ; P2 crossing Repeat Channel #1, Starting_with 100 Through 191 Copied_to 376 ; P3 crossing Repeat Channel #1, Starting_with 100 Through 191 Copied_to 468 ; P4 crossing Repeat Channel #1, Starting_with 100 Through 191 Copied_to 560 ; P5 crossing ; MTG PROM Addresses 560 through 651 service the P5 crossing ; MTG PROM Address 651 is the last PROM Address ; used in this 6 on 6 pattern. Repeat Channel #2, Starting_with 100 Through 191 Copied_to 192 ; P1 crossing Repeat Channel #2, Starting_with 100 Through 191 Copied_to 284 ; P2 crossing Repeat Channel #2, Starting_with 100 Through 191 Copied_to 376 ; P3 crossing Repeat Channel #2, Starting_with 100 Through 191 Copied_to 468 ; P4 crossing Repeat Channel #2, Starting_with 100 Through 191 Copied_to 560 ; P5 crossing . . . End_of_Data_Section Version Number for the PROM's ----------------------------- Things have gotten somewhat mixed up over the years about MTG PROM Version Numbers. I'm not certain what to do at this point. For now we will make all of these 6 on 6 parts be Version "K". All the binary files make on the VAX for the Sprint programmer will have the filename extension *.BNK (i.e. binary version K). Details about what to do for 4 on 4; both for MTG and Carmen Master Clock -------------------------------------------------------------------------- When used in the 4 on 4 mode Carmen's Master Clock set the crossings as: P1 = 278 P2 = 556 P3 = 835 P4 = 1113 As the master clock file starts, P4 has just happened, then there are 277 empty buckets, then on bucket 278 P1 happens, then there are 277 more empty buckets, then on bucket 556 P2 happens, then there are 278 more empty buckets, then on bucket 835 P3 happens, then there are 277 more empty buckets, then on bucket 1113 P4 happens. This means that we can always have 139 ticks of the 26 MHz MTG clock. There are three spacings of 278 RF Buckets and one spacing of 279 RF buckets. Recall that with 6 on 6 there are 92 ticks of 26 MHz so with 4 on 4 there are 47 additional ticks of 26 MHz. --------------------- To setup the Carmen Master Clock to make the required 26 MHz it will look like: ----------------------------------------- ! Master Clock Signals for the ! Level 1 Trigger Framework and the Calorimeter Trigger ! for use with 4 bunches on 4 bunches 5.2 usec Timing ! Rev. 5-March-1992 ! First assign the value of the L1 Trigger Offset. ! A value of -6 compensates for the 65 feet cables from the Master ! Clock to the L1 MTG cards and for the 1 "tick" delay in the MTG's. Assign L1_Trig_OffSet = -6 ! Now program the P4 Marker pulse. This is the once per accelerator ! turn "beam crossing" marker to all of the L1 MTG cards. Set T10 Up Clk_T0_4+L1_Trig_Offset-1 For 2 ! Now program the L1 Bunch Clock for all 4 bunches. For 4 on 4 operation ! there are always 139 "ticks" of the L1 Bunch Clock (i.e. both the 278 RF ! bucket and 279 RF bucket crossings have 139 "ticks" of the L1 Bunch Clock. ! L1 Bunch Clock to process the P1 crossing Set T0 Up Clk_T0_1+L1_Trig_Offset+0 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+2 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+4 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+6 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+8 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+10 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+12 For 1 . . . Set T0 Up Clk_T0_1+L1_Trig_Offset+272 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+274 For 1 Set T0 Up Clk_T0_1+L1_Trig_Offset+276 For 1 ! L1 Bunch Clock to process the P2 crossing Set T0 Up Clk_T0_2+L1_Trig_Offset+0 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+2 For 1 . . Set T0 Up Clk_T0_2+L1_Trig_Offset+274 For 1 Set T0 Up Clk_T0_2+L1_Trig_Offset+276 For 1 ! L1 Bunch Clock to process the P3 crossing . The following indicates the instructions that are necessary in the MTG Timing Specification File in order to repeat the timing patterns. This is shown for 4 on 4 beam crossings. Note: 1. We start counting MTG addresses at xx0 where as Carmen starts counting his master clock files at 1. We will continue to start our files at "0" because all of our diagrams are made that way. Typically a good "xx0" place to start the timing pattern is 1100 for the 4 on 4 part of the timing pattern. Recall that all numeric data in an MTG Timing Specification File is in decimal. It is a good idea if the data in the timing pattern is established before the starting address (i.e. typically before address 1100) and if it continues unchanged for a few addresses after the last address normally "played". 2. Also note that there are 2 halves to a PROM in an MTG. One or the other half is selected by a bit in the MTG board Control Status Register. The first half runs from address 0 through 1023. The second half runs from address 1024 through 2047. The MTG can not "play" a pattern that splits across halves (i.e. all of a timing pattern must be in one half or the other). ; ; Now repeat these timing patters for all 6 beam ; crossings that are in a turn around the accelerator. Process the Event Data from the Nth Beam Crossing ----------------- ; MTG PROM Addresses 1100 through 1238 service the P4 crossing Repeat Channel #1, Starting_with 1100 Through 1238 Copied_to 1239 ; P1 cross Repeat Channel #1, Starting_with 1100 Through 1238 Copied_to 1378 ; P2 cross Repeat Channel #1, Starting_with 1100 Through 1238 Copied_to 1517 ; P3 cross ; MTG PROM Addresses 1517 through 1655 service the P3 crossing ; MTG PROM Address 1655 is the last PROM Address ; used in this 4 on 4 pattern. Repeat Channel #2, Starting_with 1100 Through 1238 Copied_to 1239 ; P1 cross Repeat Channel #2, Starting_with 1100 Through 1238 Copied_to 1378 ; P2 cross Repeat Channel #2, Starting_with 1100 Through 1238 Copied_to 1517 ; P3 cross . . . End_of_Data_Section New Uses of MTG Channels on the Framework Main Timing MTG --------------------------------------------------------- The function of some of the channels in the Framework MTG have changed. Channel Number OLD FUNCTION New Function ------- ----------------------- ------------------------------ 14 * This continues to be Not Yet Assigned. 15 Not Yet Assigned Skip 1 Beam Crossing 16 * This continues to be the LED Control for the Framework. 17 Reset All MTG's Skip 2 Beam Crossings 18 Start of Single Cycle Skip 10 Beam Crossings 19 End of Single Cycle L1 Triggers per Bunch DBSC Clock 20 * This continues to be the Increment the Event Number DBSC Clk. 21 * This continues to be the Specific Triggers Fired Strobe waveform. 22 * This continues to be the COMINT Clock. 23 * This continues to be the First 4 "Ticks" of each Beam Crossing. 24 * This continues to be the Last 4 "Ticks" of each Beam Crossing. 25 Not Yet Assigned P1 Crossing Gate 26 Not Yet Assigned P1 Crossing Gate 27 Not Yet Assigned P1 Crossing Gate 28 Not Yet Assigned P1 Crossing Gate 29 Not Yet Assigned P1 Crossing Gate 30 Not Yet Assigned P1 Crossing Gate 31 Not Yet Assigned Last 4 "Ticks" of the Turn 32 Not Yet Assigned 4 "Ticks" after the End of the Turn * ==> The use of this MTG Channel has not changed. The P1 through P6 Gate signals are High during the period that the data from the given beam crossing is being processed (e.g. P1 is high while the event data from the P1 crossing is being processed). The old setup only required channels #20 and #21 to receive the Latched Global Specific Triggers Fired signals from the TLM. The new use of the MTG channels requires that channels #15, #17, #18, #19, #20, and #21 all receive the Latched Global Specific Trigger Fired Signal from the TLM. In all cases this signal is received by the External Enable input. This signal may be bussed via headers in the terminator resistor sockets. How to Program MTG PreSet Count and Terminal Count for both 6 on 6 and 4 on 4 ----------------------------------------------------------------------------- 6 Bunches on 6 Bunches ---------------------- The first MTG PROM Address "played" during the 6 on 6 operation is decimal address 100. The last MTG PROM Address played for 6 on 6 operation is 651. This is 6 sequences of 92 addresses each or a total of 552 PROM locations played. During normal 6 on 6 operation we will set the PreSet Address to be decimal 100, we will let the Master Clock cause our MTG's to "wrap" at decimal address 651, and we will set our Terminal Count Address to be decimal 655 which is 4 past the normal "wrap" address. To set this up: Function Load Address Function Decimal Data Why do this -------- ---------- -------------- ----------------------------- 33 PROM Address 100 PreSet PROM Address Counter Counter PRESET to Address 100. Least Signf Byte 34 PROM Address 0 PreSet PROM Address Counter Counter PRESET to Address 100. No bits Most Signf Byte needed in the MSByte. 35 PROM Address 143 PROM Address Terminal Count Counter Terminal is decimal 655 (note this is Count LSByte 4 passed the normal "wrap" address of 651. (2 * 256) + 143 = 655 The 143 is the Least Signf Byte. 36 PROM Address 2 (2 * 256) + 143 = 655 Counter Terminal The Most Significant Byte Count MSByte is the 2. 37 PROM Address 22 Enable Beam Crossing Reset Counter Control Enable Terminal Count Reset Status Register Select PROM Addresses 0:1023 Select Accelerator Clock Input 4 Bunches on 4 Bunches ---------------------- The first MTG PROM Address "played" during the 4 on 4 operation is decimal address 1100. The last MTG PROM Address played for 4 on 4 operation is decimal 1655. This is 4 sequences of 139 addresses each or a total of 556 PROM locations played. During normal 4 on 4 operation we will set the PreSet Address to be decimal 1100, we will let the Master Clock cause our MTG's to "wrap" at decimal address 1655, and we will set our Terminal Count Address to be decimal 1659 which is 4 past the normal "wrap" address. To set this up: Function Load Address Function Decimal Data Why do this -------- ---------- -------------- ----------------------------- 33 PROM Address 76 PreSet PROM Address Counter Counter PRESET to Address 1100. Least Signf Byte 1100 - 1024 = 76 34 PROM Address 0 PreSet PROM Address Counter Counter PRESET to Address 76. No bits Most Signf Byte needed in the MSByte. 35 PROM Address 123 PROM Address Terminal Count Counter Terminal is decimal 1659 (note this is Count LSByte 4 passed the normal "wrap" address of 1655). 1659 - 1024 = 635 (2 * 256) + 123 is equal 635. 123 is the Least Signf Byte. 36 PROM Address 2 1659 - 1024 = 635 Counter Terminal (2 * 256) + 123 = 635 Count MSByte The MSByte is the 2. 37 PROM Address 30 Enable Beam Crossing Reset Counter Control Enable Terminal Count Reset Status Register Select PROM Addresses 1024:2047 Select Accelerator Clock Input