TITLE Level 1.5 DBSC Begin/End Latch PAL PATTERN MTG L1.5 Begin/End Latch REVISION 1.02 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 17-JUN-1992 ; The detailed description of this device is at the end of this file. CHIP BegEndLt PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD Sel_Comp Comp_Bit LD_Reg ROM_In /RD_Reg NC1 Sin_Strt ;9 10 11 12 13 14 15 16 Sin_Stop GND /Glob_OE /End_Lat /Beg_Lat CmpBitLt SelCmpLt Spr_Reg ;17 18 19 20 CmpBitOu SelCmpOu /DBSC_Lat Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /Veto) is inverted before ; being driven off-card. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. /SelCmpLt := /Sel_Comp ; This term is the CBUS Data In Bit /SelCmpLt.CLKF = LD_Reg ; #1, latched by the rising edge of /SelCmpLt.TRST = Vcc ; the Load Register (aka Write FA /SelCmpLt.SETF = GND ; #n). It is always output- /SelCmpLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; It is used to select either the ; "real" operation of this PAL, ; or to force the output to a ; defined state based on the ; stored Computer Bit. /CmpBitLt := /Comp_Bit ; This term is the CBUS Data In Bit /CmpBitLt.CLKF = LD_Reg ; #2, latched by the rising edge of /CmpBitLt.TRST = Vcc ; the Load Register (aka Write FA /CmpBitLt.SETF = GND ; #n). It is always output- /CmpBitLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; This is the bit used as the output ; if the "Computer Mode" is selected. SelCmpOu := SelCmpLt ; This term is the CBUS Data Out Bit SelCmpOu.CLKF = GND ; #1. It is not latched. It is SelCmpOu.TRST = RD_Reg ; output-enabled while Read Register SelCmpOu.SETF = Vcc ; (aka /Read FA #n) is low. It SelCmpOu.RSTF = Vcc ; reflects the state of SelCmpLt. CmpBitOu := CmpBitLt ; This term is the CBUS Data Out Bit CmpBitOu.CLKF = GND ; #2. It is not latched. It is CmpBitOu.TRST = RD_Reg ; output-enabled while Read Register CmpBitOu.SETF = Vcc ; (aka /Read FA #n) is low. It CmpBitOu.RSTF = Vcc ; reflects the state of CmpBitLt. Spr_Reg := DBSC_Lat ; This term is the CBUS Data Out Bit Spr_Reg.CLKF = GND ; #3. It is not latched. It is Spr_Reg.TRST = RD_Reg ; output-enabled while Read Register Spr_Reg.SETF = Vcc ; (aka /Read FA #n) is low. It Spr_Reg.RSTF = Vcc ; reflects the state of the DBSC ; Latch output Beg_Lat := Sin_Strt ; This term is the Begin Latch. Beg_Lat.CLKF = ROM_In ; It goes high on the first ROM_In Beg_Lat.TRST = Vcc ; rising edge which occurs while Beg_Lat.SETF = GND ; Single Start is high. It will Beg_Lat.RSTF = /Sin_Strt ; become low as soon as the ; Single Start becomes low. Recall ; that Single Start is only active ; for one Level 1.5 period. End_Lat := Sin_Stop ; This term is the End Latch. It End_Lat.CLKF = /ROM_In ; goes high on the first ROM_In End_Lat.TRST = Vcc ; falling edge which occurs while End_Lat.SETF = GND ; Single Stop is high. It will End_Lat.RSTF = /Sin_Stop ; become low as soon as Single ; Stop becomes low. Recall that ; Single Stop is only active for ; one Level 1.5 period. DBSC_Lat := SelCmpLt * CmpBitLt + /SelCmpLt * Beg_Lat + /SelCmpLt * End_Lat DBSC_Lat.CLKF = GND ; This term is the Latch to the DBSC_Lat.TRST = Vcc ; DBSC. If the Computer Mode is DBSC_Lat.SETF = Vcc ; selected, this term follows the DBSC_Lat.RSTF = Vcc ; latched Computer Bit. Otherwise, ; it is the OR of the Begin Latch ; and the End Latch. It is ; not latched, and is always ; output-enabled. ; Description of this DBSC Begin/End Latch PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket on ; the L1.5 CONTROL MTG card. ; The following table shows how to setup these ; connections for the maximum flexability from the 16RA8 PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Sel Computer Socket pin tied to device pin. ; 0: make Begin/End Latch ; 1: listen to Computer Bit ; ; 3 Data 2 In Computer Bit Socket pin tied to device pin. ; 1: Computer Bit HIGH ; 0: Computer Bit LOW ; ; 4 Data 3 In Load Reg Input Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. ; ; 5 Data 4 In ROM BIT In Device pin tied to socket pin 12. ; Socket pin not used. ; ; 6 Data 5 In Read Reg Input Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; ; 7 Data 6 In Not Used Socket pin tied to device pin. ; ; 8 Ext-Enb Single Start Socket pin tied to device pin. ; 1: In the First L1.5 Decision ; Cycle ; 0: Otherwise ; ; 9 Ext-Bit Single Stop Socket pin tied to device pin. ; 1: In the Last L1.5 Decision Cycle ; 0: Otherwise ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit End Latch Device pin not connected to socket ; pin. Socket pin connected to device ; pin 5. ; ; 13 Data 6 Out Begin Latch Device pin not connected to socket pin ; ; 14 Data 5 Out Comp Bit Latch Device pin not connected to socket pin ; ; 15 Data 4 Out Sel Comp Latch Device pin not connected to socket pin ; ; 16 Data 3 Out Spare Register Socket pin tied to device pin. ; ; 17 Data 2 Out Computer Bit Socket pin tied to device pin. ; Output ; ; 18 Data 1 Out Sel Comp Output Socket pin tied to device pin. ; ; 19 Channel Out DBSC Latch Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; ; This PAL performs the Level 1.5 DBSC Begin/End Latch logic. ; ; It has two CBUS-loadable single-bit registers, "Sel Computer Latch" ; and "Computer Bit Latch," which are loaded on the rising edge of ; the "Load Register" line. Both of these registers are CBUS readable, ; on the pins "Select Computer Output" and "Computer Bit Output" ; respectively, while the "Read Register" pin is low. ; Also, the pin "Spare Register" contains the status of the "DBSC Latch" ; while the "Read Register" line is low. ; ; The processing logic is as follows: ; ; COMPUTER MODE ; ------------- ; The output follows the Computer Bit Latch ; ; BEGIN/END LATCH MODE ; -------------------- ; The output goes high at the first ROM_In rising edge while ; the Single Start is high. It goes low when the Single Start ; goes low. Single Start will only be active during the first ; Level 1.5 Decision Cycle. ; The output also goes high at the first ROM_In falling edge ; while the Single Stop is high. It goes low when the Single ; Stop goes low. Single Stop will only be active during the ; last Level 1.5 Decision Cycle. SIMULATION ; Enable tracing of several signals TRACE_ON Beg_Lat End_Lat DBSC_Lat ; Disable preload, enable global OE (done in wiring on PCB) SETF /Pre_LD Glob_OE /RD_Reg /LD_Reg ; Set the inputs to the normal "quiescent" state SETF /Sin_Strt /Sin_Stop /ROM_In ; Simulate CBUS cycle to program the PAL to listen to "real" signals SETF /Sel_Comp /Comp_Bit SETF LD_Reg SETF /LD_Reg ; Check that quiescent state is OK CHECK /Beg_Lat /End_Lat /DBSC_Lat ; Generate the pattern SETF Sin_Strt CHECK /Beg_Lat /End_Lat /DBSC_Lat ; Hit the ROM. Begin Latch, DBSC Latch should go high SETF ROM_In CHECK Beg_Lat /End_Lat DBSC_Lat ; Now drop the ROM. Should see no change SETF /ROM_In CHECK Beg_Lat /End_Lat DBSC_Lat ; Now drop Single Start. Outputs should go low SETF /Sin_Strt CHECK /Beg_Lat /End_Lat /DBSC_Lat ; Now hit the ROM. Outputs should stay low SETF ROM_In CHECK /Beg_Lat /End_Lat /DBSC_Lat ; Drop the ROM. No change SETF /ROM_In CHECK /Beg_Lat /End_Lat /DBSC_Lat ; Now set Single Stop. Still no change SETF Sin_Stop CHECK /Beg_Lat /End_Lat /DBSC_Lat ; And set the ROM. Still no change SETF ROM_In CHECK /Beg_Lat /End_Lat /DBSC_Lat ; And now drop the ROM. End Latch, DBSC Latch should go high SETF /ROM_In CHECK /Beg_Lat End_Lat DBSC_Lat ; And now drop Single Stop. Outputs should go low SETF /Sin_Stop CHECK /Beg_Lat /End_Lat /DBSC_Lat TRACE_OFF