TITLE Level 1.5 Clear Most Recent Trigger to COMINT PAL PATTERN MTG L1.5 Clear Most Recent Trigger Style #2 REVISION 1.00 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 2-JUL-1992 ; The detailed description of this device is at the end of this file. CHIP ClrTrg_2 PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 LD_Reg Dat_In_1 Dat_In_2 Dat_In_3 Dat_In_4 Dat_In_5 L15_HTC NC1 ;9 10 11 12 13 14 15 16 St_Digit GND /RD_Reg ROM_In /StDgtL15 C_BitEna /CMRT Spr_Reg ;17 18 19 20 M_1 M_0 /ClrMRTrg Vcc ; Recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /ClrMRTrg) is inverted before ; being driven off-card. EQUATIONS /M_0 := /Dat_In_1 ; This term is the CBUS Data In Bit ; #1, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the low-order mode ; select bit. See table below. /M_1 := /Dat_In_2 ; This term is the CBUS Data In Bit ; #2, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the high-order mode ; select bit. See table below. /Spr_Reg := /ClrMRTrg ; This term is the READ-ONLY CBUS ; Data Bit Output #3. It reflects ; the state of the Clear Most ; Recent Trigger ; output, latched by the rising edge ; of Load Register (aka Write FA #n). ; It is output-enabled while Read ; Register (aka /Read FA #n) is low. /C_BitEna := /Dat_In_5 ; This term is the CBUS Data In Bit ; #5, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer ; Bit and Enable bit. When in ; Computer Mode, the Computer Enable ; is assumed high, and this bit ; is the Computer Bit. When not ; in Computer Mode, this bit ; is the Computer Enable. ; Note that the possibility of ; watching the Computer Bit enabled ; by the Start Digitize input is ; not available on the Clear Most ; Recent Trigger ; PAL, but it is available on the ; Start Digitize PAL. ROM_In.TRST = GND ; This term is an input StDgtL15 = /M_0 * M_1 * ROM_In * St_Digit + /M_0 * M_1 * L15_HTC * StDgtL15 StDgtL15.TRST = Vcc ; This is the Start Digitize and L15 ; signal. ; If in Level-1.5 Mode, ; it goes high when the ROM Input ; and Start Digitize Input both go ; high, and is held high while the ; Level 1.5 Hold Transfer Control is ; high. When the Level 1.5 Hold ; Transfer Control falls low, it ; will remain high only if the Start ; Digitize Input and the ROM Input ; are high. The Level 1.5 Hold ; Transfer Control will fall only ; while the ROM Input is high. ; If not in Level-1.5 Mode, it will ; never go high. CMRT = /M_0 * M_1 * StDgtL15 * /St_Digit * ROM_In + /M_0 * M_1 * /L15_HTC * CMRT + /M_0 * M_1 * CMRT * ROM_In CMRT.TRST = Vcc ; This is the (internal) Clear ; Most Recent Trigger ; signal. It goes high when we are ; in Level-1.5 Mode, and the Start ; Digitize and L15 signal is high, ; and the ROM Input is high, and the ; Start Digitize Input is low. That ; is, it becomes high only if the ; Level 1.5 Trigger Framework has ; rejected all Specific Triggers. ; Once it goes high, ; it will remain high while either ; the ROM Input is high or the Level ; 1.5 Hold Transfer Control is low. ; Recall that the Start Digitize and ; Level 1.5 signal goes low at the ; falling edge of the ROM Input ; before the last cycle. The Level ; 1.5 Hold Transfer control will be ; low at that time, so the (internal) ; Clear Most Recent Trigger signal ; will remain high ; until the Level 1.5 Hold Transfer ; Control goes high again. ; The Clear Most Recent Trigger ; signal need not be synchronized ; with anything. ClrMRTrg = /M_0 * M_1 * CMRT * /StDgtL15 + M_0 * M_1 * St_Digit * L15_HTC + M_0 * M_1 * C_BitEna * L15_HTC + M_0 * /M_1 * C_BitEna ClrMRTrg.TRST = Vcc ; This term is the Clear Most Recent ; Trigger. If in Level-1.5 Mode, it ; is high only when the Internal ; Clear Most Recent Trigger signal ; is high BUT the Start Digit L15 ; signal is low. It will therefore ; only be high from the falling edge ; of the Level 1.5 Hold Transfer ; Control until the rising edge ; of the final pulse of the L1.5 ; Hold Transfer Control signal ; (if it is high at all). ; Additionally, if in Computer Mode, ; it will be high if the Computer ; Bit/Enable is high. And if ; in Display Level 1.5 Hold Transfer ; Control Signal Mode, it is high if ; the Level 1.5 Hold Transfer Control ; signal is high and either Start ; Digitize or Computer Enable are high ; ; Description of this Clear Most Recent L1.5 Specific Trigger PAL ; ; This circuit uses a 16V8 type of PAL. There are some special ; connections required to plug this 16V8 PAL into a Bit PAL socket on ; the HOLD TRANSFER MTG card. Recall that a HOLD TRANSFER MTG is different ; from a normal timing signal MTG in that the HOLD TRANSFER MTG has a ; "Global External" input line in place of the normal timing signal MTG's ; "Data 6 In" line. The following table shows how to setup these ; connections for the maximum flexability from the 16V8 PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg CLOCK Socket pin tied to device pin. ; pos edge ; ; 2 Data 1 In Mode Bit 0 Socket pin tied to device pin. ; ; 3 Data 2 In Mode Bit 1 Socket pin tied to device pin. ; ; 4 Data 3 In Not used Socket pin tied to device pin. ; ; 5 Data 4 In Not used Socket pin tied to device pin. ; ; 6 Data 5 In Computer Bit/ Socket pin tied to device pin. ; Computer Enable ; ; 7 Glob-Ext L1.5 Hold Socket pin tied to device pin. ; Transfer Control ; ; 8 Ext-Enb Not used Socket pin tied to device pin. ; ; 9 Ext-Bit Start Digitize Socket pin tied to device pin. ; ; 10 GND Device GND Socket pin tied to device pin. ; ; 11 Read Reg. Global Output Socket pin tied to device pin. ; Low Active Enable Low Active ; ; 12 ROM Bit ROM Bit Input Socket pin tied to device pin. ; ; 13 Data 6 Out Start Digitize Device pin not connected to socket pin ; and Level 1.5 ; ; 14 Data 5 Out Computer Bit/ Socket pin tied to device pin. ; Computer Enable ; Output ; ; 15 Data 4 Out (internal) Clear Device pin not connected to socket pin ; Most Recent Trg ; ; 16 Data 3 Out Spare Register Socket pin tied to device pin. ; ; 17 Data 2 Out Mode Bit 1 Out Socket pin tied to device pin. ; ; 18 Data 1 Out Mode Bit 0 Out Socket pin tied to device pin. ; ; 19 Channel Out Clear Most Rec. Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; ; ; This PAL performs the Clear Most Recent Trigger to COMINT logic. ; ; It has 3 CBUS-loadable and CBUS-readable registers: ; Mode Bit 0 ; Mode Bit 1 ; Computer Bit/Computer Enable ; ; Additionally, it has one CBUS READ-ONLY register: ; Spare Register (reflects the state of the Clr Most Recent output) ; ; It can be in one of 4 Modes, based on the Mode Bit 0 and 1: ; ; M_1 M_0 Mode ; ----- ----- ------ ; 0 0 Level-1 style Clear Most Recent Trg processing ; 0 1 Display Computer Bit (no enable control) ; 1 0 Level-1.5 style Clear Most Recent Trg processing ; 1 1 Display Level 1.5 Hold Transfer Control signal, ; enabled by either St_Digit or Computer Enable ; ; The processing for Display Computer Bit Mode or Display Level 1.5 Hold ; Transfer Control Signal Mode is self-explanatory. ; ; The processing for the Level-1 Style Clear Most Recent Trigger Mode ; forces the output to a logic LOW at all times. Clear Most Recent ; Trigger is not used in the Level-1 Mode. ; ; The processing for the Level 1.5 Style Clear Most Recent Trigger Mode ; is as follows: ; Clear Most Recent Trigger will go high at the falling edge of the ; Level 1.5 Hold Transfer Control signal IF the Start Digitize input ; disappeared during that Level 1.5 Cycle. It will remain high until ; the rising edge of the "final" pulse of the Level 1.5 Hold Transfer ; Control signal. Thus the Clear Most Recent Trigger will only be ; high for one Beam Crossing. SIMULATION ; Set up the trace: TRACE_ON St_Digit ROM_In M_1 M_0 L15_HTC StDgtL15 CMRT ClrMRTrg ; Initialize all important pins SETF /St_Digit /ROM_In /L15_HTC ; Do "CBUS Cycles" to set Level-1 mode SETF /Dat_In_1 /Dat_In_2 /Dat_In_5 CLOCKF LD_Reg ; TEST: NORMAL LEVEL 1 MODE ; Hit Start Digitize SETF St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now drop Start Digitize SETF /St_Digit CHECK /ClrMRTrg ; TEST: LEVEL 1 MODE, BUT LEVEL 1.5 IS TALKING TOO ; Hit Start Digitize SETF St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now hit Level 1.5 Hold Transfer Control SETF L15_HTC CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now drop Start Digitize and Level 1.5 HTC SETF /St_Digit /L15_HTC CHECK /ClrMRTrg ; TEST: LEVEL 1.5 MODE, NO LEVEL 1.5 SIGNALS ; Initialize all important pins SETF /St_Digit /ROM_In /L15_HTC ; Do "CBUS Cycles" to set Level-1 mode SETF /Dat_In_1 Dat_In_2 /Dat_In_5 CLOCKF LD_Reg ; Hit Start Digitize SETF St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now drop Start Digitize SETF /St_Digit CHECK /ClrMRTrg ; TEST: LEVEL 1.5 MODE, LEVEL 1.5 ACCEPTS >= 1 ST DIGITIZING THIS G.S. ; Hit Start Digitize SETF St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now hit Level 1.5 Hold Transfer Control SETF L15_HTC CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop Level 1.5 Hold Transfer Control SETF /L15_HTC CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now hit L1.5 HTC with final pulse SETF L15_HTC CHECK /ClrMRTrg SETF /L15_HTC CHECK /ClrMRTrg ; Now drop Start Digitize SETF /St_Digit CHECK /ClrMRTrg ; TEST: LEVEL 1.5 MODE, LEVEL 1.5 REJECTS ALL ST DIGITIZING THIS G.S. ; Hit Start Digitize SETF St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now hit Level 1.5 Hold Transfer Control SETF L15_HTC CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now drop Start Digitize SETF /St_Digit CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK /ClrMRTrg ; Now hit ROM_In SETF ROM_In CHECK /ClrMRTrg ; Now drop Level 1.5 Hold Transfer Control SETF /L15_HTC CHECK ClrMRTrg ; Now drop ROM_In SETF /ROM_In CHECK ClrMRTrg ; Now pulse Level 1.5 Hold Transfer Control for last time SETF L15_HTC CHECK /ClrMRTrg SETF /L15_HTC CHECK /ClrMRTrg TRACE_OFF