TITLE Level 1.5 Confirm Specific Trigger #i PAL PATTERN MTG L1.5 Confirm ST REVISION 1.08 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 28-MAY-1992 ; The detailed description of this device is at the end of this file. CHIP L15_conf PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD Sel_Comp Comp_Ans LD_Reg ROM_In /RD_Reg L15_Cycl ST_Fired ;9 10 11 12 13 14 15 16 Done_Ans GND /Glob_OE /Done_Lat /Rejected CmpAnsLt SelCmpLt DA_Out ;17 18 19 20 /Dly_Done SelCmpOu /Confirm Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /Confirm) is inverted before ; being driven off-card. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. /SelCmpLt := /Sel_Comp ; This term is the CBUS Data In Bit /SelCmpLt.CLKF = LD_Reg ; #1, latched by the rising edge of /SelCmpLt.TRST = Vcc ; the Load Register (aka Write FA /SelCmpLt.SETF = GND ; #n). It is always output- /SelCmpLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; It is used to select either the ; "real" Done/Answer line or the ; Latched CBUS Data Bit #2 as the ; input to the CONFIRM decision. /CmpAnsLt := /Comp_Ans ; This term is the CBUS Data In Bit /CmpAnsLt.CLKF = LD_Reg ; #2, latched by the rising edge of /CmpAnsLt.TRST = Vcc ; the Load Register (aka Write FA /CmpAnsLt.SETF = GND ; #n). It is always output- /CmpAnsLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; This is the bit used as the input ; to the CONFIRM if the "CBUS" ; Answer line is selected. SelCmpOu := SelCmpLt ; This term is the CBUS Data Out Bit SelCmpOu.CLKF = GND ; #1. It is not latched. It is SelCmpOu.TRST = RD_Reg ; output-enabled while Read Register SelCmpOu.SETF = Vcc ; (aka /Read FA #n) is low. It SelCmpOu.RSTF = Vcc ; reflects the state of SelCmpLt. DA_Out := Done_Ans ; This term is the CBUS Data Out Bit DA_Out.CLKF = GND ; #3. It is not latched. It is DA_Out.TRST = RD_Reg ; output-enabled while Read Registed DA_Out.SETF = Vcc ; (aka /Read FA #n) is low. It DA_Out.RSTF = Vcc ; reflects the state of Done_Ans Done_Lat := Done_Ans * ST_Fired + SelCmpLt Done_Lat.CLKF = ROM_In * /Done_Lat Done_Lat.TRST = Vcc ; This term is the Latched Done. It Done_Lat.SETF = GND ; is latched on the rising edge of Done_Lat.RSTF = /L15_Cycl ; ROM_In, only if the Latched Done ; is not asserted. It will be ; asserted if the "CBUS" Done/Answer ; is not selected, and the "real" ; Done/Answer is asserted, and the ; Level 1.5 Cycle is in progress, and ; the L1 Specific Trigger has fired. ; ; Once asserted, it remains asserted ; (independent of the inputs) until ; the Level 1.5 Cycle is completed. ; ; When the Level 1.5 Cycle is not ; in progress, this term is held ; low. Dly_Done := Done_Lat ; This term is the Delayed Done Dly_Done.CLKF = /ROM_In ; Latch. It goes high on the Dly_Done.TRST = Vcc ; falling edge of the ROM_In Dly_Done.SETF = GND ; after the Latched Done goes Dly_Done.RSTF = /L15_Cycl ; high. It exists to eliminate ; a race condition between the ; rising edge of the Latched Done ; and the rising edge of the ; ROM_In. If this signal is not ; used, a fast Latched Done (one ; which arrives at the ; Confirm logic before the ; rising edge of ROM_In), the ; Done but Not Vetoed logic would ; examine the Done/Answer during ; the DONE 1/2 Cycle, not the ; ANSWER 1/2 Cycle, and incorrectly ; decide that the Specific Trigger ; should be Confirmed (regardless of ; the real Answer). ; ; This term is not "held," because ; its input is held. ; ; This term is kept at reset while ; the Level 1.5 Cycle is not ; in progress. Rejected := SelCmpLt * /CmpAnsLt + /SelCmpLt * /Done_Ans * ST_Fired Rejected.CLKF = /ROM_In * /Rejected Rejected.TRST = Vcc ; This term is the Rejected signal. Rejected.SETF = GND ; It is latched on the falling edge Rejected.RSTF = /L15_Cycl ; of ROM_In only if the Rejected ; signal is not asserted. ; It is asserted if the "CBUS" ; Done/Answer is NOT selected, and ; the "real" Done/Answer is NOT ; asserted, and the L1 Specific ; Trigger has fired. ; It will also be asserted ; if the "CBUS" Done/Answer is ; selected, and the "CBUS" Done/ ; Answer is NOT asserted. In either ; case, once asserted it remains ; asserted until the Level 1.5 ; Cycle completes. ; ; This term is held at reset while ; the Level 1.5 Cycle is not in ; progress. Confirm := SelCmpLt * CmpAnsLt + /SelCmpLt * Done_Ans * ST_Fired Confirm.CLKF = /ROM_In * Dly_Done * /Rejected * /Confirm Confirm.TRST = Vcc Confirm.SETF = GND ; This term is the Confirm. It is Confirm.RSTF = /L15_Cycl ; latched on the falling edge of ; ROM_In only if the Delayed Done ; signal is asserted, and the Rejected ; signal is NOT asserted, and the ; Confirm signal is also NOT asserted. ; This is the appropriate time to ; examine the "real" Done/Answer line. ; It will be asserted if the "CBUS" ; Done/Answer is NOT selected, and the ; "real" Done/Answer is high, and the ; L1 Specific Trigger has fired. ; It will also be asserted if the ; "CBUS" Answer is selected, and the ; "CBUS" Answer is high, and the L1.5 ; Cycle is in progress. ; ; In either case, once asserted it ; remains asserted until the Level ; 1.5 Cycle is completed. ; ; This term is held low while the ; Level 1.5 Cycle is not in progress ; ; Although a race condition may appear ; to exist between /ROM_In and ; /Rejected (that is, a "fast" ; /Rejected may mask a "slow" ; /ROM_In), this situation may ; only occur when the Specific Trigger ; should be Confirmed Rejected. In ; this case, the Confirm should remain ; low, and will do so regardless of ; whether it receives a final clock ; pulse ; ; Description of this Confirm L1.5 Specific Trigger PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket on ; the VETO/CONFIRM MTG card. Recall that a VETO/CONFIRM MTG is different ; from a normal timing signal MTG in that the VETO/CONFIRM MTG has a ; "Global External" input line in place of the normal timing signal MTG's ; "Data 6 In" line. The following table shows how to setup these ; connections for the maximum flexability from the 16RA8 PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Sel Computer Socket pin tied to device pin. ; 0: listen to Done_Ans ; 1: listen to Comp_Ans ; ; 3 Data 2 In Computer Answer Socket pin tied to device pin. ; 1: simulate the L1.5 Specific Trigger ; CONFIRM state ; 0: simulate the L1.5 Specific Trigger ; NOT_CONFIRM state ; ; 4 Data 3 In Load Reg Input Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. ; ; 5 Data 4 In ROM BIT In Device pin tied to socket pin 12. ; Socket pin not used. ; ; 6 Data 5 In Read Reg Input Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; ; 7 Glob-Ext L1.5 Cycle Socket pin tied to device pin. ; 1: L1.5 Cycle in progress ; 0: L1.5 Cycle not in progress ; ; 8 Ext-Enb L1 SpTrg Fired Socket pin tied to device pin. ; 1: L1 Specific Trigger #n Fired ; 0: L1 Specific Trigger #n not Fired ; ; 9 Ext-Bit L1.5 SpTrg Socket pin tied to device pin. ; DONE/ANSWER During DONE 1/2 cycle: ; 1: All terms DONE ; 0: >= 1 term not DONE ; During ANSWER 1/2 cycle: ; 1: No terms confirmed rejected ; 0: >=1 term confirmed rejected ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit Latched Done Device pin not connected to socket ; pin. Socket pin connected to device ; pin 5. ; ; 13 Data 6 Out Rejected Device pin not connected to socket pin ; ; 14 Data 5 Out Comp Ans Latch Device pin not connected to socket pin ; ; 15 Data 4 Out Sel Comp Latch Device pin not connected to socket pin ; ; 16 Data 3 Out Done/Ans Output Socket pin tied to device pin. ; ; 17 Data 2 Out Delayed Latched Device pin not connected to socket pin ; Done ; ; 18 Data 1 Out Sel Comp Output Socket pin tied to device pin. ; ; 19 Channel Out Confirm Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; This PAL performs the Level 1.5 Confirm Specific Trigger #i logic. ; ; It has two CBUS-loadable single-bit registers, "Sel Computer Latch" ; and "Computer Answer Latch," which are loaded on the rising edge of ; the "Load Register" line. The "Sel Computer Latch" register ; is CBUS readable on the pin "Select Computer Output" while the "Read ; Register" pin is low. Also, the pin "Done/Answer Output" contains ; the status of "Done/Answer Input" while the "Read Register" line ; is low. ; ; Additionally, the CONFIRM processing logic is performed. The table ; below illustrates the CONFIRM processing logic. ; ; L15_Cycl ST_Fired SelCmpLt CmpAnsLt Done_Ans ROM_In Confirm ; -------- -------- -------- -------- -------- ------ ------- ; 0 X X X X X 0 ; 1 X 1 0 X fall edge 0 ; 1 X 1 1 X fall edge 1 ; 1 0 0 X X fall edge 0 ; 1 1 0 X 0 fall edge 0 ; 1 1 0 X 1 f.e. before DONE 0 ; 1 1 0 X 1 f.e. after DONE 1 ; ; ; Note that the Confirm input is sampled (that is, the "Answer" ; signal, either computer-generated or the external inputs) at ; the "Answer sampling point" (ROM_In falling edge). If the "Answer" ; signal is high following the reception of the "Done" signal, ; the Specific Trigger is Confirmed and the Confirm will ; remain stable until the end of the Level 1.5 Cycle, when it will ; be reset. If the "Answer" is low at this time (or if it is ever low ; at any "Answer sampling point"), the Specific Trigger is Rejected, and ; the Confirm can not be asserted until the logic has been reset (at the ; end of the Level 1.5 Cycle). If the "Done" signal is never received, ; the "Answer" cannot confirm the Specific Trigger. The Confirm signal ; is held at reset while the Level 1.5 Cycle is not in progress. ; ; Note also that if the "Computer Answer" is selected, the Confirm is ; still only allowed to change states SYNCHRONOUSLY with the ROM signal, ; and the Level 1.5 Cycle must be in progress to allow this change to ; occur. The Level 1 Specific Trigger need not have fired in this case. ; SIMULATION ; Enable tracing of several signals TRACE_ON L15_Cycl ST_Fired ROM_In Done_Ans Done_Lat Dly_Done Rejected Confirm ; Disable preload, enable global OE (done in wiring on PCB) SETF /Pre_LD Glob_OE /RD_Reg /LD_Reg ; Set the inputs to the normal "quiescent" state SETF /L15_Cycl /ST_Fired /ROM_In /Sel_Comp /Comp_Ans /Done_Ans ; Simulate CBUS cycle to program the PAL to listen to "real" signals SETF /Sel_Comp /Comp_Ans SETF LD_Reg SETF /LD_Reg ; TEST: CONFIRM SPECIFIC TRIGGER ; Fire the Specific Trigger SETF ST_Fired CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Start the L1.5 Cycle SETF L15_Cycl CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set NOT_DONE SETF /Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE signal SETF ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set ANSWER=YES (default until DONE) SETF Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the ANSWER signal SETF /ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set DONE, next answer is final SETF Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE signal SETF ROM_In CHECK /Confirm Done_Lat /Dly_Done /Rejected ; Set ANSWER=YES, we should CONFIRM this Specific Trigger SETF Done_Ans CHECK /Confirm Done_Lat /Dly_Done /Rejected ; Sample the ANSWER signal SETF /ROM_In ; We should have CONFIRMed, and be done, check: CHECK Confirm Done_Lat Dly_Done /Rejected ; We should ignore inputs. Set NOT_DONE SETF /Done_Ans CHECK Confirm Done_Lat Dly_Done /Rejected ; Sample the DONE SETF ROM_In CHECK Confirm Done_Lat Dly_Done /Rejected ; Set ANSWER=NO SETF /Done_Ans CHECK Confirm Done_Lat Dly_Done /Rejected ; Sample the Answer SETF /ROM_In CHECK Confirm Done_Lat Dly_Done Rejected ; Now end the Level 1.5 Cycle SETF /L15_Cycl SETF /ST_Fired ; The Confirm and Latched Done and Reject should now be low. Check: CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; TEST: CONFIRM SPECIFIC TRIGGER BEFORE ALL TERMS DONE ; Normal quiescent state SETF /L15_Cycl /ST_Fired /ROM_In /Sel_Comp /Comp_Ans /Done_Ans ; Fire the Specific Trigger SETF ST_Fired CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Start the Level 1.5 Cycle SETF L15_Cycl CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE SETF ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set the ANSWER=YES (default until done) SETF Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the ANSWER SETF /ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set NOT DONE SETF /Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE SETF ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set ANSWER=NO (should not CONFIRM after sampling) SETF /Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the ANSWER SETF /ROM_In CHECK /Confirm /Done_Lat /Dly_Done Rejected ; Change the DONE, ANSWER, and ST_FIRED. CONFIRM shouldn't change SETF /ST_Fired SETF Done_Ans SETF ROM_In SETF /ROM_In CHECK /Confirm /Done_Lat /Dly_Done Rejected ; Now end the Level 1.5 Cycle SETF /ST_Fired SETF /L15_Cycl CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; TEST: CONFIRM SPECIFIC TRIGGER AFTER ALL DONE ; Normal quiescent state SETF /L15_Cycl /ST_Fired /ROM_In /Sel_Comp /Comp_Ans /Done_Ans ; Fire the Specific Trigger SETF ST_Fired CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Start the Level 1.5 Cycle SETF L15_Cycl CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE SETF ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set the ANSWER=YES (default until done) SETF Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the ANSWER SETF /ROM_In CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Set DONE SETF Done_Ans CHECK /Confirm /Done_Lat /Dly_Done /Rejected ; Sample the DONE SETF ROM_In CHECK /Confirm Done_Lat /Dly_Done /Rejected ; Set ANSWER=NO (should not CONFIRM after sampling) SETF /Done_Ans CHECK /Confirm Done_Lat /Dly_Done /Rejected ; Sample the ANSWER SETF /ROM_In CHECK /Confirm Done_Lat Dly_Done Rejected ; Change the DONE, ANSWER, and ST_FIRED. CONFIRM shouldn't change SETF /ST_Fired SETF /Done_Ans SETF ROM_In SETF Done_Ans SETF /ROM_In CHECK /Confirm Done_Lat Dly_Done Rejected ; Now end the Level 1.5 Cycle SETF /ST_Fired SETF /L15_Cycl CHECK /Confirm /Done_Lat /Dly_Done /Rejected TRACE_OFF