TITLE Level 1.5 Control MTG Bit Pal #3 PATTERN MTG L1.5 Control Bit Pal #3 REVISION 1.02 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 29-MAY-1992 ; The detailed description of this device is at the end of this file. CHIP L15MTG01 PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 LD_Reg Dat_In_1 Dat_In_2 Dat_In_3 Dat_In_4 Dat_In_5 Dat_In_6 Ext_Enb ;9 10 11 12 13 14 15 16 Ext_Bit GND /RD_Reg ROM_In Spr_Reg Comp_Bit Comp_Enb Sel_ROM ;17 18 19 20 Sel_L15 Sel_Comp /Bitout Vcc ; Recall that, on the MTG, the signal connected to pin 19 ; (here called /Bitout) is inverted before being driven off-card. EQUATIONS /Sel_Comp := /Dat_In_1 ; This term is the CBUS Data In Bit ; #1, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Select ; Computer Mode bit. /Sel_L15 := /Dat_In_2 ; This term is the CBUS Data In Bit ; #2, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Select Level ; 1.5 Mode bit. /Sel_ROM := /Dat_In_3 ; This term is the CBUS Data In Bit ; #3, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Select ROM ; Mode bit. /Comp_Enb := /Dat_In_4 ; This term is the CBUS Data In Bit ; #4, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer ; Enable bit. /Comp_Bit := /Dat_In_5 ; This term is the CBUS Data In Bit ; #5, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer Bit. /Spr_Reg := /Bitout ; This term is the READ-ONLY CBUS ; Data Bit #6. It reflects the ; state of the Bitout at the time ; of the last CBUS Write to this ; PAL. It is output-enabled while ; /Read FA #n is low. ROM_In.TRST = GND ; This term is an input. Bitout = Sel_L15 * Ext_Enb * ROM_In + Sel_L15 * Ext_Enb * Bitout + Sel_L15 * /Ext_Bit * Bitout + Sel_L15 * /ROM_In * Bitout + Sel_ROM * Ext_Enb * ROM_In + Sel_ROM * Comp_Enb * ROM_In + Sel_Comp * Comp_Bit ; This term is the Bitout. If ; Level-1.5 operation is selected, ; the output is the ; External Enable ; while the ROM input is high, and ; latched while either the ROM ; input or the External Bit are ; low. The transparent latch ; is the glitch-free variety ; as described in the AMD PAL ; Device Handbook page 2-58. ; If ROM Mode is selected, the ; output is the ROM input, gated ; by either the External Enable ; or the Computer Enable. ; If Computer Mode is selected, ; the output Computer Bit, not ; gated. ; ; ; Description of this Level 1.5 Control MTG Bit #3 PAL ; ; This circuit uses a 16V8 type of PAL. There are NO special ; connections required to plug this 16V8 PAL into a Bit PAL socket on ; the Level 1.5 Control MTG. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg CLOCK Socket pin tied to device pin. ; pos edge ; ; 2 Data 1 In Select Socket pin tied to device pin. ; Computer Mode ; ; 3 Data 2 In Select Level Socket pin tied to device pin. ; 1.5 Mode ; ; 4 Data 3 In Select ROM Mode Socket pin tied to device pin. ; ; 5 Data 4 In Computer Enable Socket pin tied to device pin. ; ; 6 Data 5 In Computer Bit Socket pin tied to device pin. ; ; 7 Data 6 In Spare Register Socket pin tied to device pin. ; ; 8 Ext-Enb External Input Socket pin tied to device pin. ; #1 ; ; 9 Ext-Bit External Input Socket pin tied to device pin. ; #2 ; ; 10 GND Device GND Socket pin tied to device pin. ; ; 11 Read Reg. Global Output Socket pin tied to device pin. ; Low Active Enable Low Active ; ; 12 ROM Bit ROM Bit In Socket pin tied to device pin. ; ; 13 Data 6 Out Spare Register Socket pin tied to device pin. ; Output ; ; 14 Data 5 Out Computer Bit Out Socket pin tied to device pin. ; ; 15 Data 4 Out Computer Ena Out Socket pin tied to device pin. ; ; 16 Data 3 Out Select ROM Socket pin tied to device pin. ; Mode Output ; ; 17 Data 2 Out Select Level Socket pin tied to device pin. ; 1.5 Mode Output ; ; 18 Data 1 Out Select Computer Socket pin tied to device pin. ; Mode Output ; ; 19 Channel Out Bitout Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; ; ; Logic for this Level 1.5 Control MTG Bit #3 PAL ; ; This PAL is intended for use in the Level 1.5 Control MTG. ; ; In the Level 1.5 Mode: ; The output follows the External Enable while the ROM ; input is high. The output is latched when the ROM input is low ; or while the External Bit is low. ; ; In the ROM Mode: ; The output follows the ROM input while the External Enable input ; is high, or while the Computer Enable is high. ; ; In the Computer Mode: ; The output follows the Computer Bit always.