TITLE Level 1.5 Control MTG Bit Pal #6 PATTERN MTG L1.5 Control Bit Pal #6 REVISION 1.03 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 1-JUN-1992 ; The detailed description of this device is at the end of this file. CHIP L15MTG06 PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 LD_Reg Dat_In_1 Dat_In_2 Dat_In_3 Dat_In_4 Dat_In_5 NC1 Ext_Enb ;9 10 11 12 13 14 15 16 Ext_Bit GND /RD_Reg ROM_In NC2 Spr_Reg Comp_Bit ExtBitDs ;17 18 19 20 ExtEnbDs Sel_Comp /Bitout Vcc ; Recall that, on the MTG, the signal connected to pin 19 ; (here called /Bitout) is inverted before being driven off-card. EQUATIONS /Sel_Comp := /Dat_In_1 ; This term is the CBUS Data In Bit ; #1, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Select ; Computer Mode bit. /ExtEnbDs := /Dat_In_2 ; This term is the CBUS Data In Bit ; #2, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Disallow the ; External Enable bit. /ExtBitDs := /Dat_In_3 ; This term is the CBUS Data In Bit ; #3, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Disallow the ; External Bit bit. /Comp_Bit := /Dat_In_4 ; This term is the CBUS Data In Bit ; #4, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer Bit. /Spr_Reg := /Bitout ; This term is the READ-ONLY CBUS ; Data Bit #5. It reflects the ; state of the Bitout at the time ; of the last CBUS Write to this ; PAL. It is output-enabled while ; /Read FA #n is low. ROM_In.TRST = GND ; This term is an input. NC2.TRST = GND ; This term is not used. Bitout = Sel_Comp * Comp_Bit * Ext_Bit * Ext_Enb * /ExtBitDs * /ExtEnbDs + Sel_Comp * Comp_Bit * ExtBitDs * ExtEnbDs + /Sel_Comp * ROM_In + /Sel_Comp * Ext_Bit * Ext_Enb * /ExtBitDs * /ExtEnbDs + /Sel_Comp * Ext_Bit * /ExtBitDs * ExtEnbDs + /Sel_Comp * Ext_Enb * ExtBitDs * /ExtEnbDs ; This term is the Bitout. If ; Computer Mode is selected, the ; output is the Computer Bit, gated ; by the AND of the External Bit ; and the External Enable if the ; External Bit Disallow and the ; External Enable Disallow are ; not high, OR the ; AND of the External Bit Disallow ; and the External Enable Disallow. ; output. ; If not in the Computer Mode, the ; output is the ROM, BUT the output ; can be forced high by the AND of ; the External Bit and the External ; Enable. Additionally, the External ; External Bit AND the External ; Enable. Additionally, the External ; Bit and External Enable can ; individually be prevented from ; forcing the output high. ; ; ; Description of this Level 1.5 Control MTG Bit #6 PAL ; ; This circuit uses a 16V8 type of PAL. There are NO special ; connections required to plug this 16V8 PAL into a Bit PAL socket on ; the Level 1.5 Control MTG. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg CLOCK Socket pin tied to device pin. ; pos edge ; ; 2 Data 1 In Select Socket pin tied to device pin. ; Computer Mode ; ; 3 Data 2 In External Enable Socket pin tied to device pin. ; Disallow ; ; 4 Data 3 In External Bit Socket pin tied to device pin. ; Disallow ; ; 5 Data 4 In Computer Bit Socket pin tied to device pin. ; ; 6 Data 5 In Spare Register Socket pin tied to device pin. ; ; 7 Data 6 In Not used / Socket pin tied to device pin. ; Global External ; ; 8 Ext-Enb External Input Socket pin tied to device pin. ; #1 ; ; 9 Ext-Bit External Input Socket pin tied to device pin. ; #2 ; ; 10 GND Device GND Socket pin tied to device pin. ; ; 11 Read Reg. Global Output Socket pin tied to device pin. ; Low Active Enable Low Active ; ; 12 ROM Bit ROM Bit In Socket pin tied to device pin. ; ; 13 Data 6 Out Not Used. Socket pin tied to device pin. ; ; ; 14 Data 5 Out Spare Register Socket pin tied to device pin. ; Output ; ; 15 Data 4 Out Computer Bit Out Socket pin tied to device pin. ; ; 16 Data 3 Out External Bit Socket pin tied to device pin. ; Disallow Output ; ; 17 Data 2 Out External Enable Socket pin tied to device pin. ; Disallow Output ; ; 18 Data 1 Out Select Computer Socket pin tied to device pin. ; Mode Output ; ; 19 Channel Out Bitout Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; ; ; Logic for this Level 1.5 Control MTG Bit #6 PAL ; ; This PAL is intended for use in the Level 1.5 Control MTG. ; ; ; In the ROM Mode: ; The output follows the ROM input always. Additionally, the output ; can be forced high by the AND of the External Bit and the External ; Enable. The External Bit and External Enable can individually be ; disallowed from forcing the output high. ; ; In the Computer Mode: ; The output follows the Computer Bit, gated by the AND of the External ; Bit and External Enable IF the External Bit Disallow and the External ; Enable Disallow are not set, OR the AND of the External Bit Disallow ; and the External Enable Disallow.