TITLE Level 1.5 Very Long Timeout PATTERN MTG L1.5 Very Long Timeout (L1.5 CTRL MTG Channel 29 and/or 30) REVISION 1.02 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 12-MAR-1993 ; This is a modification of the Short/Long L15 Timeout PAL (file TimeOut.PDS) ; The Short/Long feature has been dropped in order to provide a longer ; timeout as requested by the L15 Muon People. ; The detailed description of this device is at the end of this file. CHIP LONGOUT PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD NC_2 NC_3 NC_4 ROM_In NC_6 NC_7 Ext_Enb ;9 10 11 12 13 14 15 16 Ext_Bit GND /Glob_OE /Cnt_0 /Cnt_1 /Cnt_2 /Cnt_3 /Cnt_4 ;17 18 19 20 /Cnt_5 /Cnt_6 /Timeout Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; ; L15 Stretch BAR is connected to Ext_Bit. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /Timeout) is inverted before ; being driven off-card. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. Cnt_0 := /Cnt_0 Cnt_0.CLKF = ROM_In * /Ext_Bit * /Timeout Cnt_0.TRST = Vcc Cnt_0.SETF = GND Cnt_0.RSTF = ROM_In * Ext_Bit ; This term is the LSB of the ; ripple counter. The output is ; ROM_In count value of 1. ; ; This term of the ripple counter ; (and all the higher order ripple ; counter terms) are reset when ; Ext_Bit AND ROM_In are both high. ; Ext_Bit is the L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Cnt_1 := /Cnt_1 ; This term is the next to LSB of Cnt_1.CLKF = /Cnt_0 ; the ripple counter. The output Cnt_1.TRST = Vcc ; is ROM_In count value of 2. Cnt_1.SETF = GND Cnt_1.RSTF = ROM_In * Ext_Bit Cnt_2 := /Cnt_2 ; This term is the nt nt LSB of Cnt_2.CLKF = /Cnt_1 ; the ripple counter. The output Cnt_2.TRST = Vcc ; is ROM_In count value of 4. Cnt_2.SETF = GND Cnt_2.RSTF = ROM_In * Ext_Bit Cnt_3 := /Cnt_3 ; This term is the nt nt nt LSB of Cnt_3.CLKF = /Cnt_2 ; the ripple counter. The output Cnt_3.TRST = Vcc ; is ROM_In count value of 8. Cnt_3.SETF = GND Cnt_3.RSTF = ROM_In * Ext_Bit Cnt_4 := /Cnt_4 ; This term is the nt nt MSB of Cnt_4.CLKF = /Cnt_3 ; the ripple counter. The output Cnt_4.TRST = Vcc ; is ROM_In count value of 16. Cnt_4.SETF = GND Cnt_4.RSTF = ROM_In * Ext_Bit Cnt_5 := /Cnt_5 ; This term is the next to MSB of Cnt_5.CLKF = /Cnt_4 ; the ripple counter. The output Cnt_5.TRST = Vcc ; is ROM_In count value of 32. Cnt_5.SETF = GND Cnt_5.RSTF = ROM_In * Ext_Bit Cnt_6 := /Cnt_6 ; This term is the MSB of Cnt_6.CLKF = /Cnt_5 ; the ripple counter. The output Cnt_6.TRST = Vcc ; is ROM_In count value of 64. Cnt_6.SETF = GND Cnt_6.RSTF = ROM_In * Ext_Bit Timeout := /Cnt_0 * Cnt_1 * Cnt_2 * /Cnt_3 * /Cnt_4 * /Cnt_5 * Cnt_6 + Timeout Timeout.CLKF = ROM_In * /Ext_Bit Timeout.TRST = Vcc Timeout.SETF = GND Timeout.RSTF = ROM_In * Ext_Bit ; This is the timeout term. ; Timeout is asserted ; on the rising edge of ROM_In ; after the counter has counted ; to 70 (i.e. the rising edge of ; ROM_In which causes the ; counter to increment to 71). ; Once the timeout is asserted, it ; remains asserted until reset. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. i.e. it is rest ; only when L1.5 Stretch is low. ; ; The clock only forces this bit to ; change if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; ; Description of this Level 1.5 Timeout PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket on ; the Level 1.5 Control MTG card. The following table shows how to ; set up these connections for the maximum flexibility from the 16RA8 ; PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active has no connection ; ; 2 Data 1 In Not Used Socket pin tied to device pin. ; ; 3 Data 2 In Not Used Socket pin tied to device pin. ; ; 4 Data 3 In Not used Socket pin tied to device pin. ; ; 5 Data 4 In ROM BIT In Device pin tied to socket pin 12. ; Socket pin not used. ; ; 6 Data 5 In Not used Socket pin tied to device pin. ; ; 7 Data 6 In Not Used Socket pin tied to device pin. ; ; 8 Ext-Enb Not Used Socket pin tied to device pin. ; ; 9 Ext-Bit L1.5 Stretch Socket pin tied to device pin. ; BAR Input ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active has not connection. ; ; 12 ROM Bit Count Bit 0 Device pin not connected to socket ; pin. Socket pin connected to device ; pin 5. ; ; 13 Data 6 Out Count Bit 1 Device pin not connected to socket pin ; ; 14 Data 5 Out Count Bit 2 Device pin not connected to socket pin ; ; 15 Data 4 Out Count Bit 3 Device pin not connected to socket pin ; ; 16 Data 3 Out Count Bit 4 Device pin not connected to socket pin ; ; 17 Data 2 Out Count Bit 5 Device pin not connected to socket pin ; ; 18 Data 1 Out Count Bit 6 Device pin not connected to socket pin ; ; 19 Channel Out Timeout Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; ; Description of this Level 1.5 Timeout PAL ; ; ; ; Once per beam crossing, if Level 1.5 Stretch is low, the counter ; and output stage flip flops will be reset. ; ; To initiate operation, the Level 1.5 Stretch signal must first become ; asserted. This allows a PROM pulse to act as a clock for the counter ; section of this PAL. The counter section of this PAL is a 7-bit ; ripple counter. ; ; On subsequent beam crossing cycles the pulses from the PROM will be used ; to cause this 7 bit ripple counter to increment. When this counter ; reaches max count (0110001 for 70 BX cycles) ; the output state flip flop will be prepared to change state. On the ; next clock pulse, the output state flip flop will change state, and the ; counter will increment by 1 ; The Timeout signal is fed back to the counter, ; masking all further clock signals to the counter until the device is ; reset. ; ; If the Level 1.5 Stretch signal is LOW during the time the PROM pulse ; is asserted, the counter will be reset to all zeros, no matter what ; value the counter had previously assumed. The output state flip flop ; will also be forced LOW if this combination of L1.5 Stretch and PROM ; occurs. ; ; ; ; Following is the SIMULATION data for the Skip 8 Beam Crossing PAL ; SIMULATION ; Enable tracing of several signals TRACE_ON Ext_Bit ROM_In Cnt_0 Cnt_1 Cnt_2 Cnt_3 Cnt_4 Cnt_5 Cnt_6 Timeout ; Disable preload, enable global OE (done in wiring on PCB) ; Set no loading or readback of the CBus data register. SETF /Pre_LD Glob_OE SETF /ROM_In /Ext_Bit PRLDF Timeout Cnt_0 Cnt_1 Cnt_2 Cnt_3 Cnt_4 Cnt_5 Cnt_6 SETF Ext_Bit ; Set Ext_Bit to its "reset" state and SETF ROM_In ; ROM_In clock it. This resets all flip SETF /ROM_In ; flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Cnt_5 CHECK /Cnt_6 /Timeout SETF ROM_In ; Pulse ROM_In again SETF /ROM_In ; Absolutely nothing should change CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; All flip-flops should still be CHECK /Cnt_3 /Cnt_4 /Cnt_5 ; reset. CHECK /Cnt_6 /Timeout ; ; Now test the Long Timeout Function. ; SETF /Ext_Bit ; Set the Ext_Bit to its "count" mode. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that the /Cnt_% pins = count of 1. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that the /Cnt_% pins = count of 2. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that the /Cnt_% pins = count of 3. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 4. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 5. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 6. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 7th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 7. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 8th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 8. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 9th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 9. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 10th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 10. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 11th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 11. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 12th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 12. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 13th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 13. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 14th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 14. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 15th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 15. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 16th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 16. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 17th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 17. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 18th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 18. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 19th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 19. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 20th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 20. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 21th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 21. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 22th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 22. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 23th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 23. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 24th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 24. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 25th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 25. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 26th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 26. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 27th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 27. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 28th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 28. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 29th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 29. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 30th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 30. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 31th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 31. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 32th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 32. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 33th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 33. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 34th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 34. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 35th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 35. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 36th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 36. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 37th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 37. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 38th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 38. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 39th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 39. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 40th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 40. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 41th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 41. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 42th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 42. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 43th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 43. CHECK /Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 44th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 44. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 45th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 45. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 46th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 46. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 47th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 47. CHECK Cnt_2 Cnt_3 CHECK /Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 48th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 48. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 49th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 49. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 50th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 50. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 51th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 51. CHECK /Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 52th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 52. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 53th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 53. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 54th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 54. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 55th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 55. CHECK Cnt_2 /Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 56th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 56. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 57th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 57. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 58th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 58. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 59th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 59. CHECK /Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 60th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 60. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 61th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 61. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 62th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 62. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 63th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 63. CHECK Cnt_2 Cnt_3 CHECK Cnt_4 Cnt_5 /Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 64th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 64. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 65th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 65. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 66th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 66. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 67th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 67. CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 68th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 68. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 69th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 ; Verify that /Cnt_% pins = count of 69. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 70th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 70. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 71th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin NOW GOES to GND. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins = count of 71. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 72th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at GND. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins HOLD at count 71. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 73th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at GND. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins HOLD at count 71. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 74th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at GND. CHECK Cnt_0 Cnt_1 ; Verify that /Cnt_% pins HOLD at count 71. CHECK Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 Cnt_6 SETF Ext_Bit ; Set the Ext_Bit to its "reset" mode SETF ROM_In ; and clock it in. This should reset SETF /ROM_In ; all flip-flops. CHECK /Timeout ; Verify that all flip-flops are reset. CHECK /Cnt_0 /Cnt_1 CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 SETF ROM_In ; Pulse the ROM_In and nothing SETF /ROM_In ; should happen. CHECK /Timeout ; Verify that all flip-flops are reset. CHECK /Cnt_0 /Cnt_1 CHECK /Cnt_2 /Cnt_3 CHECK /Cnt_4 /Cnt_5 /Cnt_6 TRACE_OFF