TITLE Level 1.5 Receive Term #i PAL PATTERN MTG L1.5 Receive Term #i PAL REVISION 1.06 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 29-MAY-1992 ; The detailed description of this device is at the end of this file. CHIP L15_recv PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD Sel_Comp Comp_Trm LD_Reg ROM_In /RD_Reg L15_Cycl Term_Don ;9 10 11 12 13 14 15 16 Term_Ans GND /Glob_OE /Done_Lat /Conf_NO /Ans_Lat CmpTrmLt SelCmpLt ;17 18 19 20 CmpTrmOu SelCmpOu /Term_D_A Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /Term_D_A) is inverted before ; being driven off-card. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. /SelCmpLt := /Sel_Comp ; This term is the CBUS Data In Bit /SelCmpLt.CLKF = LD_Reg ; #1, latched by the rising edge of /SelCmpLt.TRST = Vcc ; the Load Register (aka Write FA /SelCmpLt.SETF = GND ; #n). It is always output- /SelCmpLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; It is used to select either the ; "real" Level 1.5 Term Done and ; Answer or the CBUS latched data ; bit #2 as the input to the Done/ ; Answer logic. /CmpTrmLt := /Comp_Trm ; This term is the CBUS Data In Bit /CmpTrmLt.CLKF = LD_Reg ; #2, latched by the rising edge of /CmpTrmLt.TRST = Vcc ; the Load Register (aka Write FA /CmpTrmLt.SETF = GND ; #n). It is always output- /CmpTrmLt.RSTF = GND ; enabled, and fed-back to the ; matrix. ; This is the bit used as the input ; to the Done/Answer logic if the ; "CBUS" Term is selected. SelCmpOu := SelCmpLt ; This term is the CBUS Data Out Bit SelCmpOu.CLKF = GND ; #1. It is not latched. It is SelCmpOu.TRST = RD_Reg ; output-enabled while Read Register SelCmpOu.SETF = Vcc ; (aka /Read FA #n) is low. It SelCmpOu.RSTF = Vcc ; reflects the state of SelCmpLt. CmpTrmOu := CmpTrmLt ; This term is the CBUS Data Out Bit CmpTrmOu.CLKF = GND ; #2. It is not latched. It is CmpTrmOu.TRST = RD_Reg ; output-enabled while Read Register CmpTrmOu.SETF = Vcc ; (aka /Read FA #n) is low. It CmpTrmOu.RSTF = Vcc ; reflects the state of CmpTrmLt. Done_Lat := Term_Don Done_Lat.CLKF = ROM_In * /Done_Lat Done_Lat.TRST = Vcc ; This term is the Latched Done. It Done_Lat.SETF = GND ; is latched on the rising edge of Done_Lat.RSTF = /L15_Cycl ; ROM_In, only if the Latched Done ; is not asserted. It will be ; asserted if the Level 1.5 Term Done ; signal is asserted. ; ; Once asserted, it remains asserted ; (independent of the inputs) until ; the Level 1.5 Cycle is completed. ; ; When the Level 1.5 Cycle is not ; in progress, this term is held ; low. Ans_Lat := Term_Don * Term_Ans Ans_Lat.CLKF = ROM_In * /Ans_Lat * /Conf_NO Ans_Lat.TRST = Vcc ; This term is the Latched Answer. Ans_Lat.SETF = GND ; It is latched on the rising edge Ans_Lat.RSTF = /L15_Cycl ; of ROM_In, only if the Latched ; Answer is not asserted and the ; Confirmed NO signal is also not ; asserted. ; It is asserted if the Term Done ; and Term Answer are both high. ; Once asserted it remains ; asserted until the Level 1.5 ; Cycle completes. ; ; This term is held at reset while ; the Level 1.5 Cycle is not in ; progress. ; ; Although a race condition may appear ; to exist between /ROM_In and ; /Conf_No (that is, a "fast" ; /Conf_No may mask a "slow" ; /ROM_In), this situation may ; only occur when the Term has been ; confirmed Rejected. In this case, ; the Latched Answer should remain ; low, and will do so regardless of ; whether it receives a final clock ; pulse Conf_NO := Term_Don * /Term_Ans Conf_NO.CLKF = ROM_In * /Conf_NO Conf_NO.TRST = Vcc ; This term is the Confirmed NO. Conf_NO.SETF = GND ; It is latched on the rising edge Conf_NO.RSTF = /L15_Cycl ; of ROM_In if the Confirmed NO is ; not asserted. It will be asserted ; if the Term Done is high and the ; Term Answer is low. Once asserted ; it remains asserted until the ; Level 1.5 Cycle completes. ; ; This term is held at reset ; while the Level 1.5 Cycle is ; not in progress. Term_D_A := SelCmpLt * CmpTrmLt + /SelCmpLt * ROM_In * Done_Lat + /SelCmpLt * /ROM_In * /Done_Lat + /SelCmpLt * /ROM_In * Done_Lat * Ans_Lat Term_D_A.CLKF = GND ; This is the Term Done/Answer signal. Term_D_A.TRST = Vcc ; It ALWAYS reflects the state of the Term_D_A.SETF = Vcc ; Computer Term Latched if the "CBUS" Term_D_A.RSTF = Vcc ; Term has been selected. Otherwise, ; during the DONE 1/2 cycle, it ; reflects the state of the Latched ; Done (0 if not done, 1 if done). ; During the ANSWER 1/2 cycle, it ; will be high until the Done is ; received, and will reflect the ; state of the Latched Answer after ; the Done is received. While ; the L1.5 cycle is not in progress, ; it is low during the DONE 1/2 cycle, ; and high during the ANSWER 1/2 ; cycle (if the "CBUS" Done/Answer ; is NOT selected). ; Note that the Term Done/Answer ; signal may not be valid immediately ; following any transition of ROM_In, ; but will settle within a short time ; to its valid state. Any glitches ; in the output following transitions ; of ROM_In will not be latched. ; The Term Done/Answer signal is then ; mapped by the Digimem Matrix to ; Specific Trigger Done/Answer ; signals, which are sampled at a ; specific time. This sampling point ; is chosen to be well clear of the ; possible glitches in the output. ; ; Description of this Receive Level 1.5 Term PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket on ; the RECEIVING MTG card. Recall that a RECEIVING MTG is different ; from a normal timing signal MTG in that the RECEIVING MTG has a ; "Global External" input line in place of the normal timing signal MTG's ; "Data 6 In" line. The following table shows how to setup these ; connections for the maximum flexability from the 16RA8 PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Sel Computer Socket pin tied to device pin. ; 0: listen to Done_Ans ; 1: listen to Comp_Ans ; ; 3 Data 2 In Computer Term Socket pin tied to device pin. ; 1: simulate the L1.5 Term DONE and ; ANSWER=YES state ; 0: simulate the L1.5 Term NOT_DONE ; and ANSWER=NO state ; ; 4 Data 3 In Load Reg Input Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. ; ; 5 Data 4 In ROM BIT In Device pin tied to socket pin 12. ; Socket pin not used. ; ; 6 Data 5 In Read Reg Input Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; ; 7 Glob-Ext L1.5 Cycle Socket pin tied to device pin. ; 1: L1.5 Cycle in progress ; 0: L1.5 Cycle not in progress ; ; 8 Ext-Enb L1.5 Term Done Socket pin tied to device pin. ; value at sampling point: ; 1: L1.5 Term Done ; 0: L1.5 Term Not Done ; When Done is high at sampling point, ; the accompanying Answer is valid ; ; 9 Ext-Bit L1.5 Term Answer Socket pin tied to device pin. ; value at sampling point ; 1: L1.5 Term Confirmed Positive ; 0: L1.5 Term Confirmed Negative ; This signal must be accompanied ; by a DONE signal to be valid. ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit Latched Done Device pin not connected to socket ; pin. Socket pin connected to device ; pin 5. ; ; 13 Data 6 Out L1.5 Term Device pin not connected to socket pin ; Conf Negative ; ; 14 Data 5 Out Latched Answer Device pin not connected to socket pin ; ; 15 Data 4 Out Comp Trm Latch Device pin not connected to socket pin ; ; 16 Data 3 Out Sel Comp Latch Device pin not connected to socket pin ; ; 17 Data 2 Out Comp Trm Output Socket pin tied to device pin. ; ; 18 Data 1 Out Sel Comp Output Socket pin tied to device pin. ; ; 19 Channel Out Term Done/Answer Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; This PAL performs the Level 1.5 Veto for Specific Trigger #i logic. ; ; It has two CBUS-loadable single-bit registers, "Sel Computer Latch" ; and "Computer Term Latch," which are loaded on the rising edge of ; the "Load Register" line. These two registers are CBUS-readable, ; the pins "Sel Computer Output" and "Computer Term Output" contain ; the output of their respective registers while the "Read Register" ; line is low. ; ; Additionally, the Receive L1.5 Term processing logic is performed. ; The table below illustrates this logic: ; ; Term_Don Term_Ans ; at ROM_In at ROM_In ; rising rising ; L15_Cycl SelCmpLt CmpTrmLt edge edge ROM_In Term_D_A ; -------- -------- -------- --------- -------- ------ -------- ; X 1 0 X X X 0 ; X 1 1 X X X 1 ; 0 0 X X X 0 0 ; 0 0 X X X 1 1 ; 1 0 X 0 X 0 1 ; 1 0 X 0 X 1 1 ; 1 0 X 1 X 0 1 ; 1 0 X 1 0 1 0 ; 1 0 X 1 1 1 1 ; ; ; Note that the inputs are sampled (that is, the "Term" and "Done" ; signals, either computer-generated or the external inputs) at every ; "Term sampling point" (ROM_In) rising edge, until the Done is asserted ; at the Term sampling point. Once this state has been reached, the ; Latched Answer and Latched Done will remain stable until the end of ; the Level 1.5 Cycle, when they will be reset. They will be held reset ; while the Level 1.5 Cycle is not in progress. ; ; If the "real" Term has been selected, the Done/Answer line will be ; low during the DONE 1/2 cycle and high during the ANSWER 1/2 cycle ; while the Level 1.5 Cycle is not in progress, AND ALSO while the ; Level 1.5 Cycle is in progress but the Done has not been received. ; After the Done is received, the Done/Answer line will be high during ; the DONE 1/2 cycle, and will reflect the Latched Answer during the ; ANSWER 1/2 cycle. ; ; If the "CBUS" Term has been selected, the Level 1.5 Cycle and the ; half-cycles are both ignored. The Done/Answer line will always ; reflect the Latched Computer Term, regardless of the ROM or the Level ; 1.5 Cycle signals. SIMULATION ; Set up the trace TRACE_ON L15_Cycl ROM_In Term_Don Term_Ans Done_Lat Ans_Lat Conf_NO Term_D_A ; Disable preload, enable global OE (done in wiring on PCB) SETF /Pre_LD Glob_OE /RD_Reg /LD_Reg ; Set the inputs to the normal "quiescent" state SETF /L15_Cycl /ROM_In /Term_Don /Term_Ans /Sel_Comp /Comp_Trm ; Simulate CBUS cycle to program the PAL to listen to "real" signals SETF /Sel_Comp /Comp_Trm SETF LD_Reg SETF /LD_Reg ; TEST: NOT IN LEVEL 1.5 CYCLE ; Set ROM low, ANSWER 1/2 Cycle, default answer = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs, DONE 1/2 Cycle, default done = NO SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low, ANSWER 1/2 Cycle, default answer = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ANSWER, DONE high. Default answer. SETF Term_Don Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs, DONE 1/2 cycle. Default done ; because we are not in Level 1.5 Cycle SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low again, and set ANSWER, DONE low also SETF /ROM_In /Term_Don /Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; TEST: LEVEL 1.5 TERM CONFIRMED ACCEPTED ; ROM starts low, for ANSWER 1/2 Cycle, default answer = YES SETF /ROM_In /Term_Don /Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Start the Level 1.5 Cycle, still ANS 1/2 Cyc, def ans = YES SETF L15_Cycl CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs (which are low), done = NO SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Change inputs, nothing should happen until clock SETF Term_Don Term_Ans CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low, ANS 1/2 Cycle, default ANS = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ANSWER high, but don't set DONE. This should not register. SETF Term_Ans /Term_Don CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs, done = NO SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low, ANS 1/2 Cyc, default ANS = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ANSWER high, and DONE high. SETF Term_Don Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Now clock inputs. Done should go high SETF ROM_In CHECK Term_D_A Done_Lat Ans_Lat /Conf_NO ; Answer 1/2 cycle, answer = YES SETF /ROM_In CHECK Term_D_A Done_Lat Ans_Lat /Conf_NO ; Now change inputs. Should not change outputs! SETF /Term_Don /Term_Ans CHECK Term_D_A Done_Lat Ans_Lat /Conf_NO ; Now clock changed inputs. Still should not change outputs! SETF ROM_In CHECK Term_D_A Done_Lat Ans_Lat /Conf_NO ; Now drop ROM input SETF /ROM_In CHECK Term_D_A Done_Lat Ans_Lat /Conf_NO ; Now drop Level 1.5 Cycle. Everything should reset SETF /L15_Cycl CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; TEST: LEVEL 1.5 TERM CONFIRMED REJECTED ; ROM starts low, for ANSWER 1/2 Cycle, default answer = YES SETF /ROM_In /Term_Don /Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Start the Level 1.5 Cycle, still ANS 1/2 Cyc, def ans = YES SETF L15_Cycl CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs (which are low), done = NO SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Change inputs, nothing should happen until clock SETF Term_Don Term_Ans CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low, ANS 1/2 Cycle, default ANS = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ANSWER high, but don't set DONE. This should not register. SETF Term_Ans /Term_Don CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM high, clock inputs, done = NO SETF ROM_In CHECK /Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ROM low, ANS 1/2 Cyc, default ANS = YES SETF /ROM_In CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Set ANSWER low, and DONE high. SETF Term_Don /Term_Ans CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Now clock inputs. Done should go high SETF ROM_In CHECK Term_D_A Done_Lat /Ans_Lat Conf_NO ; Answer 1/2 cycle, answer = NO SETF /ROM_In CHECK /Term_D_A Done_Lat /Ans_Lat Conf_NO ; Now change inputs. Should not change outputs! SETF /Term_Don /Term_Ans CHECK /Term_D_A Done_Lat /Ans_Lat Conf_NO ; Now clock changed inputs. Still should not change outputs! SETF ROM_In CHECK Term_D_A Done_Lat /Ans_Lat Conf_NO ; Now drop ROM input SETF /ROM_In CHECK /Term_D_A Done_Lat /Ans_Lat Conf_NO ; Now drop Level 1.5 Cycle. Everything should reset SETF /L15_Cycl CHECK Term_D_A /Done_Lat /Ans_Lat /Conf_NO ; Turn off the trace TRACE_OFF