TITLE Start Digitize for Geographic Sector #1 (COMINT) PATTERN L1.5 Start Digitize Geographic Sector #1 (Start Datablock) REVISION 1.01 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 15-JUN-1992 ; The detailed description of this device is at the end of this file. CHIP StrtDBlk PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 LD_Reg Dat_In_1 Dat_In_2 Dat_In_3 Dat_In_4 Dat_In_5 NC1 Ext_Enb ;9 10 11 12 13 14 15 16 Ext_Bit GND /RD_Reg ROM_In NC2 Comp_Bit Comp_Ena Spr_Reg ;17 18 19 20 M_1 M_0 /Bitout Vcc ; Recall that, on the MTG, the signal connected to pin 19 ; (here called /Bitout) is inverted before being driven off-card. EQUATIONS /M_0 := /Dat_In_1 ; This term is the CBUS Data In Bit ; #1, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the low-order ; Mode Bit. See table below. /M_1 := /Dat_In_2 ; This term is the CBUS Data In Bit ; #2, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is high-order Mode ; Bit. See table below. /Spr_Reg := /Bitout ; This term is the READ-ONLY CBUS ; Data Bit #3. It reflects the ; state of the Bitout at the time ; of the last CBUS Write to this ; PAL. It is output-enabled while ; /Read FA #n is low. /Comp_Ena := /Dat_In_4 ; This term is the CBUS Data In Bit ; #4, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer ; Enable. /Comp_Bit := /Dat_In_5 ; This term is the CBUS Data In Bit ; #5, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer Bit. ROM_In.TRST = GND ; This term is an input. NC2.TRST = GND ; This term is not used. Bitout = /M_1 * /M_0 * ROM_In * Ext_Bit + /M_1 * /M_0 * ROM_In * Comp_Ena + /M_1 * M_0 * Comp_Bit * Comp_Ena + /M_1 * M_0 * Comp_Bit * Ext_Bit + M_1 * /M_0 * ROM_In * Ext_Bit * Ext_Enb + M_1 * M_0 * Ext_Bit * Ext_Enb + M_1 * M_0 * Ext_Enb * Comp_Ena Bitout.TRST = Vcc ; This term is the Bitout. It has ; 4 modes: Display Computer Bit ; ,enabled by Computer Enable OR ; the External Bit (Start Datablock ; input); display the ROM enabled ; by the Computer Enable or the ; External Bit; display the ROM ; gated by the AND of the External ; Bit and the External Enable ; (Level 1.5 Start Datablock Mask); ; and display the External ; Enable gated by the External Bit ; or the Computer Enable. ; ; Description of this Start Digitize for Geo. Sect #1 PAL ; ; This circuit uses a 16V8 type of PAL. There are NO special ; connections required to plug this 16V8 PAL into a Bit PAL socket on ; the Level 1.5 Control MTG. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg CLOCK Socket pin tied to device pin. ; pos edge ; ; 2 Data 1 In M_0 Socket pin tied to device pin. ; ; 3 Data 2 In M_1 Socket pin tied to device pin. ; ; 4 Data 3 In Spare Register Socket pin tied to device pin. ; ; 5 Data 4 In Computer Enable Socket pin tied to device pin. ; ; 6 Data 5 In Computer Bit Socket pin tied to device pin. ; ; 7 Data 6 In Not used / Socket pin tied to device pin. ; Global External ; ; 8 Ext-Enb External Input Socket pin tied to device pin. ; #1 ; ; 9 Ext-Bit External Input Socket pin tied to device pin. ; #2 ; ; 10 GND Device GND Socket pin tied to device pin. ; ; 11 Read Reg. Global Output Socket pin tied to device pin. ; Low Active Enable Low Active ; ; 12 ROM Bit ROM Bit In Socket pin tied to device pin. ; ; 13 Data 6 Out Not Used. Socket pin tied to device pin. ; ; ; 14 Data 5 Out Computer Bit Out Socket pin tied to device pin. ; ; 15 Data 4 Out Computer Enable Socket pin tied to device pin. ; Output ; ; 16 Data 3 Out Spare Register Socket pin tied to device pin. ; Read-only Out ; ; 17 Data 2 Out M_1 Output Socket pin tied to device pin. ; ; 18 Data 1 Out M_0 Output Socket pin tied to device pin. ; ; 19 Channel Out Bitout Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; ; ; Logic for this Level 1.5 SD to Geo Sect 1 PAL ; ; This PAL is intended for use in the SD Control MTG ; ; The modes of this PAL are the following: ; ; M_1 M_0 Description ; --- --- ----------- ; 0 0 Level 1.0 Processing Mode (Display the ROM, gated by either ; the External Bit [Start Datablock Input] OR the Computer ; Enable) ; 0 1 Display the Computer Bit, gated by the Computer Enable or ; the External Bit (Start Datablock Input) ; 1 0 Level 1.5 Processing Mode (Display the ROM, gated by the AND ; of the External Bit [Start Datablock Input] and the External ; Enable [Level 1.5 Start Datablock Mask]). ; 1 1 Display the ROM, gated by Ext_Enb + Comp_Ena