TITLE Level 1.5 Start Digitize for Geo Sect #i PAL PATTERN MTG L1.5 Start Digitize REVISION 1.03 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 16-MAY-1992 ; The detailed description of this device is at the end of this file. CHIP StrtDgtz PAL16V8 ;PINS ;1 2 3 4 5 6 7 8 LD_Reg Dat_In_1 Dat_In_2 Dat_In_3 Dat_In_4 Dat_In_5 L15_SDC NC1 ;9 10 11 12 13 14 15 16 St_Digit GND /RD_Reg ROM_In /ShapedSD Comp_Bit Comp_Ena Spr_Reg ;17 18 19 20 M_1 M_0 /StrtDgtz Vcc ; Recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /StrtDgtz) is inverted before ; being driven off-card. EQUATIONS /M_0 := /Dat_In_1 ; This term is the CBUS Data In Bit ; #1, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the low-order mode ; select bit. See table below. /M_1 := /Dat_In_2 ; This term is the CBUS Data In Bit ; #2, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the high-order mode ; select bit. See table below. /Spr_Reg := /StrtDgtz ; This term is the READ-ONLY CBUS ; Data Bit Output #3. It reflects ; the state of the Start Digitize ; output, latched by the rising edge ; of Load Register (aka Write FA #n). ; It is output-enabled while Read ; Register (aka /Read FA #n) is low. /Comp_Ena := /Dat_In_4 ; This term is the CBUS Data In Bit ; #4, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer ; Enable bit. /Comp_Bit := /Dat_In_5 ; This term is the CBUS Data In Bit ; #5, latched by the rising edge of ; Load Register (aka Write FA #n). ; It is always fed-back to the ; matrix, and output-enabled while ; Read Register (aka /Read FA #n) ; is low. It is the Computer Bit. ROM_In.TRST = GND ; This term is an input. ShapedSD = St_Digit * ROM_In + M_1 * /M_0 * L15_SDC * ShapedSD ShapedSD.TRST = Vcc ; This term is the Shaped Start ; Digitize. It goes high when ; the Start Digitize input and ; ROM_In are high. If we are not ; in the Level-1.5 Mode (see table ; below), it goes low again when ; either ROM_In or the Start Digitize ; input become low. ROM_In will always ; fall before the Start Digitize input ; If we are in the Level-1.5 Mode, ; it will be latched high once the ; Level 1.5 Start Digitize Control ; signal goes high. When the L1.5 ; SDC signal goes low, it will ; again follow ROM_In * Start Digitize ; input. That is, it will go low if ; either ROM_In or the Start Digitize ; input are low at that time. The ; L1.5 SDC signal will only go low ; when ROM_In is high. StrtDgtz = /M_0 * ShapedSD + M_0 * M_1 * St_Digit * L15_SDC + M_0 * M_1 * Comp_Ena * L15_SDC + M_0 * /M_1 * St_Digit * Comp_Bit + M_0 * /M_1 * Comp_Ena * Comp_Bit StrtDgtz.TRST = Vcc ; This term is the Start Digitize. If ; in Level-1 or Level-1.5 Mode, it ; is high when Start Digitize and ; ROM_In are high. In Level 1.5 Mode, ; is held high while the Level 1.5 ; Trigger Framework is processing, ; and will be dropped before the Beam ; Crossing if the Level 1.5 Trigger ; Framework has rejected all Specific ; Triggers which digitize this ; Geographic Section, or dropped ; after the Beam Crossing if Level 1.5 ; has accepted at least one Specific ; Trigger which digitizes this ; Geographic Section. ; Additionally, if in Computer Mode, ; it will be high if the Computer ; Bit is high and either Start ; Digitize ; or Computer Enable are high. And if ; in Display Level 1.5 Hold Transfer ; Control Signal Mode, it is high if ; the Level 1.5 Hold Transfer Control ; signal is high and either Start ; Digitize or Computer Enable are high ; ; Description of this Start Digitize L1.5 Specific Trigger PAL ; ; This circuit uses a 16V8 type of PAL. There are some special ; connections required to plug this 16V8 PAL into a Bit PAL socket on ; the HOLD TRANSFER MTG card. Recall that a HOLD TRANSFER MTG is different ; from a normal timing signal MTG in that the HOLD TRANSFER MTG has a ; "Global External" input line in place of the normal timing signal MTG's ; "Data 6 In" line. The following table shows how to setup these ; connections for the maximum flexability from the 16V8 PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg CLOCK Socket pin tied to device pin. ; pos edge ; ; 2 Data 1 In Mode Bit 0 Socket pin tied to device pin. ; ; 3 Data 2 In Mode Bit 1 Socket pin tied to device pin. ; ; 4 Data 3 In Spare Register Socket pin tied to device pin. ; ; 5 Data 4 In Computer Enable Socket pin tied to device pin. ; ; 6 Data 5 In Computer Bit Socket pin tied to device pin. ; ; 7 Glob-Ext L1.5 Start Socket pin tied to device pin. ; Digitize Control ; ; 8 Ext-Enb Not used Socket pin tied to device pin. ; ; 9 Ext-Bit Start Digitize Socket pin tied to device pin. ; ; 10 GND Device GND Socket pin tied to device pin. ; ; 11 Read Reg. Global Output Socket pin tied to device pin. ; Low Active Enable Low Active ; ; 12 ROM Bit ROM Bit In Socket pin tied to device pin. ; ; 13 Data 6 Out Shaped Start Device pin not connected to socket pin ; Digitize ; ; 14 Data 5 Out Computer Bit Out Socket pin tied to device pin. ; ; 15 Data 4 Out Computer Ena Out Socket pin tied to device pin. ; ; 16 Data 3 Out Spare Register Socket pin tied to device pin. ; Output ; ; 17 Data 2 Out Mode Bit 1 Out Socket pin tied to device pin. ; ; 18 Data 1 Out Mode Bit 0 Out Socket pin tied to device pin. ; ; 19 Channel Out Start Digitize Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; ; ; ; This PAL performs the Start Digitize for Geo Sect #i logic. ; ; It has 4 CBUS-loadable and CBUS-readable registers: ; Mode Bit 0 ; Mode Bit 1 ; Computer Bit ; Computer Enable ; ; It also has one CBUS READ-ONLY register: ; Spare Register Output (reflects state of Start Digitize output) ; ; It can be in one of 4 Modes, based on the Mode Bit 0 and 1: ; ; M_1 M_0 Mode ; ----- ----- ------ ; 0 0 Level-1 style Start Digitize processing ; 0 1 Display Computer Bit, enabled by either ST_Digit ; or Computer Enable ; 1 0 Level-1.5 style Start Digitize processing ; 1 1 Display Level 1.5 Start Digitize Control signal, ; enabled by either ST_Digit or Computer Enable ; ; The processing for Display Computer Bit Mode or Display Level 1.5 Hold ; Transfer Control Signal Mode is self-explanatory. ; ; The processing for the Level-1 Style Start Digitize Mode is identical to ; the ROM-Gated behavior of an MTG BITPAL4. That is, the PROM pattern is ; displayed while the Start Digitize Signal is high. ; ; The processing for the Level 1.5 Style Start Digitize Mode is as follows: ; Hold Transfer goes high at the beginning of the PROM pattern if the ; Start Digitize is high at that time. The Start Digitize will remain high ; while the Level 1.5 Trigger Framework is processing the event. If at ; least one Specific Trigger which digitizes this Geographic Section is ; accepted by Level 1.5, the start Digitize will go low at the end of the ; PROM pattern. If all Specific Triggers digitizing the Geographic Section ; are rejected by Level 1.5, the Start Digitize will fall earlier than ; the beam crossing, but at a precise, controlled point in time. SIMULATION ; Set up the trace: TRACE_ON St_Digit ROM_In M_1 M_0 L15_SDC ShapedSD StrtDgtz ; Initialize all important pins SETF /St_Digit /ROM_In /L15_SDC ; Do "CBUS Cycles" to set Level-1 mode SETF /Dat_In_1 /Dat_In_2 /Dat_In_4 /Dat_In_5 CLOCKF LD_Reg ; TEST: NORMAL LEVEL 1 MODE ; Hit Start Digitize SETF St_Digit CHECK /StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK /StrtDgtz ; Now drop Start Digitize SETF /St_Digit CHECK /StrtDgtz ; TEST: LEVEL 1 MODE, BUT LEVEL 1.5 IS TALKING TOO ; Hit Start Digitize SETF St_Digit CHECK /StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now hit Level 1.5 Start Digitize Control SETF L15_SDC CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK /StrtDgtz ; Now drop Start Digitize and Level 1.5 SDC SETF /St_Digit /L15_SDC CHECK /StrtDgtz ; TEST: LEVEL 1.5 MODE, NO LEVEL 1.5 SIGNALS ; Initialize all important pins SETF /St_Digit /ROM_In /L15_SDC ; Do "CBUS Cycles" to set Level-1 mode SETF /Dat_In_1 Dat_In_2 /Dat_In_4 /Dat_In_5 CLOCKF LD_Reg ; Hit Start Digitize SETF St_Digit CHECK /StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK /StrtDgtz ; Now drop Start Digitize SETF /St_Digit CHECK /StrtDgtz ; TEST: LEVEL 1.5 MODE, LEVEL 1.5 ACCEPTS >= 1 ST DIGITIZING THIS G.S. ; Hit Start Digitize SETF St_Digit CHECK /StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now hit Level 1.5 Start Digitize Control SETF L15_SDC CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop Level 1.5 Start Digitize Control SETF /L15_SDC CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK /StrtDgtz ; Now drop Start Digitize SETF /St_Digit CHECK /StrtDgtz ; TEST: LEVEL 1.5 MODE, LEVEL 1.5 REJECTS ALL ST DIGITIZING THIS G.S. ; Hit Start Digitize SETF St_Digit CHECK /StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now hit Level 1.5 Start Digitize Control SETF L15_SDC CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK StrtDgtz ; Now drop Start Digitize SETF /St_Digit CHECK StrtDgtz ; Now hit ROM_In SETF ROM_In CHECK StrtDgtz ; Now drop Level 1.5 Start Digitize Control SETF /L15_SDC CHECK /StrtDgtz ; Now drop ROM_In SETF /ROM_In CHECK /StrtDgtz TRACE_OFF