TITLE Level 1.5 Short/Long Timeout PATTERN MTG L1.5 Short/Long Timeout (L1.5 CTRL MTG Channel 29/30) REVISION 1.09 AUTHOR Level 1.5 Trigger (Steve Gross) COMPANY MSU HEP DATE 10-DEC-1992 ; The detailed description of this device is at the end of this file. CHIP TIMEOUT PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD D1_In D2_In LD_Reg ROM_In /RD_Reg D6_In Ext_Enb ;9 10 11 12 13 14 15 16 Ext_Bit GND /Glob_OE /Cnt_0 /Cnt_1 /Cnt_2 /Cnt_3 /Cnt_4 ;17 18 19 20 D1_Lat D1_Out /Timeout Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output pin low, and RESETting the latch ; drives the output pin high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /BITOUT, here called /Veto) is inverted before ; being driven off-card. EQUATIONS ;/Glob_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ;/Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for each term. /D1_Lat := /D1_In ; This term is the CBUS Data In Bit /D1_Lat.CLKF = LD_Reg ; #1, latched by the rising edge of /D1_Lat.TRST = Vcc ; the Load Register (aka Write FA /D1_Lat.SETF = GND ; #n). It is always output- /D1_Lat.RSTF = GND ; enabled, and fed-back to the ; matrix. ; Storing a 0 selects the short ; (8 Bx or 28 usec) timeout. ; Storing a 1 selects the long ; (32 Bx or 112 usec) timeout. ; This is the bit used as the input ; to the VETO decision if the "CBUS" ; Answer line is selected. D1_Out := D1_Lat ; This is the CBUS Data Out Bit D1_Out.CLKF = GND ; #1. It is output enabled while D1_Out.TRST = RD_Reg ; the Read Register (aka /Read FA D1_Out.SETF = Vcc ; #n) is low. It reflects the state D1_Out.RSTF = Vcc ; of the Timeout Select. Cnt_0 := /Cnt_0 Cnt_0.CLKF = ROM_In * /Ext_Bit * /Timeout Cnt_0.TRST = Vcc Cnt_0.SETF = GND Cnt_0.RSTF = ROM_In * Ext_Bit ; This term is the LSB of the ; ripple counter. The output is ; ROM_In divided by 2. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Cnt_1 := /Cnt_1 Cnt_1.CLKF = /Cnt_0 Cnt_1.TRST = Vcc Cnt_1.SETF = GND Cnt_1.RSTF = ROM_In * Ext_Bit ; This term is the next to LSB of ; the ripple counter. The output ; is the LSB divided by 2. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Cnt_2 := /Cnt_2 Cnt_2.CLKF = /Cnt_1 Cnt_2.TRST = Vcc Cnt_2.SETF = GND Cnt_2.RSTF = ROM_In * Ext_Bit ; This term is the nt nt LSB of ; the ripple counter. The output ; is the nt LSB divided by 2. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Cnt_3 := /Cnt_3 Cnt_3.CLKF = /Cnt_2 Cnt_3.TRST = Vcc Cnt_3.SETF = GND Cnt_3.RSTF = ROM_In * Ext_Bit ; This term is the next to MSB of ; the ripple counter. The output ; is the nt nt LSB divided by 2. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Cnt_4 := /Cnt_4 Cnt_4.CLKF = /Cnt_3 Cnt_4.TRST = Vcc Cnt_4.SETF = GND Cnt_4.RSTF = ROM_In * Ext_Bit ; This term is the MSB of ; the ripple counter. The output ; is the nt MSB divided by 2. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; toggle if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; AND while the Timeout is low. ; That is, the clock is masked ; if either the Timeout is asserted ; or the Ext_Bit (L1.5 Stretch BAR) ; is asserted. Timeout := /D1_Lat * Cnt_0 * Cnt_1 * Cnt_2 * /Cnt_3 * /Cnt_4 + D1_Lat * Cnt_0 * Cnt_1 * Cnt_2 * Cnt_3 * Cnt_4 + Timeout Timeout.CLKF = ROM_In * /Ext_Bit Timeout.TRST = Vcc Timeout.SETF = GND Timeout.RSTF = ROM_In * Ext_Bit ; This is the timeout term. It is ; has two modes. In Short Timeout ; mode, it is asserted on the ; rising edge of ROM_In ; after the counter has counted ; to 7 (i.e. the rising edge of ; ROM_In which causes the counter ; to increment to 8). In Long ; Timeout mode, it is asserted ; on the rising edge of ROM_In ; after the counter has counted ; to 31 (i.e. the rising edge of ; ROM_In which causes the ; counter to roll over to 0). ; In both modes, once the ; timeout is asserted, it ; remains asserted until reset. ; ; It is reset when Ext_Bit AND ROM_In ; are both high. Ext_Bit is the ; L1.5 Stretch BAR. ; ; The clock only forces this bit to ; change if Ext_Bit is low (i.e. ; only while L1.5 Stretch is high) ; ; Description of this Level 1.5 Timeout PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket on ; the Level 1.5 Control MTG card. The following table shows how to ; set up these connections for the maximum flexibility from the 16RA8 ; PAL. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Timeout Select Socket pin tied to device pin. ; 0: Short Timeout ; 1: Long Timeout ; ; 3 Data 2 In Not Used Socket pin tied to device pin. ; ; 4 Data 3 In Load Reg Input Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. ; ; 5 Data 4 In ROM BIT In Device pin tied to socket pin 12. ; Socket pin not used. ; ; 6 Data 5 In Read Reg Input Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; ; 7 Data 6 In Not Used Socket pin tied to device pin. ; ; 8 Ext-Enb Not Used Socket pin tied to device pin. ; ; 9 Ext-Bit L1.5 Stretch Socket pin tied to device pin. ; BAR Input ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit Count Bit 0 Device pin not connected to socket ; pin. Socket pin connected to device ; pin 5. ; ; 13 Data 6 Out Count Bit 1 Device pin not connected to socket pin ; ; 14 Data 5 Out Count Bit 2 Device pin not connected to socket pin ; ; 15 Data 4 Out Count Bit 3 Device pin not connected to socket pin ; ; 16 Data 3 Out Count Bit 4 Device pin not connected to socket pin ; ; 17 Data 2 Out Data Bit 1 Device pin not connected to socket pin ; Latched ; ; 18 Data 1 Out Data Bit 1 Out Socket pin tied to device pin. ; ; 19 Channel Out Timeout Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; ; Description of this Level 1.5 Timeout PAL ; ; ; The TIMEOUT PAL has a one bit wide data register that can be loaded and ; read from CBus data bit #1 (the LSB). When a zero is loaded into this ; register then the Short Timeout (28 us) will be used. When a one is ; loaded into this register then the Long Timeout (112 us) is used. ; ; Once per beam crossing, if Level 1.5 Stretch is low, the counter ; and output stage flip flops will be reset. ; ; To initiate operation, the Level 1.5 Stretch signal must first become ; asserted. This allows a PROM pulse to act as a clock for the counter ; section of this PAL. The counter section of this PAL is a 5-bit ; ripple counter. ; ; On subsequent beam crossing cycles the pulses from the PROM will be used ; to cause this 5 bit ripple counter to increment. When this counter ; reaches max count (00111 for Short Timeout, 11111 for Long Timeout), ; the output state flip flop will be prepared to change state. On the ; next clock pulse, the output state flip flop will change state, and the ; counter will increment by 1 (to 01000 for Short Timeout, rollover to ; 00000 for Long Timeout). The Timeout signal is fed back to the counter, ; masking all further clock signals to the counter until the device is ; reset. ; ; If the Level 1.5 Stretch signal is LOW during the time the PROM pulse ; is asserted, the counter will be reset to all zeros, no matter what ; value the counter had previously assumed. The output state flip flop ; will also be forced LOW if this combination of L1.5 Stretch and PROM ; occurs. ; ; ; ; Following is the SIMULATION data for the Skip 8 Beam Crossing PAL ; SIMULATION ; Enable tracing of several signals TRACE_ON D1_Lat D1_Out Ext_Bit ROM_In Cnt_0 Cnt_1 Cnt_2 Cnt_3 Cnt_4 Timeout ; Disable preload, enable global OE (done in wiring on PCB) ; Set no loading or readback of the CBus data register. SETF /Pre_LD Glob_OE /RD_Reg /LD_Reg SETF /ROM_In /Ext_Bit PRLDF Timeout Cnt_0 Cnt_1 Cnt_2 Cnt_3 Cnt_4 ; First test the one bit CBus data register for data 1. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK D1_Lat D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. SETF /D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of zero. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK /D1_Lat /D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. FOR J := 1 TO 12 DO ; Execute enough ROM clock pulses BEGIN ; so that the Skip Beam Crossings SETF ROM_In ; Cycle is certain to have counted SETF /ROM_In ; out in the Short Timeout mode END ; (for which it is currently ; programmed). CHECK Timeout ; Verify that the /Timeout pin is at 0V ; i.e. verify that it has counted out. SETF Ext_Bit ; Set Ext_Bit to its "reset" state but do SETF /Ext_Bit ; not ROM_In clock it. Then put it back. CHECK Timeout ; Verify that /Timeout pin is still at 0V. ; Begin testing Short Timeout mode. Reset the flip flops and verify that ; the counter counts to Timeout (7 + 1 pulses). ; The part is already programmed via CBUS for Short Timeout SETF Ext_Bit ; Set Ext_Bit to its "reset" state and SETF ROM_In ; ROM_In clock it. This resets all flip SETF /ROM_In ; flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout SETF ROM_In ; Pulse ROM_In again SETF /ROM_In ; Absolutely nothing should change CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; All flip-flops should still be CHECK /Cnt_3 /Cnt_4 /Timeout ; reset. SETF /Ext_Bit ; Set Ext Bit to its "count" state. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 1. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 2. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 3. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 4. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 5. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 6. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 7th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 7. CHECK /Cnt_3 /Cnt_4 ; The next pulse will set the Timeout. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 8th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is now at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 ; Subsequent clock pulses to the counter ; are masked until the device is reset. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 9th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 10th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 11th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF Ext_Bit ; Set the Ext_Bit to its "reset" mode SETF ROM_In ; and clock it in. This should reset SETF /ROM_In ; all flip-flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout ; Now test Short Timeout Mode, but interrupt the count before the max ; count is reached. Prove that the counter resets and can begin anew. SETF /Ext_Bit ; Set the Ext_Bit to its "count" mode. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 1. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 2. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 3. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 4. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 5. CHECK /Cnt_3 /Cnt_4 SETF Ext_Bit ; Set the Ext_Bit to its "reset" mode SETF ROM_In ; and clock it in. this should reset SETF /ROM_In ; all flip-flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout SETF /Ext_Bit ; Set the Ext_Bit to its "count" mode. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 1. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 2. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 3. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 4. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 5. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 6. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 7th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 7. CHECK /Cnt_3 /Cnt_4 ; The next pulse will set the Timeout. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 8th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is now at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 ; Subsequent clock pulses to the counter ; are masked until the device is reset. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 9th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 10th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 11th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF Ext_Bit ; Set the Ext_Bit to its "reset" mode SETF ROM_In ; and clock it in. This should reset SETF /ROM_In ; all flip-flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout ; Now test the Long Timeout Mode. Verify that the counter counts to max ; count (31 + 1 pulses) and that the Timeout is asserted at the appropriate ; time. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK D1_Lat D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. SETF /Ext_Bit ; Set the Ext_Bit to its "count" mode. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 1. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 2. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 3. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 4. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 5. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 6. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 7th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins = count of 7. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 8th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 8. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 9th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins = count of 9. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 10th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 10. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 11th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 11. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 12th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 12. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 13th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 13. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 14th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 14. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 15th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 15. CHECK Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 16th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 16. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 17th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 17. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 18th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 18. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 19th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 19. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 20th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 20. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 21st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 21. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 22nd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 22. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 23rd ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 23. CHECK /Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 24th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 24. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 25th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 25. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 26th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 26. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 27th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 27. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 28th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 28. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 29th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 /Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 29. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 30th ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK /Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 30. CHECK Cnt_3 Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 31st ROM clock of the cycle. CHECK /Timeout ; Verify that /Timeout pin is still at +5V. CHECK Cnt_0 Cnt_1 Cnt_2 ; Verify that the /Cnt_% pins =count of 31. CHECK Cnt_3 Cnt_4 ; The next pulse will set the Timeout. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 32nd ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is now at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 0. CHECK /Cnt_3 /Cnt_4 ; Note that the counter has rolled over. ; Subsequent clocks to the counter are ; masked until the device is reset. SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 33rd ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 0. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 34th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 0. CHECK /Cnt_3 /Cnt_4 SETF ROM_In ; ROM_In clock the Timeout PAL. SETF /ROM_In ; This is the 35th ROM clock of the cycle. CHECK Timeout ; Verify that /Timeout pin is still at 0V. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that the /Cnt_% pins =count of 0. CHECK /Cnt_3 /Cnt_4 SETF Ext_Bit ; Set the Ext_Bit to its "reset" mode SETF ROM_In ; and clock it in. This should reset SETF /ROM_In ; all flip-flops. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout SETF ROM_In ; Pulse the ROM_In. Nothing should SETF /ROM_In ; happen. CHECK /Cnt_0 /Cnt_1 /Cnt_2 ; Verify that all flip-flops are reset. CHECK /Cnt_3 /Cnt_4 /Timeout TRACE_OFF