18-DEC-1992 =========== The Timeout PAL test vectors have a problem regarding vectors 15 through 32. These vectors were generated from the AMD PALASM2 software from the SIMULATION information provided in TIMEOUT.PDS. Vectors 15 through 32 correspond to an unimportant part of the initialization routine for this PAL (walking the PAL to a known state). These vectors are NOT CONSISTENT with correct operation of this part. The vectors indicate that the counter should go from a count of 00000 to a count of 11111 with a single clock pulse. The counter should rather go from a count of 00000 to a count of 00001 with a single clock pulse. The simulation runs 100% correctly on the PC (that is, no errors are discovered) because no CHECK statements are defined for vectors 15 through 32 (thus PALASM computes the expected output for each pin using presumably the same code used to simulate the part. This points out the necessity of using CHECK statements to verify operation of the PAL). All of the "important" operations of the PAL are checked with CHECK statements, and no difficulties are found there. If the TIMEOUT PAL is tested using these vectors, the TIMEOUT PAL will fail on vectors 15 through 32. The failure has been examined and found to be consistent with CORRECT OPERATION of this PAL. The results from the Data I/O are included below (recall pin 12 = /Cnt_0, pin 13 = /Cnt_1, etc.): Vector pin pins pin Number 12 13..16 19 Data From ------ ----- ------ ----- --------- 15 L LLLL H Simulator (incorrect) 15 L HHHH H Data I/O (correct) 16 All the same as 15. 17 H HHHH H Simulator 17 H LHHH H Data I/O 18 All the same as 17. 19 L HHHH H Simulator 19 L LHHH H Data I/O 20 All the same as 19. 21 H LHHH H Simulator 21 H HLHH H Data I/O 22 All the same as 21. 23 L LHHH H Simulator 23 L HLHH H Data I/O 24 All the same as 23. 25 H HLHH H Simulator 25 H LLHH H Data I/O 26 All the same as 25. 27 L HLHH H Simulator 27 L LLHH H Data I/O 28 All the same as 27. 29 H LLHH H Simulator 29 H HHLH L Data I/O 30 All the same as 29. 31 L LLHH H Simulator 31 H HHLH L Data I/O 32 All the same as 31. Finally, below is a set of what I believe to be 100% GOOD test vectors. That is, if the chip were tested with these vectors no failures would be experienced. V0001 1XX0X1XXXN0XXXXXXZXN* V0002 1XX001XX0N0XXXXXXZXN* V0003 0XX001XX0N111111XX1N* V0004 1XX001XX0N0HHHHHXZHN* V0005 11X001XX0N0HHHHHXZHN* V0006 11X101XX0N0HHHHHHZHN* V0007 11X001XX0N0HHHHHHZHN* V0008 11X000XX0N0HHHHHHHHN* V0009 11X001XX0N0HHHHHHZHN* V0010 10X001XX0N0HHHHHHZHN* V0011 10X101XX0N0HHHHHLZHN* V0012 10X001XX0N0HHHHHLZHN* V0013 10X000XX0N0HHHHHLLHN* V0014 10X001XX0N0HHHHHLZHN* V0015 10X011XX0N0LHHHHLZHN* V0016 10X001XX0N0LHHHHLZHN* V0017 10X011XX0N0HLHHHLZHN* V0018 10X001XX0N0HLHHHLZHN* V0019 10X011XX0N0LLHHHLZHN* V0020 10X001XX0N0LLHHHLZHN* V0021 10X011XX0N0HHLHHLZHN* V0022 10X001XX0N0HHLHHLZHN* V0023 10X011XX0N0LHLHHLZHN* V0024 10X001XX0N0LHLHHLZHN* V0025 10X011XX0N0HLLHHLZHN* V0026 10X001XX0N0HLLHHLZHN* V0027 10X011XX0N0LLLHHLZHN* V0028 10X001XX0N0LLLHHLZHN* V0029 10X011XX0N0HHHLHLZLN* V0030 10X001XX0N0HHHLHLZLN* V0031 10X011XX0N0HHHLHLZLN* V0032 10X001XX0N0HHHLHLZLN* V0033 10X011XX0N0HHHLHLZLN* V0034 10X001XX0N0HHHLHLZLN* V0035 10X011XX0N0HHHLHLZLN* V0036 10X001XX0N0HHHLHLZLN* V0037 10X011XX0N0HHHLHLZLN* V0038 10X001XX0N0HHHLHLZLN* V0039 10X001XX1N0HHHLHLZLN* V0040 10X001XX0N0HHHLHLZLN* V0041 10X001XX1N0HHHLHLZLN* V0042 10X011XX1N0HHHHHLZHN* V0043 10X001XX1N0HHHHHLZHN* V0044 10X011XX1N0HHHHHLZHN* V0045 10X001XX1N0HHHHHLZHN* V0046 10X001XX0N0HHHHHLZHN* V0047 10X011XX0N0LHHHHLZHN* V0048 10X001XX0N0LHHHHLZHN* V0049 10X011XX0N0HLHHHLZHN* V0050 10X001XX0N0HLHHHLZHN* V0051 10X011XX0N0LLHHHLZHN* V0052 10X001XX0N0LLHHHLZHN* V0053 10X011XX0N0HHLHHLZHN* V0054 10X001XX0N0HHLHHLZHN* V0055 10X011XX0N0LHLHHLZHN* V0056 10X001XX0N0LHLHHLZHN* V0057 10X011XX0N0HLLHHLZHN* V0058 10X001XX0N0HLLHHLZHN* V0059 10X011XX0N0LLLHHLZHN* V0060 10X001XX0N0LLLHHLZHN* V0061 10X011XX0N0HHHLHLZLN* V0062 10X001XX0N0HHHLHLZLN* V0063 10X011XX0N0HHHLHLZLN* V0064 10X001XX0N0HHHLHLZLN* V0065 10X011XX0N0HHHLHLZLN* V0066 10X001XX0N0HHHLHLZLN* V0067 10X011XX0N0HHHLHLZLN* V0068 10X001XX0N0HHHLHLZLN* V0069 10X001XX1N0HHHLHLZLN* V0070 10X011XX1N0HHHHHLZHN* V0071 10X001XX1N0HHHHHLZHN* V0072 10X001XX0N0HHHHHLZHN* V0073 10X011XX0N0LHHHHLZHN* V0074 10X001XX0N0LHHHHLZHN* V0075 10X011XX0N0HLHHHLZHN* V0076 10X001XX0N0HLHHHLZHN* V0077 10X011XX0N0LLHHHLZHN* V0078 10X001XX0N0LLHHHLZHN* V0079 10X011XX0N0HHLHHLZHN* V0080 10X001XX0N0HHLHHLZHN* V0081 10X011XX0N0LHLHHLZHN* V0082 10X001XX0N0LHLHHLZHN* V0083 10X001XX1N0LHLHHLZHN* V0084 10X011XX1N0HHHHHLZHN* V0085 10X001XX1N0HHHHHLZHN* V0086 10X001XX0N0HHHHHLZHN* V0087 10X011XX0N0LHHHHLZHN* V0088 10X001XX0N0LHHHHLZHN* V0089 10X011XX0N0HLHHHLZHN* V0090 10X001XX0N0HLHHHLZHN* V0091 10X011XX0N0LLHHHLZHN* V0092 10X001XX0N0LLHHHLZHN* V0093 10X011XX0N0HHLHHLZHN* V0094 10X001XX0N0HHLHHLZHN* V0095 10X011XX0N0LHLHHLZHN* V0096 10X001XX0N0LHLHHLZHN* V0097 10X011XX0N0HLLHHLZHN* V0098 10X001XX0N0HLLHHLZHN* V0099 10X011XX0N0LLLHHLZHN* V0100 10X001XX0N0LLLHHLZHN* V0101 10X011XX0N0HHHLHLZLN* V0102 10X001XX0N0HHHLHLZLN* V0103 10X011XX0N0HHHLHLZLN* V0104 10X001XX0N0HHHLHLZLN* V0105 10X011XX0N0HHHLHLZLN* V0106 10X001XX0N0HHHLHLZLN* V0107 10X011XX0N0HHHLHLZLN* V0108 10X001XX0N0HHHLHLZLN* V0109 10X001XX1N0HHHLHLZLN* V0110 10X011XX1N0HHHHHLZHN* V0111 10X001XX1N0HHHHHLZHN* V0112 11X001XX1N0HHHHHLZHN* V0113 11X101XX1N0HHHHHHZHN* V0114 11X001XX1N0HHHHHHZHN* V0115 11X000XX1N0HHHHHHHHN* V0116 11X001XX1N0HHHHHHZHN* V0117 11X001XX0N0HHHHHHZHN* V0118 11X011XX0N0LHHHHHZHN* V0119 11X001XX0N0LHHHHHZHN* V0120 11X011XX0N0HLHHHHZHN* V0121 11X001XX0N0HLHHHHZHN* V0122 11X011XX0N0LLHHHHZHN* V0123 11X001XX0N0LLHHHHZHN* V0124 11X011XX0N0HHLHHHZHN* V0125 11X001XX0N0HHLHHHZHN* V0126 11X011XX0N0LHLHHHZHN* V0127 11X001XX0N0LHLHHHZHN* V0128 11X011XX0N0HLLHHHZHN* V0129 11X001XX0N0HLLHHHZHN* V0130 11X011XX0N0LLLHHHZHN* V0131 11X001XX0N0LLLHHHZHN* V0132 11X011XX0N0HHHLHHZHN* V0133 11X001XX0N0HHHLHHZHN* V0134 11X011XX0N0LHHLHHZHN* V0135 11X001XX0N0LHHLHHZHN* V0136 11X011XX0N0HLHLHHZHN* V0137 11X001XX0N0HLHLHHZHN* V0138 11X011XX0N0LLHLHHZHN* V0139 11X001XX0N0LLHLHHZHN* V0140 11X011XX0N0HHLLHHZHN* V0141 11X001XX0N0HHLLHHZHN* V0142 11X011XX0N0LHLLHHZHN* V0143 11X001XX0N0LHLLHHZHN* V0144 11X011XX0N0HLLLHHZHN* V0145 11X001XX0N0HLLLHHZHN* V0146 11X011XX0N0LLLLHHZHN* V0147 11X001XX0N0LLLLHHZHN* V0148 11X011XX0N0HHHHLHZHN* V0149 11X001XX0N0HHHHLHZHN* V0150 11X011XX0N0LHHHLHZHN* V0151 11X001XX0N0LHHHLHZHN* V0152 11X011XX0N0HLHHLHZHN* V0153 11X001XX0N0HLHHLHZHN* V0154 11X011XX0N0LLHHLHZHN* V0155 11X001XX0N0LLHHLHZHN* V0156 11X011XX0N0HHLHLHZHN* V0157 11X001XX0N0HHLHLHZHN* V0158 11X011XX0N0LHLHLHZHN* V0159 11X001XX0N0LHLHLHZHN* V0160 11X011XX0N0HLLHLHZHN* V0161 11X001XX0N0HLLHLHZHN* V0162 11X011XX0N0LLLHLHZHN* V0163 11X001XX0N0LLLHLHZHN* V0164 11X011XX0N0HHHLLHZHN* V0165 11X001XX0N0HHHLLHZHN* V0166 11X011XX0N0LHHLLHZHN* V0167 11X001XX0N0LHHLLHZHN* V0168 11X011XX0N0HLHLLHZHN* V0169 11X001XX0N0HLHLLHZHN* V0170 11X011XX0N0LLHLLHZHN* V0171 11X001XX0N0LLHLLHZHN* V0172 11X011XX0N0HHLLLHZHN* V0173 11X001XX0N0HHLLLHZHN* V0174 11X011XX0N0LHLLLHZHN* V0175 11X001XX0N0LHLLLHZHN* V0176 11X011XX0N0HLLLLHZHN* V0177 11X001XX0N0HLLLLHZHN* V0178 11X011XX0N0LLLLLHZHN* V0179 11X001XX0N0LLLLLHZHN* V0180 11X011XX0N0HHHHHHZLN* V0181 11X001XX0N0HHHHHHZLN* V0182 11X011XX0N0HHHHHHZLN* V0183 11X001XX0N0HHHHHHZLN* V0184 11X011XX0N0HHHHHHZLN* V0185 11X001XX0N0HHHHHHZLN* V0186 11X011XX0N0HHHHHHZLN* V0187 11X001XX0N0HHHHHHZLN* V0188 11X001XX1N0HHHHHHZLN* V0189 11X011XX1N0HHHHHHZHN* V0190 11X001XX1N0HHHHHHZHN* V0191 11X011XX1N0HHHHHHZHN* V0192 11X001XX1N0HHHHHHZHN*