TITLE Main Timing MTG Skip 8 Beam Crossings PAL PATTERN MTG Skip 8 BX REVISION 1.00 AUTHOR Level 1 Trigger COMPANY MSU HEP DATE 31-MAY-1992 ; The detailed description of this device is at the end of this file. CHIP BX_8_Skip PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 9 10 /Pre_LD D1_In D2_In LD_Reg ROM_In /RD_Reg D6_In Ext_Enb Ext_Bit GND ;11 12 13 14 15 16 17 18 19 20 /Glb_OE No_Con /Cnt_1 /Cnt_2 /Cnt_3 /Str_Skp D1_Ltch D1_Out /TS_Out Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output low, and RESETting the latch ; drives the output high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /TS_OUT) is inverted before being driven off-card. EQUATIONS ; /Glb_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ; /Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for all terms. /D1_Ltch := /D1_In ; This term is the CBUS Data In Bit /D1_Ltch.CLKF = LD_Reg ; #1, latched by the rising edge of /D1_Ltch.TRST = Vcc ; the Load Register (aka Write FA /D1_Ltch.SETF = GND ; #n). It is always output enabled /D1_Ltch.RSTF = GND ; and fed-back to the matrix. ; Storing a 0 disables ExtBit from ; beginning the skip count. ; Storing a 1 enables ExtBit to ; begin the skip count. D1_Out := D1_Ltch ; This term is the CBUS Data Out Bit D1_Out.CLKF = GND ; #1. It is not latched. It is D1_Out.TRST = RD_Reg ; output-enabled while Read Register D1_Out.SETF = Vcc ; (aka /Read FA #n) is low. It D1_Out.RSTF = Vcc ; reflects the state of Data_1. Str_Skp := Ext_Enb ; This term builds the signal that + Ext_Bit * D1_Ltch ; "Resets" the Skip BX Counters and Str_Skp.CLKF = GND ; Clears the output Timing Signal. Str_Skp.TRST = Vcc ; It is not latched. It is Str_Skp.SETF = Vcc ; output-enabled all the time. Str_Skp.RSTF = Vcc Cnt_1 := /Cnt_1 * /TS_Out ; Count Register 1 bit value 1 Cnt_1.CLKF = ROM_In * /Str_Skp Cnt_1.TRST = Vcc Cnt_1.SETF = GND Cnt_1.RSTF = ROM_In * Str_Skp Cnt_2 := Cnt_1 * /Cnt_2 * /TS_Out ; Count Register 2 bit value 2 + /Cnt_1 * Cnt_2 * /TS_Out Cnt_2.CLKF = ROM_In * /Str_Skp Cnt_2.TRST = Vcc Cnt_2.SETF = GND Cnt_2.RSTF = ROM_In * Str_Skp Cnt_3 := Cnt_1 * Cnt_2 * /Cnt_3 * /TS_Out ; Count Register 3 + /Cnt_1 * /Cnt_2 * Cnt_3 * /TS_Out ; bit value 4 + Cnt_1 * /Cnt_2 * Cnt_3 * /TS_Out + /Cnt_1 * Cnt_2 * Cnt_3 * /TS_Out Cnt_3.CLKF = ROM_In * /Str_Skp Cnt_3.TRST = Vcc Cnt_3.SETF = GND Cnt_3.RSTF = ROM_In * Str_Skp TS_Out := Cnt_1 * Cnt_2 * Cnt_3 ; Timing Signal Output pin. + TS_Out ; Skip EIGHT Beam Crossings TS_Out.CLKF = ROM_In * /Str_Skp ; then Hold until the TS_Out.TRST = Vcc ; next ROM_In & Ext_Enb. TS_Out.SETF = GND TS_Out.RSTF = ROM_In * Str_Skp No_Con.TRST = GND ; This "product line" is an Input. No_Con.CLKF = GND ; ; Following is the SIMULATION data for the Skip 8 Beam Crossing PAL ; SIMULATION ; Enable tracing of several signals TRACE_ON D1_In D1_Ltch D1_Out Ext_Enb Ext_Bit ROM_In Cnt_1 Cnt_2 Cnt_3 TS_Out ; Disable preload, enable global OE (done in wiring on PCB) ; Set no loading or readback of the CBus data register. SETF /Pre_LD Glb_OE /RD_Reg /LD_Reg SETF /ROM_In /Ext_Enb /Ext_Bit PRLDF TS_Out Cnt_1 Cnt_2 Cnt_3 ; First test the one bit CBus data register for data 1. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK D1_Ltch D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. SETF /D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of zero. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK /D1_Ltch /D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. FOR J := 1 TO 12 DO ; Execute enough ROM clock pulses BEGIN ; so that the Skip Beam Crossings SETF ROM_In ; Cycle is certain to have counted SETF /ROM_In ; out. END CHECK TS_Out ; Verify that the /TS_Out pin is at 0V ; i.e. verify that it has counted out. SETF Ext_Enb ; Set Ext_Enb to its active state but do SETF /Ext_Enb ; not ROM_In clock it. Then put it back. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. SETF Ext_Bit ; Set Ext_Bit to its active state and SETF ROM_In ; ROM_In clock it. This trys to initiate SETF /ROM_In ; a Skip BX Cycle but the Ext_Bit input is SETF /Ext_Bit ; now disabled by the CBus data register. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. SETF Ext_Enb ; Set Ext_Enb to its active state and SETF ROM_In ; ROM_In clock it. This should initiate SETF /ROM_In ; a Skip BX Cycle. It will set the 3 bit SETF /Ext_Enb ; counter to zero and clear the /TS_Out. CHECK /TS_Out ; Verify that /TS_Out pin is now at +5V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins are all ; at +5V i.e. the count is zero. SETF Ext_Enb ; Set Ext_Enb to its active state and SETF ROM_In ; ROM_In clock it. The PAL should stay SETF /ROM_In ; at the beginning of a Skip Beam Crossing SETF /Ext_Enb ; Cycle count and /TS_Out should stay +5V. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins are all ; at +5V i.e. the count is zero. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 1. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 2. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 3. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 4. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 5. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 6. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 7. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is now at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. ; Now enable the ExtBit input to initiate ; a Skip Beam Crossings Cycle by loading a ; one into the CBus data register. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK D1_Ltch D1_Out ; Verify the value of Data 1. SETF /RD_Reg ; End the CBus read cycle. ; Trigger a Skip Beam Crossing Cycle by ; using the Ext_Bit input. SETF Ext_Bit ; Set Ext_Bit to its active state and SETF ROM_In ; ROM_In clock it. The PAL should stay SETF /ROM_In ; at the beginning of a Skip Beam Crossing SETF /Ext_Bit ; Cycle count and /TS_Out should stay +5V. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins are all ; at +5V i.e. the count is zero. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 1. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 2. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 3. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 4. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 5. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 6. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 7. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is now at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. ; In this test a Skip Beam Crossing Cycle ; will be initiated by Ext_Bit. It will ; bee allowed to count up to 5 and then ; another Skip Beam Crossing Cycle will be ; triggered this time by Ext_Enb. This ; second cycle will be allowed to count ; out. SETF Ext_Bit ; Set Ext_Bit to its active state and SETF ROM_In ; ROM_In clock it. The PAL should stay SETF /ROM_In ; at the beginning of a Skip Beam Crossing SETF /Ext_Bit ; Cycle count and /TS_Out should stay +5V. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins are all ; at +5V i.e. the count is zero. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 1. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 2. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 3. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 4. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 5. ; Now that it has counted to 5 trigger it ; a second time. Use the Ext_Enb input. SETF Ext_Enb ; Set Ext_Enb to its active state and SETF ROM_In ; ROM_In clock it. The PAL should stay SETF /ROM_In ; at the beginning of a Skip Beam Crossing SETF /Ext_Enb ; Cycle count and /TS_Out should stay +5V. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins are all ; at +5V i.e. the count is zero. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 1st ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 1. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 2nd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 2. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 3rd ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 3. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 4. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 5th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 /Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 5. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 6th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK /Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 6. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK /TS_Out ; Verify that /TS_Out pin is still at +5V. CHECK Cnt_1 Cnt_2 Cnt_3 ; Verify that the /Cnt_% pins = count of 7. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is now at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. SETF ROM_In ; ROM_In clock the BX 8 Skip PAL. SETF /ROM_In ; This is the 4th ROM clock of the cycle. CHECK TS_Out ; Verify that /TS_Out pin is still at 0V. CHECK /Cnt_1 /Cnt_2 /Cnt_3 ; Verify that the /Cnt_% pins = count of 0. TRACE_OFF ; ; Description of the Skip BX 8 PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket. ; The following table shows the connections used with this BXSKIP device. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Data 1 In Socket pin tied to device pin. ; ; 3 Data 2 In Data 2 In Socket pin tied to device pin. ; This input is not used in this design. ; ; 4 Data 3 In /Load_Reg Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. Socket pin 4 is open. ; ; 5 Data 4 In ROM_In Device pin 5 connected to socket ; pin 12. This is the PROM input. ; Socket pin 5 is open. ; ; 6 Data 5 In /Read_Reg Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; Socket pin 6 is open. ; ; 7 Data 6 In Data 6 In Socket pin tied to device pin. ; This input is not used in this design. ; ; 8 Ext-Enb Ext-Enb Socket pin tied to device pin. ; Receives the Latched Global Spec Trig ; Fired signal. ; ; 9 Ext-Bit Ext-Bit Socket pin tied to device pin. ; Receives the L1.5 Stretch signal. ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit No_Con Device pin not connected to socket pin. ; Socket pin 12 is connected to device ; pin 5. ; ; 13 Data 6 Out /Cnt_1 Device pin not connected to socket pin ; ; 14 Data 5 Out /Cnt_2 Device pin not connected to socket pin ; ; 15 Data 4 Out /Cnt_3 Device pin not connected to socket pin ; ; 16 Data 3 Out /Str_Skip Device pin not connected to socket pin ; ; 17 Data 2 Out D1_Ltch Device pin not connected to socket pin ; ; 18 Data 1 Out D1_Out Socket pin tied to device pin. ; ; 19 Channel Out /TS_Out Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; Detailed Description of the BX8SKIP PAL ; This PAL performs the Skip 8 Beam Crossing logic. ; ; The BX8SKIP PAL has a one bit wide data register that can be loaded and ; read from CBus data bit #1 (the LSB). When a zero is loaded into this ; register then only the ExtEnb input can initiate a Skip Beam Crossings ; Cycle. When a one is loaded into this register then either the ExtEnb ; or the ExtBit inputs can initiate a Skip Beam Crossings Cycle. ; ; In operation this PAL will receive a signal to initiate a Skip Beam ; Crossings Cycle on either ExtEnb input (typically the Latched Global ; Specific Trigger Fired signal) or else if it is enabled as explained ; above on the ExtBit input (typically the Level 1.5 Stretch signal). ; This "initiate"signal will be "validated" by a fairly narrow time marker ; pulse from the PROM pattern for this MTG channel. This combination will ; be used to reset to zero a 3 bit binary counter and to reset an output ; state flip-flop ; ; On subsiquent beam crossing cycles the pulses from the PROM will be used ; to cause this 3 bit counter to increment. When the 3 bit counter ; reaches max count (all ones) it will freeze at that count. With the ; continuing input of PROM pulses it will not roll back through zero and ; start up counting again. ; ; No matter what count the 3 bit counter has reached it will always reset ; to zero during a beam crossing cycle when the PAL receives an "initiate" ; Skip Beam Crossings Cycle on either it ExtEnb input or if enabled on its ; ExtBit input. ; ; The Output State Flip-Flop will change states when the counter has reached ; some predetermined count, typically 1, 2, or 8, (8 for this device). ;