TITLE Front-End Busy Control MTG Geographic Section #1 PAL PATTERN Front-End Busy for Geographic Section #1 REVISION 1.02 AUTHOR Level 1 Trigger (Steve Gross) COMPANY MSU HEP DATE 1-OCT-1992 ; The detailed description of this device is at the end of this file. CHIP FEBzGS01 PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 /Pre_LD M_0_In M_1_In LD_Reg ROM_In /RD_Reg NoConnct Ext_Enb ;9 10 11 12 13 14 15 16 FE_Busy GND /Glob_OE /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 M_1_Lat M_0_Lat ;17 18 19 20 M_1_Out M_0_Out /FEBzGS01 Vcc ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output low, and RESETting the latch ; drives the output high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /TS_OUT) is inverted before being driven off-card. EQUATIONS ; /Glb_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ; /Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for all terms. /M_0_Lat := /M_0_In ; This term is the CBUS Data In Bit /M_0_Lat.CLKF = LD_Reg ; #1, latched by the rising edge of /M_0_Lat.TRST = Vcc ; the Load Register (aka Write FA /M_0_Lat.SETF = GND ; #n). It is always output- /M_0_Lat.RSTF = GND ; enabled, and fed-back to the ; matrix. ; It is used as the Mode Bit #0. ; See table below. /M_1_Lat := /M_1_In ; This term is the CBUS Data In Bit /M_1_Lat.CLKF = LD_Reg ; #2, latched by the rising edge of /M_1_Lat.TRST = Vcc ; the Load Register (aka Write FA /M_1_Lat.SETF = GND ; #n). It is always output- /M_1_Lat.RSTF = GND ; enabled, and fed-back to the ; matrix. ; It is used as the Mode Bit #1. ; See table below. M_0_Out := M_0_Lat ; This term is the CBUS Data Out Bit M_0_Out.CLKF = GND ; #1. It is not latched. It is M_0_Out.TRST = RD_Reg ; output-enabled while Read Register M_0_Out.SETF = Vcc ; (aka /Read FA #n) is low. It M_0_Out.RSTF = Vcc ; reflects the state of M_0_Lat. M_1_Out := M_1_Lat ; This term is the CBUS Data Out Bit M_1_Out.CLKF = GND ; #2. It is not latched. It is M_1_Out.TRST = RD_Reg ; output-enabled while Read Register M_1_Out.SETF = Vcc ; (aka /Read FA #n) is low. It M_1_Out.RSTF = Vcc ; reflects the state of M_1_Lat. FE_Bz_D1 := FE_Busy ; This term is the First Delay FE_Bz_D1.CLKF = ROM_In ; of the Front-End Busy. It goes FE_Bz_D1.TRST = Vcc ; high with the rising edge of the FE_Bz_D1.SETF = GND ; PROM pulse after the Front-End FE_Bz_D1.RSTF = GND ; busy input is asserted. It ; remains high until the rising ; edge of the first PROM pulse ; after Front-End Busy is ; removed. FE_Bz_D2 := FE_Bz_D1 ; This term is the Second Delay FE_Bz_D2.CLKF = /ROM_In ; of the Front-End Busy. It goes FE_Bz_D2.TRST = Vcc ; high with the falling edge of the FE_Bz_D2.SETF = GND ; PROM pulse after the First Delayed FE_Bz_D2.RSTF = GND ; Front-End Busy signal is asserted. ; It remains high until the falling ; edge of the PROM pulse after the ; First Delay of the Front-End Busy ; is removed. This term eliminates ; a potential race condition ; between the PROM pulse and the ; First Delay of the Front-End ; busy. FE_Bz_D3 := FE_Bz_D2 + FE_Busy ; This term is the Third Delay FE_Bz_D3.CLKF = ROM_In ; of the Front-End Busy. It goes FE_Bz_D3.TRST = Vcc ; high with the rising edge of the FE_Bz_D3.SETF = GND ; PROM pulse after the Front-End FE_Bz_D3.RSTF = GND ; busy input is asserted. It ; remains high until the rising ; edge of the first PROM pulse ; after the Second Delay of the ; Front-End Busy is removed. ; That is, it remains active until ; the rising edge of the SECOND ; PROM pulse following the removal ; of the Front-End Busy input. FEBzGS01 := /M_1_Lat * /M_0_Lat * FE_Bz_D3 + /M_1_Lat * FE_Busy + M_1_Lat * M_0_Lat FEBzGS01.CLKF = GND ; This term is the Front-End Busy FEBzGS01.TRST = Vcc ; output. It operates in one of FEBzGS01.SETF = Vcc ; four modes. The modes are: FEBzGS01.RSTF = Vcc ; 0: Display the Front-End Busy ; input, ORed with the delayed ; Front-End Busy ; 1: Display the Front-End Busy ; input only ; 2: Force the output LOW ; 3: Force the output HIGH ; ; ; Description of the Front-End Busy for Geo. Sect. 1 PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket. ; The following table shows the connections used with this FEBZGS01 device. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Mode 0 In Socket pin tied to device pin. ; ; 3 Data 2 In Mode 1 In Socket pin tied to device pin. ; ; 4 Data 3 In /Load_Reg Device pin 4 connected to socket ; pin 1. Load CBUS registers on ; rising edge. Socket pin 4 is open. ; ; 5 Data 4 In ROM_In Device pin 5 connected to socket ; pin 12. This is the PROM input. ; Socket pin 5 is open. ; ; 6 Data 5 In /Read_Reg Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; Socket pin 6 is open. ; ; 7 Data 6 In No Connection Socket pin tied to device pin. ; This input is not used in this design. ; ; 8 Ext-Enb Ext-Enb Socket pin tied to device pin. ; This input is not used in this design. ; ; 9 Ext-Bit Front-End Socket pin tied to device pin. ; Busy Input Receives the Front-End Busy Input ; signal. ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit /Front-End Device pin not connected to socket pin. ; Busy Delay #1 Socket pin 12 is connected to device ; pin 5. ; ; 13 Data 6 Out /Front-End Device pin not connected to socket pin ; Busy Delay #2 ; ; 14 Data 5 Out /Front-End Device pin not connected to socket pin ; Busy Delay #3 ; ; 15 Data 4 Out M_1_Lat Device pin not connected to socket pin ; ; 16 Data 3 Out M_0_Lat Device pin not connected to socket pin ; ; 17 Data 2 Out M_1_Out Socket pin tied to device pin. ; ; 18 Data 1 Out M_0_Out Socket pin tied to device pin. ; ; 19 Channel Out /TS_Out Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; Detailed Description of the FEBzGS01 PAL. ; This PAL performs the processing for the Front-End ; Busy for Geographic Section #1 (Level 1 Framework/Cal Trig) ; ; The FEBzGS01 PAL has a two bit wide data register that can be loaded and ; read from CBus data bits #1 (the LSB) and #2. This register is used ; to store the Mode Bits for this PAL. The Modes of this pal are as ; follows: ; ; M_1 M_0 Description ; --- --- ----------- ; 0 0 Display the stretched Front-End Busy signal ; 0 1 Display the Front-End Busy input signal with no processing ; 1 0 Force the output LOW ; 1 1 Force the output HIGH ; ; The detailed description of each mode of operation follows: ; ; Mode 0: Display the stretched Front-End Busy signal ; ------ The output will be high whenever the Front-End Busy input ; signal is high. It will also remain high until the SECOND rising ; edge of the ROM input following the removal of the Front-End ; Busy input. The Front-End Busy input signal must remain active ; through one rising edge of the ROM input to initiate this ; "stretching" function. ; ; Mode 1: Display the Front-End Busy input signal with no processing. ; ------ This is equivalent to using a BIT2 PAL in the SELEXT * CMPENB ; mode. ; ; Mode 2: Force the output LOW ; ------ ; ; Mode 3: Force the output HIGH ; ------ SIMULATION ; Enable tracing of several signals TRACE_ON FE_Busy ROM_In FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Disable preload, enable global OE (done in wiring on PCB) SETF /Pre_LD Glob_OE /RD_Reg /LD_Reg ; Set the inputs to the normal "quiescent" state SETF /FE_Busy /ROM_In /M_0_In /M_1_In ; Simulate CBUS cycle to program the PAL to Mode 0 SETF /M_0_In /M_1_In SETF LD_Reg SETF /LD_Reg ; CASE 1: Front-End Busy input active for a few ticks, then it goes away ; ------ ; Pulse ROM_In twice to initialize flip flops. SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 ; Set the Front-End Busy input high. The output should go high. All ; of the delayed signals should remain low SETF FE_Busy CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 FEBzGS01 ; ROM_In rising edge should clock the Front-End Busy input into both ; Delay 1 and Delay 3. SETF ROM_In CHECK FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; ROM_In falling edge should clock the Front-End Busy input into Delay 2 SETF /ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Now allow a couple of ROM pulses through. Nothing should change SETF ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 SETF /ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 SETF ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 SETF /ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Now let the Front-End Busy go away. Nothing should change SETF /FE_Busy CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The rising edge of ROM_In should clear Delay 1 SETF ROM_In CHECK /FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The falling edge of ROM_In should clear Delay 2 SETF /ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The rising edge of ROM_In should clear delay 3 and cause the output ; to go low. SETF ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 ; Now drop ROM_In SETF /ROM_In ; CASE 2: Front-End Busy input on for 1 tick, then off for one tick, then ; ------ back on again. ; Front-end Busy input going high should force output high. SETF FE_Busy CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 FEBzGS01 ; Setting the ROM high sets Delay 1 and Delay 3 high SETF ROM_In CHECK FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Setting the ROM low sets Delay 2 also. SETF /ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Now let the Front-End Busy go away SETF /FE_Busy CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Setting the ROM high clears Delay 1 SETF ROM_In CHECK /FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Set the ROM low to clear Delay 2 SETF /ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Now let the Front-End Busy go active again SETF FE_Busy CHECK /FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; And hit the ROM again to set Delay 1 (Delay 3 still set) SETF ROM_In CHECK FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; And drop the ROM to set Delay 2 SETF /ROM_In CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; Now clear the Front-End Busy input SETF /FE_Busy CHECK FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The rising edge of ROM_In should clear Delay 1 SETF ROM_In CHECK /FE_Bz_D1 FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The falling edge of ROM_In should clear Delay 2 SETF /ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 FE_Bz_D3 FEBzGS01 ; The rising edge of ROM_In should clear delay 3 and cause the output ; to go low. SETF ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 ; Now drop ROM_In SETF /ROM_In ; CASE 3: Front-End Busy input active for less than 1 tick ; ------ ; Set the Front-End Busy input active. The output should go high, ; but the delayed Front-End Busies should remain low SETF FE_Busy CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 FEBzGS01 ; Now set the Front-End Busy input low. The output should go low. SETF /FE_Busy CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 ; Now set the ROM high. Nothing should change SETF ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 ; Ans set the ROM low. Nothing should change SETF /ROM_In CHECK /FE_Bz_D1 /FE_Bz_D2 /FE_Bz_D3 /FEBzGS01 TRACE_OFF