TITLE L15CT MTG Channel #5 Transmit Trigger Master Channel PAL PATTERN MTGBIT15 REVISION 1.99 AUTHOR Level 15 Calorimeter Trigger COMPANY MSU HEP DATE 31-MAY-1995 ; The detailed description of this device is at the end of this file. CHIP MTGBIT15 PAL16R4 ;PINS ;1 2 3 4 5 6 7 8 9 10 Ld_Reg D1_NC D2_In D3_In D4_In D5_In ROM_In ExtEnb ExtBit GND ;11 12 13 14 15 16 17 18 19 20 /Rd_Reg /TMLtch /FstHld CmpBit CmpEnb SelROM SelExt /SecHld /TS_Out Vcc ; pins 7, 12, 13, 18 need to be out of socket. Socket pin 12 conecets ; to device pin 7. EQUATIONS /SelExt := /D2_In ; This term is the CBUS Data In Bit /SelROM := /D3_In ; This term is the CBUS Data In Bit /CmpEnb := /D4_In ; This term is the CBUS Data In Bit /CmpBit := /D5_In ; This term is the CBUS Data In Bit TMLtch.TRST = VCC TMLtch = SelROM * ExtBit + SelROM * /SecHld * TMLtch FstHld.TRST = VCC FstHld = SelROM * /ROM_In * TS_Out + SelROM * TS_Out * FstHld SecHld.TRST = VCC SecHld = SelROM * ROM_In * FstHld + SelROM * FstHld * SecHld + SelROM * SecHld * TMLtch TS_Out.TRST = VCC TS_Out = SelROM * ROM_In * TMLtch * ExtEnb * /SecHld + SelROM * /SecHld * TS_Out + SelExt * CmpBit ; Recall that, on the MTG, the signal connected to pin 19 ; (usually called /TS_OUT) is inverted before being driven off-card. ; Modes of Operation of the MTGBIT15 PAL: ; ; 1. When SelROM is active then this PAL is used to make output pulses that ; last for one beam crossing period (i.e. from one pulse of the PROM ; pattern to the next) even if the incomming trigger (ExtBit) lasts ; longer. In the SelROM mode there are two possible ways to operate: ; with ExtEnb HI or with ExtEnb LOW. ; ; With ExtEnb HI then as soon as the incomming trigger (ExtBit) arrives ; and the PROM timing pulse occurs then the output pulse starts. ; ; With the ExtEnb LOW then when/if an incomming trigger (ExtBit) arrives ; all that happens is that the the MTGBIT15 remembers that it needs to ; make an output pulse. When ExtEnb returns HIGH and the PROM timing ; pulse occurs then the output pulse starts. ; ; As used in the L15CT MTG Ch #7, the MTGBIT15 PAL will operate in both ; of the modes indicated above. In both cases the input ExtBit trigger ; pulse will last for one BX. ; ; 2. When SelExtp is active then the output is controlled solely by the ; CmpBit register bit. The timing pulses from the PROM pattern are not ; used. ; ; Note that PAL device pins #7, #12, #13, #18 must be bent up and not inserted ; into the socket on the MTG card. Device pin #7 connects via white wire to ; socket pin #12. ; ; ; Following is the SIMULATION data for the MTGBIT15 PAL. ; SIMULATION ; We will start by checking the CBus Register section of this PAL for ; Reading and Writing the three bits SelROM, SelCmp, CmpBit. ; Enable tracing of several signals TRACE_ON D2_In SelExt D5_In CmpBit D3_In SelROM Ld_Reg /Rd_Reg ExtBit ExtEnb ROM_In /TMLtch /FstHld /SecHld /TS_Out ; Set no loading or readback of the CBus data register. ; Set all three input bits low. SETF /Ld_Reg /Rd_Reg SETF /D2_In /D3_In /D5_In SETF /ROM_In /ExtBit /ExtEnb ; Make a CBus cycle to load the Register. CLOCKF LD_Reg ; Clock the LD_Reg signal. ; Enable readback and Verify that all three outputs are low. SETF Rd_Reg ; Rd_Reg goes to 0V. CHECK /SelExt /CmpBit /SelROM ; Verify that all three are 0V. SETF /Rd_Reg ; Rd_Reg goes to +5V. ; Now Set the D3_In high and Load the register. SETF /D2_In /D5_In D3_In ; D3_In is +5V the other two are 0V CLOCKF LD_Reg ; Clock the LD_Reg signal. SETF /D2_In /D5_In /D3_In ; All three are at 0V. ; Enable readback and Verify that SelROM is high and the other two are low. SETF Rd_Reg ; Rd_Reg goes to 0V. CHECK /SelExt /CmpBit SelROM ; Verify SelROM is +5V and the others 0V. SETF /Rd_Reg ; Rd_Reg goes to +5V. ; ======================================================================= ; Now start checking the timing signal generation logic part of this PAL ; Start with the "normal" MTGBIT8 mode of operation. ; NOTE that we are in the SelROM mode of operation. ; ======================================================================= ; Start by setting ExtBit and ROM_In to 0V and ExtEnb to +5V. SETF /ExtBit ExtEnb /ROM_In ; Now run a series of ROM clock pulses to get things defined. SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In ; Now check that that /TMLtch /FstHld /SecHld /TS_Out are all at +5V Check /TMLtch /FstHld /SecHld /TS_Out ; Now set the ExtBit input to +5V and verify that only TMLtch becomes ; active (i.e. 0V). NOTE there has been no ROM_In yet. SETF ExtBit Check TMLtch /FstHld /SecHld /TS_Out ; NOTE that ExtBit has been left at +5V ; Take the ROM Pulse to +5V. ; Verify that /FstHld /SecHld are at +5V and /TMLtch /TS_Out are at 0V. SETF ROM_In Check TMLtch /FstHld /SecHld TS_Out ; NOTE that ExtBit has been left at +5V ; Take the ROM Pulse back to 0V. ; Verify that /SecHld is at +5V and /TMLtch /FstHld /TS_Out are at 0V. SETF /ROM_In Check TMLtch FstHld /SecHld TS_Out ; NOTE that ExtBit has been left at +5V ; During the time that the output pulse is active, the input trigger ExtBit ; should become inactive. So we will take ExtBit inactive now. Note that ; TMLtch will remain active because of the hold term it has from /SecHld. SETF /ExtBit Check TMLtch FstHld /SecHld TS_Out ; Take the ROM Pulse back to +5V. ; Verify that /TMLtch /FstHld /SecHld /TS_Out are all at +5V ; Note that when the ROM Pulsed high for the second time, SecHld became ; active (0V) just long enough to remove the hold on TMLtch and on TS_Out ; which removed the hold on FstHld which forced SecHld back inactive. SETF ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Pulse the PROM a number of times and verify that nothing changes. ; Verify that /TMLtch /FstHld /SecHld /TS_Out are all at +5V SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out SETF ROM_In Check /TMLtch /FstHld /SecHld /TS_Out SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out SETF ROM_In Check /TMLtch /FstHld /SecHld /TS_Out SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; OK this finishes the test of normal MTGBIT8 PAL type of operation. ; ======================================================================= ; Now do some "remember mode" testing. ; NOTE that we are still in the SelROM mode of operation. ; ======================================================================= ; Set the ExtBit ExtEnb and ROM_In to their inactive states of 0V. ; Verify that nothing has changed. ; Give some PROM clocks and verify that nothing changes. SETF /ExtBit /ExtEnb /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out SETF ROM_In SETF /ROM_In SETF ROM_In SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Now let's take ExtBit to +5 and then back to 0V. ; Verify that nothing changes except that TMLtch becomes active i.e. 0V. SETF ExtBit SETF /ExtBit Check TMLtch /FstHld /SecHld /TS_Out ; OK let's give the system some clocks and prove that nothing changes SETF ROM_In Check TMLtch /FstHld /SecHld /TS_Out SETF /ROM_In Check TMLtch /FstHld /SecHld /TS_Out SETF ROM_In Check TMLtch /FstHld /SecHld /TS_Out SETF /ROM_In Check TMLtch /FstHld /SecHld /TS_Out ; We have remembered that we need to make an output pulse, so now let's ; bring ExtEnb active (+5V) and let the action begin. SETF ExtEnb ; ExtEnb becomes active, +5V. Check TMLtch /FstHld /SecHld /TS_Out ; Nothing happens yet. SETF ROM_In ; Start the PROM pulse. Check TMLtch /FstHld /SecHld TS_Out ; And the output pulse should start SETF /ROM_In ; End the PROM pulse. Check TMLtch FstHld /SecHld TS_Out ; That's Me Latch is still active ; i.e. 0V) because it does not drop ; until SecHld becomes active. ; FstHld becomes active (i.e. ; goes to 0V). SETF ROM_In ; Start the next the PROM pulse. Check /TMLtch /FstHld /SecHld /TS_Out ; The output pulse and FstHld and ; TMLtch all become inactive ; (i.e. goto +5V). ; Note that when the ROM Pulsed high for the second time, SecHld became ; active (0V) just long enough to remove the hold on TMLtch and on TS_Out ; which removed the hold on FstHld which forced SecHld back inactive. ; Give the system another ROM_In clock and prove that nothing happens. SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. SETF ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. ; Now bring ExtEnb inactive and check that still nothing changes with ; additional ROM clocks SETF /ExtEnb Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. SETF ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. SETF /ROM_In Check /TMLtch /FstHld /SecHld /TS_Out ; Nothing should change. TRACE_OFF ; End this simulation.