TITLE This is the PAL to control the Write A/B TSS signal PATTERN MTGBIT9D REVISION 1.00 D AUTHOR Level 1 Trigger COMPANY MSU HEP DATE 15-NOV-1992 ; The detailed description of this device is at the end of this file. CHIP MTGBIT9D PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 9 10 /Pre_LD D1_In D2_In LD_Reg ROM_In /RD_Reg CMR_ROM CMR_Trg StrDig GND ;11 12 13 14 15 16 17 18 19 20 /Glb_OE CmpMode RmCMR CMR_Tog StrDgTog L15Mode D2_Out D1_Out /TS_Out Vcc ; The "Clear Most Recent Trigger" signal is connected to Ext_Enb i.e. pin 8. ; The COMINT "Start Digitization" signal is connected to Ext_Bit i.e. pin 9. EQUATIONS /L15Mode := /D1_In ; This term is the CBUS Data In Bit /L15Mode.CLKF = LD_Reg ; #1, latched by the rising edge of /L15Mode.TRST = Vcc ; the Load Register (aka Write FA /L15Mode.SETF = GND ; #n). It is always output enabled /L15Mode.RSTF = GND ; and fed-back to the matrix. ; Storing a 0 --> Level 1 Mode. ; Storing a 1 --> Level 1.5 Mode. D1_Out := L15Mode ; This term is the CBUS Data Out Bit D1_Out.CLKF = GND ; #1. It is not latched. It is D1_Out.TRST = RD_Reg ; output-enabled while Read Register D1_Out.SETF = Vcc ; (aka /Read FA #n) is low. It D1_Out.RSTF = Vcc ; reflects the state of the Level 15 ; mode bit (L15Mode). /CmpMode := /D2_In ; This term is the CBUS Data In Bit /CmpMode.CLKF = LD_Reg ; #2, latched by the rising edge of /CmpMode.TRST = Vcc ; the Load Register (aka Write FA /CmpMode.SETF = GND ; #n). It is always output enabled /CmpMode.RSTF = GND ; and fed-back to the matrix. ; Storing a 0 --> Normal Write A/B ; Operation ; Storing a 1 --> Computer Mode ; Operation D2_Out := CmpMode ; This term is the CBUS Data Out Bit D2_Out.CLKF = GND ; #2. It is not latched. It is D2_Out.TRST = RD_Reg ; output-enabled while Read Register D2_Out.SETF = Vcc ; (aka /Read FA #n) is low. It D2_Out.RSTF = Vcc ; reflects the state of the Computer ; mode bit (CmpMode). /RmCMR := /CMR_Trg ; This is the term that "remembers" /RmCMR.CLKF = ROM_In ; the Clear Most Recent signal. It /RmCMR.TRST = Vcc ; is clocked the the ROM signal and /RmCMR.SETF = GND ; it D input is the Clear Most Recent. /RmCMR.RSTF = GND /StrDgTog := StrDgTog ; This internal signal toggels each /StrDgTog.CLKF = StrDig * ROM_In ; time that the COMINT Start /StrDgTog.TRST = Vcc ; Digitization signal fires. /StrDgTog.SETF = GND /StrDgTog.RSTF = GND /CMR_Tog := CMR_Tog ; This internal signal toggels /CMR_Tog .CLKF = RmCMR * CMR_ROM * L15Mode ; each time that the COMINT /CMR_Tog .TRST = Vcc ; Clear Most Recent Trigger /CMR_Tog .SETF = GND ; signal fires and the PAL is /CMR_Tog .RSTF = GND ; in Level 1.5 mode. TS_Out := StrDgTog * /CMR_Tog * /CmpMode ; This is the output term + /StrDgTog * CMR_Tog * /CmpMode ; (Write A/B). It is the + L15Mode * CmpMode ; Xor of the Start Digitize TS_Out.CLKF = GND ; Toggle and the Clear Most TS_Out.TRST = Vcc ; Recent Trigger Toggle. TS_Out.SETF = Vcc ; This term can also be TS_Out.RSTF = Vcc ; forced high by setting ; both L15Mode and CmpMode ; High. ; /Glb_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ; ; /Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for all terms. ; ; ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output low, and RESETting the latch ; drives the output high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /TS_OUT) is inverted before being driven off-card. ; ; Following is the SIMULATION data for the MTGBIT9C PAL. ; SIMULATION ; Enable tracing of several signals TRACE_ON D1_In L15Mode D1_Out D2_In CmpMode D2_Out CMR_Trg StrDig CMR_ROM RmCMR ROM_In CMR_Tog StrDgTog TS_Out ; Disable preload, enable global OE (done in wiring on the PAL) SETF /Pre_LD Glb_OE ; Set no loading or readback of the CBus data register. SETF /LD_Reg /RD_Reg ; Set all of the logic signal SETF /ROM_In /CMR_ROM /CMR_Trg /StrDig ; Set i.e. force all D flip flops low PRLDF /StrDgTog /CMR_Tog /RmCMR /L15Mode /CmpMode ; First test bit #2 of the CBus regester; load a 1. SETF D2_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load bit #2 with a value of one; CmpMode SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK CmpMode D2_Out ; Verify that the value of bit #2 is one. SETF /RD_Reg ; End the CBus read cycle. ; First test bit #2 of the CBus regester; load a 1. SETF /D2_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load bit #2 with value of zero; /CmpMode SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK /CmpMode /D2_Out ; Verify that the value of bit #2 is zero. SETF /RD_Reg ; End the CBus read cycle. ; OK we are not in Computer Mode ; Now test bit #1 of the CBus data register for data 1. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load bit #1 with a value of one. L15 Mode SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK L15Mode D1_Out ; Verify that the value of bit #1 is one. SETF /RD_Reg ; End the CBus read cycle. ; Now test bit #1 of the CBus data register for data 0. SETF /D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load bit #1 with a value of zero; /L15Mode SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK /L15Mode /D1_Out ; Verify that the value of bit #1 is zero. SETF /RD_Reg ; End the CBus read cycle. CHECK /L15Mode /CmpMode ; Verify that we are still in Level 1 Mode ; and not in Computer Mode. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. ; i.e. verify that the MTG output is low. ; Check the normal Level 1 Mode of the Write A/B signal. SETF ROM_In ; First just make some ROM clocks and CHECK /TS_Out ; see that nothing happens, i.e. the SETF /ROM_In ; MTG Channel output remains low, i.e. CHECK /TS_Out ; Write A/B does not flip. SETF ROM_In ; Clock it more. CHECK /TS_Out ; Keep checking. SETF /ROM_In ; More clocks. CHECK /TS_Out ; All is still OK. ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK /TS_Out ; happens. SETF ROM_In ; And ROM Clock goes high. CHECK TS_Out ; Write A/B should now swap SETF /StrDig ; This is the earlies that Start Digitize CHECK TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK TS_Out ; should still hold state. ; More clocks and the Write A/B SETF ROM_In ; should still hold state. CHECK TS_Out ; SETF /ROM_In ; CHECK TS_Out ; ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK TS_Out ; happens. SETF ROM_In ; And ROM Clock goes high. CHECK /TS_Out ; Write A/B should now swap SETF /StrDig ; This is the earlies that Start Digitize CHECK /TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK /TS_Out ; should still hold state. ; More clocks and the Write A/B SETF ROM_In ; should still hold state Low. SETF CMR_Trg ; \ SETF CMR_ROM ; \ Move all of the Clear Most Recent SETF /CMR_ROM ; / Trigger signals and Clock. SETF /CMR_Trg ; / CHECK /TS_Out ; Nothing should have changed. SETF /ROM_In ; SETF CMR_Trg ; \ SETF CMR_ROM ; \ Move all of the Clear Most Recent SETF /CMR_ROM ; / Trigger signals and Clock. SETF /CMR_Trg ; / CHECK /TS_Out ; TS_Out should still hold state Low. ; OK all of this Level 1 operation looks fine but what if the Clear Most ; Recent Trigger toggle flip flop was in the other state. PRLDF CMR_Tog /StrDgTog ; Now the Clear Most Recent Toggle will be /TS_Out /L15Mode ; set high. We start testing with the /RmCMR /CmpMode ; Start Digitize Toggle low. Remember that ; all of the latches must be specified in ; the PRLDF statement. SETF ROM_In ; First just make some ROM clocks and CHECK TS_Out ; see that nothing happens, i.e. the SETF /ROM_In ; MTG Channel output remains low, i.e. CHECK TS_Out ; Write A/B does not flip. SETF ROM_In ; Clock it more. CHECK TS_Out ; Keep checking. SETF /ROM_In ; More clocks. CHECK TS_Out ; All is still OK. ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK TS_Out ; happens. SETF ROM_In ; And ROM Clock goes high. CHECK /TS_Out ; Write A/B should now swap SETF /StrDig ; This is the earlies that Start Digitize CHECK /TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK /TS_Out ; should still hold state. ; More clocks and the Write A/B SETF ROM_In ; should still hold state. CHECK /TS_Out ; SETF /ROM_In ; CHECK /TS_Out ; ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK /TS_Out ; happens. SETF ROM_In ; And ROM Clock goes high. CHECK TS_Out ; Write A/B should now swap and go high. SETF /StrDig ; This is the earlies that Start Digitize CHECK TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK TS_Out ; should still hold state. SETF CMR_Trg ; \ SETF ROM_In ; \ SETF /ROM_In ; | SETF CMR_ROM ; | Move all of the Clear Most Recent SETF ROM_In ; | Trigger signals and Clock, and SETF /CMR_ROM ; | move ROM Clk and the Write A/B SETF /CMR_Trg ; | should still hold state. SETF ROM_In ; | SETF /ROM_In ; / CHECK TS_Out ; / SETF CMR_Trg ; \ SETF CMR_ROM ; \ Move all of the Clear Most Recent SETF /ROM_In ; | Trigger signals and Clock, and SETF /CMR_ROM ; | move ROM Clk and the Write A/B SETF /CMR_Trg ; / should still hold state. CHECK TS_Out ; / ; Now switch to L1.5 Mode and test the operation with both Start ; Digitization signals and Clear Most Recent Trigger Signals. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. i.e. L15 Mode. SETF /LD_Reg ; Clock it in with a CBus write cycle. ; First test that Start Digitize Still works. ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK TS_Out ; happens. TS_Out holds High. SETF ROM_In ; And ROM Clock goes high. CHECK /TS_Out ; Write A/B should now swap and go LOW. SETF /StrDig ; This is the earlies that Start Digitize CHECK /TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK /TS_Out ; should still hold state LOW. SETF ROM_In ; More clocks and the Write A/B CHECK /TS_Out ; should still hold state. SETF /ROM_In ; More clocks and the Write A/B CHECK /TS_Out ; should still hold state Low. SETF StrDig ;\ SETF CMR_ROM ; \ Now let the Start Digitization signal SETF /CMR_ROM ; | arrive More CMR_ROM clocks and the SETF /StrDig ; / Write A/B should hold state Low. CHECK /TS_Out ;/ SETF CMR_Trg ;\ SETF ROM_In ; \ SETF /ROM_In ; | SETF ROM_In ; | Now let the Clear Most Recent signal SETF /ROM_In ; | arrive. More ROM_In clocks and the SETF /CMR_Trg ; | Write A/B should hold state Low. SETF ROM_In ; | SETF /ROM_In ; / CHECK /TS_Out ;/ ; Now test the Clear Most Recent. ; Now let the Clear Most Recent Trigger SETF CMR_Trg ; arrive and verify that by itself nothing SETF ROM_In ; happens. ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK /TS_Out ; TS_Out holds LOW. SETF CMR_ROM ; And Clear Most Recent ROM Clock goes high. CHECK TS_Out ; Write A/B should now swap and goes High. SETF /CMR_Trg ; This is the earlies that Clr Most Recent SETF ROM_In ; can go away. ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK TS_Out ; Write A/B should hold state. SETF /CMR_ROM ; The CMR ROM pulse falls and the Write A/B CHECK TS_Out ; should still hold state High SETF CMR_ROM ; More CMR_ROM clocks and the Write A/B CHECK TS_Out ; should still hold state. SETF /CMR_ROM ; More clocks and the Write A/B CHECK TS_Out ; should still hold state High SETF StrDig ;\ SETF CMR_ROM ; \ Now let the Start Digitization signal SETF /CMR_ROM ; | arrive More CMR_ROM clocks and the SETF /StrDig ; / Write A/B should hold state High. CHECK TS_Out ;/ SETF CMR_Trg ;\ SETF ROM_In ; \ SETF /ROM_In ; | ROM_In Clocks for RmCMR. SETF ROM_In ; | Now let the Clear Most Recent signal SETF /ROM_In ; | arrive. More ROM_In clocks and the SETF /CMR_Trg ; | Write A/B should hold state High. SETF ROM_In ; | SETF /ROM_In ; / CHECK TS_Out ;/ ; And now a second test of Start Digitize (i.e. starting with the ; (CMR_Tog in the other state). ; Now let the Start Digitization signal SETF StrDig ; arrive and verify that by itself nothing CHECK TS_Out ; happens. TS_Out holds High. SETF ROM_In ; And ROM Clock goes high. CHECK /TS_Out ; Write A/B should now swap and go LOW. SETF /StrDig ; This is the earlies that Start Digitize CHECK /TS_Out ; can go away. Write A/B should hold state. SETF /ROM_In ; The ROM pulse falls and the Write A/B CHECK /TS_Out ; should still hold state LOW. SETF StrDig ; Now another state swap caused by Start SETF ROM_In ; Digitize. This time put the ROM_In SETF /ROM_In ; Clock inside the Start Digitize Signal. SETF /StrDig ; CHECK TS_Out ; Verify that Write A/B toggeled High. SETF StrDig ;\ SETF CMR_ROM ; \ Now let the Start Digitization signal SETF /CMR_ROM ; | arrive More CMR_ROM clocks and the SETF /StrDig ; / Write A/B should hold state Low. CHECK TS_Out ;/ SETF CMR_Trg ;\ SETF ROM_In ; \ SETF /ROM_In ; | ROM_In Clocks for RmCMR. SETF ROM_In ; | Now let the Clear Most Recent signal SETF /ROM_In ; | arrive. More ROM_In clocks and the SETF /CMR_Trg ; | Write A/B should hold state Low. SETF ROM_In ; | SETF /ROM_In ; / CHECK TS_Out ;/ ; And now a second test of Clear Most Recent (i.e. starting with the ; (StrDgTog in the other state). ; Now let the Clear Most Recent Trigger SETF CMR_Trg ; arrive and verify that by itself nothing SETF ROM_In ; happens. ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK TS_Out ; TS_Out holds LOW. SETF CMR_ROM ; And Clear Most Recent ROM Clock goes high. CHECK /TS_Out ; Write A/B should now swap and goes Low. SETF /CMR_Trg ; This is the earlies that Clr Most Recent SETF ROM_In ; can go away. SETF /ROM_In ; ROM_In Clocks for RmCMR. CHECK /TS_Out ; Write A/B should hold state. SETF /CMR_ROM ; The CMR ROM pulse falls and the Write A/B CHECK /TS_Out ; should still hold state Low. SETF CMR_Trg ; Now another state swap caused by Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR.; SETF /ROM_In ; CHECK TS_Out ; Verify that Write A/B toggeled High. SETF CMR_Trg ; Now another state swap caused by Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; Most Recent Trigger. This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK /TS_Out ; Verify that Write A/B toggeled Low. SETF StrDig ;\ SETF CMR_ROM ; \ Now let the Start Digitization signal SETF /CMR_ROM ; | arrive More CMR_ROM clocks and the SETF /StrDig ; / Write A/B should hold state Low. CHECK /TS_Out ;/ SETF CMR_Trg ;\ SETF ROM_In ; \ SETF /ROM_In ; | ROM_In Clocks for RmCMR. SETF ROM_In ; | Now let the Clear Most Recent signal SETF /ROM_In ; | arrive. More ROM_In clocks and the SETF /CMR_Trg ; | Write A/B should hold state Low. SETF ROM_In ; | SETF /ROM_In ; / CHECK /TS_Out ;/ ; Now verify the operation of RmCMR SETF CMR_Trg ; Now another state swap caused by Clear SETF CMR_ROM ; This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most CHECK /TS_Out ; Verify that Write A/B toggeled Low. SETF ROM_In ; SETF /ROM_In ; And NOW the ROM_In Clocks for RmCMR. SETF CMR_ROM ; SETF /CMR_ROM ; And now a second CMR_ROM Clock. CHECK TS_Out ; Verify that Write A/B toggele SETF /CMR_Trg ; High now; i.e. It held until after there SETF ROM_In ; was a ROM_In Clock after CMR_Trg was Hi. SETF /ROM_In ; ; OK, now switch to Computer Mode and verify that the Write A/B signal can ; be manually controlled and that the normal Start Digitize and Clear Most ; Recent Trigger inputs do nothing. ; Test that Write A/B TS_Out can be forced and held LOW. SETF /D1_In D2_In ; Load Computer Mode with the L15Mode bit SETF LD_Reg ; set Low. This should force the Write A/B SETF /LD_Reg ; to a low state. SETF RD_Reg ; Do a CBus Read Cycle to verify that the CHECK /L15Mode /D1_Out ; control registers have been loaded OK Check CmpMode D2_Out ; SETF /RD_Reg ; End the CBus read cycle. CHECK /TS_Out ; Verify that Write A/B toggele is LOW. ; And now lots of clocking and TS_Out ; should not change states. SETF CMR_Trg ; Try to cause a state swap with Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; Most Recent Trigger. This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK /TS_Out ; Verify that Write A/B held Low. SETF StrDig ; Try to cause a state swap with Start SETF ROM_In ; Digitize. Set Start Digitize High and SETF /ROM_In ; ROM clock it in. Now ROM clock and SETF /StrDig ; Start Digitize both are low again. CHECK /TS_Out ; Verify that Write A/B held Low. ; And once again lots of clocking and ; TS_Out should not change states. SETF CMR_Trg ; Try to cause a state swap with Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; Most Recent Trigger. This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK /TS_Out ; Verify that Write A/B held Low. SETF StrDig ; Try to cause a state swap with Start SETF ROM_In ; Digitize. Set Start Digitize High and SETF /ROM_In ; ROM clock it in. Now ROM clock and SETF /StrDig ; Start Digitize both are low again. CHECK /TS_Out ; Verify that Write A/B held Low. ; Now test that Write A/B TS_Out can be forced and held High. SETF D1_In D2_In ; Load Computer Mode with the L15Mode bit SETF LD_Reg ; set High. This should force the Write A/B SETF /LD_Reg ; to a low state. SETF RD_Reg ; Do a CBus Read Cycle to verify that the CHECK L15Mode D1_Out ; control registers have been loaded OK Check CmpMode D2_Out ; SETF /RD_Reg ; End the CBus read cycle. CHECK TS_Out ; Verify that Write A/B toggele is High. ; And now lots of clocking and TS_Out ; should not change states. SETF CMR_Trg ; Try to cause a state swap with Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; Most Recent Trigger. This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK TS_Out ; Verify that Write A/B held High. SETF StrDig ; Try to cause a state swap with Start SETF ROM_In ; Digitize. Set Start Digitize High and SETF /ROM_In ; ROM clock it in. Now ROM clock and SETF /StrDig ; Start Digitize both are low again. CHECK TS_Out ; Verify that Write A/B held High. ; And once again lots of clocking and ; TS_Out should not change states. SETF CMR_Trg ; Try to cause a state swap with Clear SETF ROM_In ; Most Recent Trigger. SETF /ROM_In ; ROM_In Clocks for RmCMR. SETF CMR_ROM ; Most Recent Trigger. This time put SETF /CMR_ROM ; CMR_ROM Clock inside the Clear Most SETF /CMR_Trg ; Recent Trigger signal. SETF ROM_In ; ROM_In Clocks for RmCMR. SETF /ROM_In ; CHECK TS_Out ; Verify that Write A/B held High. SETF StrDig ; Try to cause a state swap with Start SETF ROM_In ; Digitize. Set Start Digitize High and SETF /ROM_In ; ROM clock it in. Now ROM clock and SETF /StrDig ; Start Digitize both are low again. CHECK TS_Out ; Verify that Write A/B held High. TRACE_OFF ; ; Description of the MTGBIT9C PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket. ; The following table shows the connections used with this device. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In D1_In Socket pin tied to device pin. ; ; 3 Data 2 In D2_In Socket pin tied to device pin. ; This input is not used in this design. ; ; 4 Data 3 In /LD_Reg Device pin 4 connected to socket ; pin 1. Load CBus registers on ; rising edge. Socket pin 4 is not used. ; ; 5 Data 4 In ROM_In Device pin 5 connected to socket pin ; 12. This is the ROM input. Socket ; pin 5 is not used. ; ; 6 Data 5 In /RD_Reg Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; Socket pin 6 is not used. ; ; 7 Data 6 In CMR_ROM Device pin 7 is connected to the ; extra ROM signal for the Clear Most ; Recent Toggle timing. Socket pin ; 7 is not used. ; ; 8 Ext-Enb CMR_Trg Socket pin tied to device pin. ; It receives the Clear Most Recent ; Trigger signal. ; ; 9 Ext-Bit StrDig Socket pin tied to device pin. ; It Receives the COMINT Start ; Digitization signal. ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit CmpMode Device pin is not connected to socket. ; Socket pin 12 connected to device ; pin 5. ; ; 13 Data 6 Out RmCMR Device pin not connected to socket pin ; ; 14 Data 5 Out CMR_Tog Device pin not connected to socket pin ; ; 15 Data 4 Out StrDgTog Device pin not connected to socket pin ; ; 16 Data 3 Out L15Mode Device pin not connected to socket pin ; ; 17 Data 2 Out D2_Out Socket pin tied to device pin. ; ; 18 Data 1 Out D1_Out Socket pin tied to device pin. ; ; 19 Channel Out /TS_Out Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; ; ; ; 22-OCT-1992 ; ; This is a new PAL design to control the Write A/B control line. The old ; design needs to be replaced because of a control logic change which is ; necessary in order to properly capture the state of the L1.5 system when ; the L1.5 Rejects a candidate L1 trigger. ; ; The Write A/B pipes must continue to swap at the same point in the 3.5 usec ; cycle when this swap is caused by a L1 firing (i.e. a Start Digitization). ; ; When the Write A/B swap is caused by a L1.5 Reject then the pipes must swap ; later in the 3.5 usec cycles; other wise the L15 data from the Reject will ; be overwritten. ; ; The Timing is controlled by two conditions: ; ; 1. Must not swap the pipes back to their "pre L15 cycle" state until the ; Latch-Shifting is all finished. The last latch-shifting is the L15 END ; DBSC Latch. This is at about tick #27 of the BX cycle following the BX ; cycle where the L15 Reject decision was taken. ; ; 2. Must swap before either the Cal Trig or the L1 Framework make their ; Latch-Shift on the BX following the BX which contained the L15 decision ; to Reject. At this time Cal Trig 29525 Latch-Shift is the earliest and ; it arrives at about tick 52. ; ; One must also consider the time difference between M114 and the L15 system ; in rack M103 and the difference between setup and hold considerations. ; ; Currently the Write A/B pipe swaps (for both Start Digitize and also for ; L15 Reject at tick 8 and 9. The idea is to move the Write A/B swap in ; responce to a L15 Reject at about ticks 33 and 34. This swap after L15 ; Reject will leave M114 about 75 nsec after the end of the last latch pulses ; in M103 (and about 220 nsec after the positive active edge of these last ; latch pulses). ; ; The "Remember Clear Most Recent" signal is necessary because the normal ; Clear Most Recent signal from the Trig-Acq-Sync Cable gone by the time ; that you want to flip the Write A/B pipe in response to a L15 reject. ; ; Note that the timing on this is rather tight. The clock to the flip flop ; which remembers the Clear Most Recent is clocked beginning at tick 8 and ; Clear Most Recent signal goes away at tick 9. This should work fine just ; so long as nothing is changed. There is plenty of setup time and the ; Clear Most Recent starts to go away at tick 9 in rack M103 so it takes it ; an extra 75 nsec to go away in rack M114 (i.e. there is really plenty of ; hold time). ; ; The idea is to continue to use FrameWork Main Timing MTG channel #5 to ; control the timing of the Write A/B swap caused by Start Digitize. The ; timing information (i.e. PROM pattern) FrameWork Main Timing MTG channel ; #1 will be stollen to control the Write A/B swap by L15 Rejects. Thus the ; new PAL for controlling Write A/B will receive 2 timing signals. ; ; ; This MTGBIT9D PAL has a 2 bit wide programmable control register. Data ; bit #1 (value=1) controls the L15Mode. If this bit is low then only the ; Start Digitization signal can cause the Write A/B output to switch ; states. If the L15Mode bit is programmed high then either a Start ; Digitization or a Clear Most Recent Trigger signal will cause the ; Write A/B output to switch states. ; ; Data bit #2 (value=2) is the Computer Mode bit (CmpMode). If this bit ; is programmed low then the Write A/B output reacts to the Start ; Digitization signal and the Clear Most Recent Trigger signal (if ; enabled by the L15Mode bit). If the CmpMode bit is programmed high then ; the Write A/B output is NOT controlled by the Start Digitization and ; Clear Most Recent signals but rather it follows the state of the L15Mode ; bit (i.e. if the L15Mode is programmed high then the Write A/B is high, ; if the L15Mode is programmed low then the Write A/B is low). ; ; ; Data Data ; Bit #2 Bit #1 ; ; CmpMode L15Mode Operation of the Write A/B Output ; ------- ------- ---------------------------------------------------- ; 0 0 Switches state with only the Start Digitize signal. ; ; 0 1 Switches state with either the Start Digitize ; signal or the Clear Most Recent Trigger Signal. ; ; 1 0 Write A/B output is forced Low (B pipe). ; ; 1 1 Write A/B output is forced High (A pipe). ; ; ; ; ; The Timing Diagram and the Block Diagram Below ; Do Not Show the Computer Mode Circuitry ; ; ; Write A/B Toggle Caused by a L1 Specific Trigger Firing ; Beam ; Cross -X--------------------X--------------------X--------------------X-- ; ; _ _ _ ; ROM_Bit ___| |__________________| |__________________| |__________________| ; ; Start _____ ; Digitze ______________________| |______________________________________ ; ; Write _________________________ _________________________________________ ; A/B _________________________X_________________________________________ ; ; ; ; Write A/B Toggle Caused by a L1.5 Reject ; Beam ; Cross -X--------------------X--------------------X--------------------X-- ; ; _ _ _ ; ROM_Bit ___| |__________________| |__________________| |__________________| ; ; Clear ________ ; Most Recent ______________| |_______________________________________ ; ; Remember ____________________ ; CMR _________________________| |____________________ ; ; Extra _ _ _ ; CMR ROM ________| |__________________| |__________________| |______________ ; ; Write ______________________________ ____________________________________ ; A/B ______________________________X____________________________________ ; ; ; ; ; Block Diagram of the MTGBIT9C PAL ; --------------------------------------- ; ; ; ; Start +-------+ ; Digit >------| | +--------+ ; | AND |---------|CLK Q |---------+ ; PROM >--+---| | | | | ; Time | |_______| | | | ; | +----| D /Q |----+ | ; | | |________| | | ; | | | | +-------+ ; | +------------------+ +----| | ; | | XOR |------> ; | +----| | ; | +--------+ | |_______| Write ; +-----------|CLK Q |------+ | A/B ; | | | | ; Clear | | | | ; Most >--------------| D /Q | | | ; Recent |________| | | ; Trigger | | ; +--------------------------+ | ; | | ; | +-------+ | ; +----| | | ; Extra | | +--------+ | ; PROM >---------| AND |---------|CLK Q |-------+ ; for late | | | | ; CMR togl +----| | | | ; | |_______| +----| D /Q |----+ ; | | |________| | ; Enable | | | ; L15 | +------------------+ ; Reject | Read ; Toggle | Data ; +-------------------------------+ Bus ; Write | +---------+ Bit 1 ; Data +--------+ | | Data | ; Bus >---------------------|D Q |----+---------| Bus |-------> ; Bit 1 | | | Driver | ; | | +---------+ ; Write >---------------------|CLK /Q |-- | ; Data Clk |________| | Enable ; | ; | ; Read >--------------------------------------------------+ ; Data ;