TITLE Start Digitization Number Increment PAL Framework Main Timing MTG PATTERN STDGNINC REVISION 1.00 AUTHOR Level 1 Trigger COMPANY MSU HEP DATE 1-JUNE-1992 ; The detailed description of this device is at the end of this file. CHIP STDGNINC PAL16RA8 ;PINS ;1 2 3 4 5 6 7 8 9 10 /Pre_LD D1_In D2_In LD_Reg ROM_In /RD_Reg D6_In LtGlSTF L15Stch GND ;11 12 13 14 15 16 17 18 19 20 /Glb_OE No_Con No_Cn1 No_Cn2 No_Cn3 /SaveStch L15Mode D1_Out /TS_Out Vcc ; Latched Global Spec Trig Fired (LtGlSTF) is connected to Ext_Enb pin 8. ; Level 1.5 Stretch (L15Stch) is connected to Ext_Bit pin 9. ; This device has active-low outputs. It simulates programmable ; output polarity by allowing the latch "D" input to be inverted. ; For unlatched outputs, this is equivalent to programmable ; polarity. For latched outputs, note that SETting the latch ; corresponds to driving the output low, and RESETting the latch ; drives the output high. ; ; Also recall that, on the MTG, the signal connected to pin 19 ; (usually called /TS_OUT) is inverted before being driven off-card. EQUATIONS ; /Glb_OE = GND ; This term is the active-low ; ; Global Output Enable. By wiring ; ; this term low, all output terms ; ; are controlled by their "per-term" ; ; Output Enable (term.TRST). ; /Pre_LD = Vcc ; This term is the active-low ; ; Preload. By wiring this term ; ; high, the pre-load function is ; ; disabled for all terms. /L15Mode := /D1_In ; This term is the CBUS Data In Bit /L15Mode.CLKF = LD_Reg ; #1, latched by the rising edge of /L15Mode.TRST = Vcc ; the Load Register (aka Write FA /L15Mode.SETF = GND ; #n). It is always output enabled /L15Mode.RSTF = GND ; and fed-back to the matrix. ; Storing a 0 --> Level 1 Mode. ; Storing a 1 --> Level 1.5 Mode. D1_Out := L15Mode ; This term is the CBUS Data Out Bit D1_Out.CLKF = GND ; #1. It is not latched. It is D1_Out.TRST = RD_Reg ; output-enabled while Read Register D1_Out.SETF = Vcc ; (aka /Read FA #n) is low. It D1_Out.RSTF = Vcc ; reflects the state of Data_1, ; the mode bit. SaveStch := L15Stch ; Save the state of the L15 Stretch SaveStch.CLKF = /ROM_In ; signal at the time that the ROM SaveStch.TRST = Vcc ; time signal falls. SaveStch.SETF = GND SaveStch.RSTF = /L15Mode TS_Out := LtGlSTF * ROM_In * /L15Mode + LtGlSTF * ROM_In * L15Mode * /L15Stch + /LtGlSTF * ROM_In * L15Mode * /L15Stch * SaveStch TS_Out.CLKF = GND TS_Out.TRST = Vcc ; The 1st term is for Level 1 Mode TS_Out.SETF = Vcc ; "standard" operation. The 2nd TS_Out.RSTF = Vcc ; term is the L15 Mode either a pure ; L1 Trig or a confirmed L15 Trig. ; The 3rd term is L15 Mode a rejected ; level 15 trig. No_Con.TRST = GND ; This "product line" is not used. No_Con.CLKF = GND No_Cn1.TRST = GND ; This "product line" is not used. No_Cn1.CLKF = GND No_Cn2.TRST = GND ; This "product line" is not used. No_Cn2.CLKF = GND No_Cn3.TRST = GND ; This "product line" is not used. No_Cn3.CLKF = GND ; ; Following is the SIMULATION data for the STDGNINC PAL. ; SIMULATION ; Enable tracing of several signals TRACE_ON D1_In L15Mode D1_Out LtGlSTF L15Stch ROM_In SaveStch TS_Out ; Disable preload, enable global OE (done in wiring on PCB) ; Set no loading or readback of the CBus data register. SETF /ROM_In /LD_Reg /RD_Reg SETF /Pre_LD Glb_OE PRLDF /TS_Out /SaveStch SETF /LtGlSTF /L15Stch ; First test the one bit CBus data register for data 1. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. i.e. L15 Mode. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK L15Mode D1_Out ; Verify that the value of Data 1 is one. SETF /RD_Reg ; End the CBus read cycle. SETF /D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of zero. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK /L15Mode /D1_Out ; Verify that the value of Data 1 is zero. SETF /RD_Reg ; End the CBus read cycle. CHECK /L15Mode ; Verify that we are still in Level 1 Mode. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. ; i.e. verify that the MTG ch #14 is low. ; Check the normal Level 1 Mode L1 Trig. SetF LtGlSTF ; Set Latched Global Spec Trig Fired Strobe. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF ROM_In ; ROM signal goes active Check TS_Out ; Verify that the MTG signal is now high ; PAL output pin at 0V. --> Inc pulse SetF /ROM_In ; ROM pulse ends CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF /LtGlSTF ; Clear the Latched Spec Trig Fired Strobe. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF ROM_In ; ROM signal goes active CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF /ROM_In ; ROM pulse ends CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. ; Now verify that the L1.5 sections can not ; set the Increment pulse to the Start ; Digitize Number DBSC scaler. SetF ROM_In LtGlSTF /L15Stch ; Set all the signals for a L15 signal ; except for the L15 Mode. CHECK TS_Out ; Verify that the /TS_Out pin is at 0V. ; i.e. there is an Inc pulse to the DBSC. ; but this comes from the "standard" ; L1 term. Check /SaveStch ; Verify that the saved state of the L15 ; stretch signal is low. Now try to put SetF L15Stch ; it high. SetF /ROM_In SetF ROM_In ; Cycle the ROM clock. Check /SaveStch ; Verify that the saved state of the L15 ; stretch signal is still low. SetF /ROM_In ; End the ROM clock. ; OK now move to L1.5 Mode. And then ; verify that the standard L1 term can ; not set the Increment pulse. SETF D1_In ; Simulate CBus cycle to program the PAL. SETF LD_Reg ; Load a Data 1 value of one. i.e. L15 Mode. SETF /LD_Reg ; Clock it in with a CBus write cycle. SETF RD_Reg ; CBus read of the data register. CHECK L15Mode D1_Out ; Verify that the value of Data 1 is one i.e. SETF /RD_Reg ; verify we are in L15 Mode. End CBus Read. ; Check that the normal Level 1 Mode pure ; L1 trigger does not make an Inc pulse i.e. ; verify that it is disabled by L15 Mode. ; We are in Level 1.5 Mode and for this test ; we will be doing L15 processing. SetF L15Stch ; Set the L15 Stretch i.e. L15 is processing. SetF LtGlSTF ; Set Latched Global Spec Trig Fired Strobe. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF ROM_In ; ROM signal goes active Check /TS_Out ; Verify that the MTG signal is STILL +5V. ; i.e. no DBSC Inc pulse. SetF /ROM_In ; ROM pulse ends CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF /LtGlSTF ; Clear the Latched Spec Trig Fired Strobe. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. ; i.e. Still no pulse. ; OK now let the L1.5 processing end (i.e. ; either the L15 trigger was confirmed or ; else there was a pure L1 trigger). Verify ; that the DBSC receives and Inc pulse. SetF LtGlSTF ; Set Latched Global Spec Trig Fired Strobe. ; i.e. there still is a trigger around SetF /L15Stch ; Clear the L15 Stretch i.e. the L15 ; processing has finished (or never started). CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF ROM_In ; ROM signal goes active Check TS_Out ; Verify that the MTG signal is now 0V. ; i.e. there is a pulse to the DBSC. SetF /ROM_In ; ROM pulse ends CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. SetF /LtGlSTF ; Clear the Latched Spec Trig Fired Strobe. CHECK /TS_Out ; Verify that the /TS_Out pin is at +5v. ; Check for additional Inc pulses SetF ROM_In ; ROM signal goes active Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; ROM pulse ends SetF ROM_In ; ROM signal goes active Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; ROM pulse ends ; OK now Start the L15 processing, Process ; for a couple of beam crossing cycles, let ; the L15 trigger be rejected, and verify ; that there is an Inc pulse generated. ; LtGlSTF and L15Stch will drop at different ; times i.e. on different beam crossings. SetF /LtGlSTF /L15Stch ; Clear the signals SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. ; i.e. both are inactive. SetF LtGlSTF ; Set Latched Global Spec Trig Fired Strobe. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. SetF L15Stch ; Set the L15 Stretch i.e. L15 is processing. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. ; i.e. the output TS is inactive, and ; SaveStretch is active. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. SetF /LtGlSTF ; Clear Latched Global Spec Trig Fired Strobe. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. SetF /L15Stch ; Clear the L15 Stretch i.e. L15 proc ends. SetF ROM_In CHECK TS_Out SaveStch ; Verify that TS is 0V. and SaveStch is 0V. ; A pulse is going out, SaveStch is active. SetF /ROM_In ; Beam Crossing Cycle pulse ends. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. ; i.e. the pulse is over and SaveStch is ; is inactive. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. ; OK now Start the L15 processing, Process ; for a couple of beam crossing cycles, let ; the L15 trigger be rejected, and verify ; that there is an Inc pulse generated. ; LtGlSTF and L15Stch will drop at the same ; time i.e. on the same beam crossing. SetF /LtGlSTF /L15Stch ; Clear the signals SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. ; i.e. both are inactive. SetF LtGlSTF ; Set Latched Global Spec Trig Fired Strobe. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. SetF L15Stch ; Set the L15 Stretch i.e. L15 is processing. CHECK /TS_Out /SaveStch ; Verify that TS and Save Stretch are +5V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. ; i.e. the output TS is inactive, and ; SaveStretch is active. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out SaveStch ; Verify that TS is +5V. and SaveStch is 0V. SetF /LtGlSTF /L15Stch ; Clear Latched Global Spec Trig Fired Strobe. ; Clear the L15 Stretch i.e. L15 proc ends. SetF ROM_In CHECK TS_Out SaveStch ; Verify that TS is 0V. and SaveStch is 0V. ; A pulse is going out, SaveStch is active. SetF /ROM_In ; Beam Crossing Cycle pulse ends. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. ; i.e. the pulse is over and SaveStch is ; is inactive. CHECK /TS_Out /SaveStch ; Verify that TS is +5V. and SaveStch is +5V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. SetF ROM_In Check /TS_Out ; Verify that no pulse is coming out. SetF /ROM_In ; Beam Crossing Cycle pulse. CHECK /TS_Out /SaveStch ; Verify that TS is +5V and SaveStch is +5V. TRACE_OFF ; ; Description of the Skip BX 7 PAL ; ; This circuit uses a 16RA8 type of PAL. There are some special ; connections required to plug this 16RA8 PAL into a Bit PAL socket. ; The following table shows the connections used with this BXSKIP device. ; ; Socket ; Connection ; Pin Signal PAL Pin Signal Special Requirements ; --- ---------- -------------- ---------------------------------- ; ; 1 Load Reg PreLoad Reg Device pin tied high. Socket pin ; pos edge low active tied to device pin number 4. ; ; 2 Data 1 In Data 1 In Socket pin tied to device pin. ; ; 3 Data 2 In Data 2 In Socket pin tied to device pin. ; This input is not used in this design. ; ; 4 Data 3 In /Load_Reg Device pin 5 connected to socket ; pin 1. Load CBUS registers on ; rising edge. Socket pin 4 is not used. ; ; 5 Data 4 In ROM_In Device pin 5 connected to socket pin ; 12. This is the ROM input. Socket ; pin 5 is not used. ; ; 6 Data 5 In /Read_Reg Device pin 6 connected to socket ; pin 11. Enable CBUS register ; outputs while signal is low. ; Socket pin 6 is not used. ; ; 7 Data 6 In Data 6 In Socket pin tied to device pin. ; This input is not used in this design. ; ; 8 Ext-Enb Ext-Enb Socket pin tied to device pin. ; Receives the Latched Global Spec Trig ; Fired signal. ; ; 9 Ext-Bit Ext-Bit Socket pin tied to device pin. ; Receives the L1.5 Stretch signal. ; ; 10 GND Device GND Socket pin tied to device pin. ; Jumper to Device pin 11. ; ; 11 Read Reg. Global Output Device pin tied low. Socket ; Low Active Enable Low Active pin tied to device pin 6. ; ; 12 ROM Bit No_Con Device pin is not connected to socket. ; Socket pin 12 connected to device ; pin 5. ; ; 13 Data 6 Out No_Cn1 Device pin not connected to socket pin ; ; 14 Data 5 Out No_Cn1 Device pin not connected to socket pin ; ; 15 Data 4 Out No_Cn1 Device pin not connected to socket pin ; ; 16 Data 3 Out /Save_Stch Device pin not connected to socket pin ; ; 17 Data 2 Out L15Mode Device pin not connected to socket pin ; ; 18 Data 1 Out D1_Out Socket pin tied to device pin. ; ; 19 Channel Out /TS_Out Socket pin tied to device pin. ; ; 20 Vcc Device Vcc Socket pin tied to device pin. ; Jumper to Device pin 1. ; Detailed Description of the Framework_Main_Timing_Channel_14 PAL ; ; ;Beam x x x x ;Cross ; ------------------- ;LtGlSTF ______________| |___________________________________ ; ; _ _ _ _ ;ROM_Bit _____| |_________________| |_________________| |_________________| |__ ; ; _ ;Increment _______________________| |__________________________________________ ;DBSC ; ; Not in Level 1.5 Mode a Level 1 Trigger Fires ; ; ; ;Beam x x x x ;Cross ; --------------------------------------- ;LtGlSTF ______________| |_______________ ; ; -------------------- ;L15Stch __________________| |_______________________________ ; ; _ _ _ _ ;ROM_Bit _____| |_________________| |_________________| |_________________| |__ ; ; _ ;Increment ___________________________________________| |______________________ ;DBSC ; ; In Level 1.5 Mode and a Level 1.5 Fires ; and it is Confirmed. No pure Level 1 fired. ; ; ; ;Beam x x x x ;Cross ; ------------------- ;LtGlSTF ______________| |___________________________________ ; ; --------------------------------------- ;L15Stch __________________| |___________ ; ; _ _ _ _ ;ROM_Bit _____| |_________________| |_________________| |_________________| |__ ; ; _______ ;Fancy ___________________________________________________________| |__ ;Gate ; _ ;Increment _______________________________________________________________| |__ ;DBSC ; ; In Level 1.5 Mode and NO Pure Level 1 Fires ; but an L1.5 does Fire and it is rejected. ; ; ; ; ; ; +---------+ ; LtGlSTF >------| | This is the "standard" ; | | Start Digitization ; ROM_Bit >------| AND |----------------------+ Number increment pulse ; | | | for use in Level 1 only ; /L15Mode >------| | | mode. L15 is disabled. ; |_________| | ; | ; +---------+ | ; LtGlSTF >------| | This is the | +------+ Increment ; | | increment pulse +------| | pulse to ; /L15Stch >------| | for pure L1 | | the Start ; | AND |-----------------------------| OR |-----------> ; ROM_Bit >------| | Trigs when L15 | | Digitize ; | | is enabled and +---| | Number ; L15Mode >------| | for L15 only | |______| DBSC. ; |_________| trigs that pass. | ; +----------+ ; | ; /LtGlSTF >-------------------------------------+ | Increment ; | | pulse ; | | when L15 ; ROM_Bit >---------------------------------+ | +-------+ | is enabled ; | +---| | | and an L15 ; +-------| | | only fires ; L15Mode >-----------------------------------------| AND |---+ and the ; +---| | L15 is ; | |_______| rejected. ; /L15Stch >-------------------+ | ; | +-------+ | ; +---| | | ; ReSet | AND |-----+ ; /L15Mode >----------+ +---| | This signal is high ; | | |_______| from the time that ; +--------+ | L15Stch falls until ; L15Stch >------| D Q |---+ the end of the ; | | following (the next) ; | | ROM pulse. ; /ROM_Bit >------|CLK /Q | ; |________| ; ; ; ; ; ; ; The STDGNINC PAL has a one bit wide data register that can be loaded and ; read from CBus data bit #1 (the LSB). When a zero is loaded into this ; register then the STDGNINC PAL is in the Level 1 Mode. When a one is ; loaded into this register then the STDGNINC PAL is in the Level 1.5 Mode. ; ; ;