FULL SCALE, STEP SIZE, and GeV vs ADC COUNT ------------------------------------------- 16-JAN-1990 BLS OUTPUT I.E. CTFE DIFF DAC HEX VOLTAGE SEEN OUTPUT HEX CODE EQUIVALENT INPUT VOLTAGE INPUT CODE BY THE ADC FROM THE ADC ENERGY -------------- ---------- ------------ --------------- ---------- 0.000 Volts nn -1.0 Volts 00 0.00 GeV 0.004 -1.0 + 1/256 00 <-> 01 0.125 0.008 -1.0 + 2/256 01 0.25 0.012 -1.0 + 3/256 01 <-> 02 0.375 (2N-1)/256 -1.0+(2N-1)/256 HEX(N-1)<->HEX(N) N/4-1/8 2N/256 -1.0+2N/256 HEX(N) N/4 (2N+1)/256 -1.0+(2N+1)/256 HEX(N)<->HEX(N+1) N/4+1/8 1.000 nn 0.0 80 32.00 1.984 1.0 - 4/256 FE 63.50 1.988 1.0 - 3/256 FE <-> FF 63.625 1.992 1.0 - 2/256 FF, over = 0 63.75 1.996 1.0 - 1/256 FF, over 0 <-> 1 63.875 2.000 nn 1.0 FF, over = 1 64.00 nn = experimentally observed value compensating for CTFE internal offsets step size = 1/4 GeV range = 0 GeV to 63.75 GeV full scale = 63.75 GeV ADC RESISTOR LADDER ADC output when ladder input voltage resistor above ladder step R/2 R OVERRANGE R 255 . . R 3 R 2 R/2 1 0 0 ----- 256*R The LSB is introduced as the unit symbol for the magnitude of the analog resolution of the ADC, and serves as a reference unit to express the magnitude of other analog quantities of the same converter, especially of analog errors in multiples or submultiples of LSB. 1 LSB = Full Scale Range / ( 2**n - 1 ) CONVERSION ERRORS Even an ideal ADC will show a quantization uncertainty of +/- 1/2 LSB. If N is the digital output value from the ADC the input voltage to the ADC was distant from the nominal value of N * LSB by less than 1/2 LSB, that is the input was (N +/- 1/2) LSB. Besides this inherent uncertainty tied to the principal of digitization, the imperfections of the real component will further lower the accuracy of the reading. The DNL and INL are two measurements of the performance of an ADC: The maximum Differential Nonlinearity (DNL) guaranteed for our flash ADCs is +/- 1 LSB. This is the maximum departure of a step length from its ideal size of exactly 1 LSB. Each step length is thus only guaranteed to be between 0 and 2 LSB. The Differential Nonlinearity is caused by each resistor on the ladder not being exactly 1/256 of the total resistance of the ladder and/or by the offset input voltage of the comparator. The maximum Integral Nonlinearity (INL) guaranteed for our ADCs is +/- 1 LSB. This is the maximum departure from the straight line joining the analog end-points. The Integral Nonlinearity is (partially) caused by the cumulative sum of the resistors beneath the Nth comparator not being (N-1/2)/256 of the total resistance of the ladder. The INL is only measured at some discrete points of the quantization function; either the transition points or the midpoints of each step. unfortunately, it is not clear which definition is used by Motorola. Assuming that we can perfectly know our offsets (see next paragraph for corrective term), then we can estimate the worst case of uncertainty: 1) If the INL specification on the data sheets of the MC 10319 refers to the transition points of each digitization step, then we can add the INL to the quantization error of 1/2 LSB for a total of +/- 1.5 LSB. 4-| ---------ideal | | 3-| +.......----+----.......+ worst case | | <---> 1/2 LSB digitization 2-| --------- . <-------> 1 LSB worst case step transition (INL) | | <-----------> 1-| --------- . 1.5 LSB total | | . 0-|---+---|---|---|---|---|---|---|---|---|---|-----> EM , HD 1/8 1/4 3/8 1/2 GeV Our conversion uncertainty would then be as high as +/- 3/2 * 1/4 = 0.375 GeV 2) If the INL was measured at the midpoint of each step, then we must add INL and DNL, for a total of +/- 2 LSB. 4-| ---------ideal | | 3-| +.......+...----+----...+.......+ worst case | | <-------> 1 LSB worst case step center (INL) 2-| --------- <-------+-------> 2 LSB worst case step size (DNL) | | <---------------> 1-| --------- . 2.0 LSB total | | . 0-|---+---|---|---|---|---|---|---|---|---|---|-----> EM , HD 1/8 1/4 3/8 1/2 GeV Our conversion uncertainty would then be as high as +/- 2 * 1/4 = 0.5 GeV OFFSET AND DAC BYTE A byte is downloaded into the DAC to compensate for the offset of the receiving op-amp. The output voltage from the DAC is added to the BLS differential voltage and added to a fixed voltage reference and then fed to the ADC. One least count of the DAC is only one third of one ADC least count. This sets the achievable accuracy for centering the ADC steps to the ideal value. The centering of the ADC steps is thus only possible at 1/3 * 1/4 = 1/12 Gev or +/- 1/24 GeV. Additionally, the relative error of our DAC is +/- 1/2 LSB, which translates into +/- 1/2 * 1/3 * 1/4 = +/- 1/24 GeV. If we use a linear fit technique on the ADC versus DAC data to figure out the desirable DAC offset code, then we should add the contributions from these two sources of error. Also note that a different definition of this offset could allow a different centering of the ADC steps. For example, one could change the meaning of an ADC output of 1 from [-0.125 GeV,+0.125 GeV] to [0 GeV,+0.25 GeV] thus making an ADC count N mean an energy within [N/4,(N+1)/4]. SUMMARY In our case, an ADC output of N can be considered as an input energy of: (see above for the 2 possible interpretations of the specifications) +--------------+ 1) |N/4 +/- .5 GeV| 3/8 + 1/12 + 1/24 = 0.5 +--------------+ +----------------+ 2) |N/4 +/- .625 GeV| 1/2 + 1/12 + 1/24 = 0.625 +----------------+ EXPERIMENTALLY During the diagnostics of the front end of the CTFE cards, measurements are made that are related to this uncertainty. An important limitation to this experimental evaluation is that only the lower third of the range of the ADC is explored. The DAC is ramped up and the output of the ADC is recorded. Then a straight line is fitted to the discrete points. The slope of the line is 1/3, the intercept to the x-axis lays between 1 and 20. Parenthesis: this intercept is the value of the DAC byte that must be downloaded to compensate for our internal offsets and prevent rectifier effect. A larger value can be loaded for a positive zero energy response and be able to "see" negative energies. The program finds the worst deviation of the ADC response with respect to the straight line. If the ADC and DAC were perfect, then 3 steps of DAC would exactly cover one step of the ADC. This worst case would be equal to the slope, that is 1/3. | . 2-| + + + | . | . | . 1-| + + + | . | . | 0 |---|---|---|---|---|---|---|---|---|---|---|-----> DAC byte 4 5 6 7 8 9 10 The experimental numbers have always been smaller than 0.8 | . -| . | . | | . | 0.8 | . | -| .-----------+ | . 0.8 * 3 = 2.4 | . | 0 |---|---|---|---|---|---|---|---|---|---|---|-----> DAC byte 4 5 6 7 8 9 10 The program also finds the smallest and largest number of DAC steps that gave a same ADC output. These extremes have always been 1 and 4. The DNL is "probably" only of the order +/- 1/3 LSB ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | 4-| +---+---+ | | ADC_ZERESP (EM) = 0 3-| +---+---+ ADC_ZERESP (HD) = 0 | | 2-| +---+---+ | | 1-| +---+---+ | | 0-|---+ | | | | |---|---|---|---|---|---|---|---|-----------------> EM , HD 0 1/8 1/4 1/2 3/4 1 GeV | 4-| +-------+-------+ +1/8<=EM <=+3/8 COUNT=1 | +1/8<= HD<=+3/8 COUNT=1 3-| +-------+-------+ +1/4<=EM+HD<=+3/4 COUNT=2 | or 2-|.......+-------+-------+ -1/8<=EM <=+1/8 COUNT=0 | +3/8<= HD<=+5/8 COUNT=2 1-|-------+-------+ +1/4<=EM+HD<=+3/4 COUNT=2 | 0-|-------+ | | | | |---|---|---|---|---|---|---|---|-----------------> EM + HD 0 1/8 1/4 1/2 3/4 1 GeV | 3-| +-----------+-----------+ | 2-| +-----------+-----------+ | 5/8 1-|.......+-----------+-----------+ | 1/8 0-|---+-----------+ | | | | |---|---|---|---|---|---|---|---|-----------------> ( EM + HD ) / 2 0 1/8 1/4 1/2 3/4 1 GeV ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | 4-| +---+---+ | | ADC_ZERESP (EM) = 1 3-| +---+---+ ADC_ZERESP (HD) = 1 | | 2-| +---+---+ | | 1-| +---+---+ | | 0-|---+ | | | | | | |---|---|---|---|---|---|---|---|---|---|---------> EM , HD -1/4 0 1/8 1/4 1/2 3/4 1 GeV | 4-| +-------+-------+ -1/8<=EM <=+1/8 COUNT=1 | -1/8<= HD<=+1/8 COUNT=1 3-| +-------+-------+ -1/4<=EM+HD<=+1/4 COUNT=2 | or 2-|.......+-------+-------+ -3/8<=EM <=-1/8 COUNT=0 | +1/8<= HD<=+3/8 COUNT=2 1-|-------+-------+ -1/4<=EM+HD<=+1/4 COUNT=2 | 0-|-------+ | | | | | | | | |---|---|---|---|---|---|---|---|---|---|---|---|-> EM + HD -1/2 -1/4 0 1/8 1/4 1/2 3/4 1 GeV | 3-| +-----------+-----------+ | 2-| +-----------+-----------+ | 1/8 1-|.......+-----------+-----------+ | -3/8 0-|---+-----------+ | | | | | | | |---|---|---|---|---|---|---|---|---|---|---|---|-> ( EM + HD ) / 2 -1/2 -1/4 0 1/8 1/4 1/2 3/4 1 GeV ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | 3-| +---+---+ | | ADC_ZERESP (EM) = 1 2-| +---+---+ ADC_ZERESP (HD) = 0 | | 1-| +---+---+ | | 0-|---+ | | | | | | |---|---|---|---|---|---|---|---|---|---|---------> EM -1/4 0 1/8 1/4 1/2 3/4 1 GeV |---|---|---|---|---|---|---|---|---|---|---------> HD 0 1/8 1/4 1/2 3/4 1 GeV | 4-| +-------+-------+ -1/8<=EM <=+1/8 COUNT=1 | +1/8<= HD<=+3/8 COUNT=1 3-| +-------+-------+ 0 <=EM+HD<=+1/2 COUNT=2 | or 2-|.......+-------+-------+ -3/8<=EM <=-1/8 COUNT=0 | +3/8<= HD<=+5/8 COUNT=2 1-|-------+-------+ 0 <=EM+HD<=+1/2 COUNT=2 | 0-|-------+ | | | | | |---|---|---|---|---|---|---|---|---|---|---------> EM + HD -1/4 0 1/8 1/4 1/2 3/4 1 GeV | 3-| +-----------+-----------+ | 2-| +-----------+-----------+ | 3/8 1-|.......+-----------+-----------+ | -1/8 0-|---+-----------+ | | | | | |---|---|---|---|---|---|---|---|---|---|---------> ( EM + HD ) / 2 -1/4 0 1/8 1/4 1/2 3/4 1 GeV ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~