{ *************************************************************************** } MODULE mod_handle_l15ct ; { Created 4-MAY-1994 MICHIGAN STATE UNIVERSITY, TRIGGER CONTROL SOFTWARE } { *************************************************************************** } INCLUDE mod_common_global_flags, mod_handle_zrl, mod_def_hardware_tables, mod_handle_tracing, $KERNELMSG ; { from ELN$:RTLOBJECT.OLB } { *************************************************************************** } EXPORT Header_Word_Universal_Param, {TYPE header word for universal parameter block} Universal_Parameter_Block, {TYPE universal parameter block data struct } Block_Type_Code, {Enumerated TYPE for frame, Local, global } Header_Word_Term_Param, {TYPE header word for parameter block } Frame_Parameter_Block, {TYPE Frame code parameter block } Local_Parameter_Block, {TYPE Local DSP parameter block } Global_Parameter_Block, {TYPE GLobal DSP parameter block } L15CT_Relative_Term, {Enumerated TYPE for crate term number } RefSet_segment, {TYPE Local DSP segement of Reference Set } Loc_DSP_RefSet_Block, {TYPE Local DSP Reference Set Block } Loc_DSP_eta, {Enumerated TYPE eta ranges for local DSP } RefSet_Block, {TYPE Block of Local DSP Reference Set Blocks } L15CT_VME_Params_Map, {TYPE full map of L1.5 CT VME parameters } L15CT_Crate_ID, {Enumerated TYPE Crate 0/1 } DSP_ID, {Enumerated TYPE DSPs in eta order, Global Last} L15CT_Params, {TYPE array of crate 0 and 1 VME parameters } L15CT_Term_Mask, {TYPE mask of one crate of L1.5 Cal Trig Terms } SpTrg_use_L15CT_Terms, {ARRAY for programming Term Select P2 card } Term_RefSet_Type, {ARRAY for noting the EM/Tot Type of a Ref Set } Hydra_A_DPM, {ARRAY of pointers to Hydra Dual Port Memory } Hydra_B_DPM, {ARRAY of pointers to Hydra Dual Port Memory } Hydra_C_DPM, {ARRAY of pointers to Hydra Dual Port Memory } CPU_68k_DPM, {ARRAY of pointers to 68k Dual Port Memory } Init_L15CT_Progr, {PROCEDURE call at boot and initialize } Copy_Params_to_VME, {PROCEDURE Load already prepared parameter Map } Prepare_Params_to_VME, {PROCEDURE Add final contribution to param map } Halt_L15CT_Crate, {PROCEDURE Halt a Level 1.5 CT Crate } Load_L15CT_Code, {PROCEDURE Load Code in a crate of L1.5 CT } Start_L15CT, {PROCEDURE Tell L1.5 CT to read params and go } Conv_VAX_Float_to_DSP, {FUNCTION Convert Float from VAX to DSP } { Input REAL, ouput INTEGER } Check_Term_Select, {PROCEDURE check Term Select card programming } Check_DSP_to_TCC_Status, {PROCEDURE read DSP to TCC status } Check_DSP_to_EC_Status, {PROCEDURE read DSP to 68k status } Check_Wake_Up_Word, {PROCEDURE read Wake Up and Transfer words } Check_68k_Status, {PROCEDURE read 68k to TCC status } Read_68k_Errors, {PROCEDURE read 68k run-time error counters } Read_68k_Flags, {PROCEDURE read 68k flags } Read_68K_Counts, {PROCEDURE read 68k run loop counters } Test_VME_conX ; {PROCEDURE Speed and data transfer tests to VME} { *************************************************************************** } IMPORT status_type, {from module MOD_COMMON_GLOBAL_FLAGS } ok, io_failure, error_found, {from module MOD_COMMON_GLOBAL_FLAGS } get_host_address, {from module MOD_COMMON_GLOBAL_FLAGS } { trace_info, trace_warn, trace_error,{from module MOD_HANDLE_TRACING } { inline_tracing, {from module MOD_HANDLE_TRACING } { io_tracing, db_tracing, ON, {from module MOD_HANDLE_TRACING } handle_trc_sys, {from module MOD_HANDLE_TRACING } handle_trc_inf, {from module MOD_HANDLE_TRACING } handle_trc_sta, {from module MOD_HANDLE_TRACING } handle_trc_err, {from module MOD_HANDLE_TRACING } VME_mapped_region, {from module MOD_HANDLE_ZRL } pVBA_Mapped_page, {from module MOD_HANDLE_PVBA } Hydra_A_Page_DPM, {from module MOD_HANDLE_PVBA } Hydra_A_Page_Ctrl, {from module MOD_HANDLE_PVBA } Hydra_B_Page_DPM, {from module MOD_HANDLE_PVBA } Hydra_B_Page_Ctrl, {from module MOD_HANDLE_PVBA } Hydra_C_Page_DPM, {from module MOD_HANDLE_PVBA } Hydra_C_Page_Ctrl, {from module MOD_HANDLE_PVBA } CPU_68k_page_DPM, {from module MOD_HANDLE_PVBA } CPU_68k_page_Ctrl, {from module MOD_HANDLE_PVBA } Ironics_Page, {from module MOD_HANDLE_PVBA } longwords_of_A24_scratch, {from module MOD_HANDLE_PVBA } scratch_A24_long_offset, {from module MOD_HANDLE_PVBA } scratch_A24_page, {from module MOD_HANDLE_PVBA } bytes_of_A16_scratch, {from module MOD_HANDLE_PVBA } scratch_A16_byte_offset, {from module MOD_HANDLE_PVBA } scratch_A16_page, {from module MOD_HANDLE_PVBA } {phi_value,}p_1, p_32, {from module MOD_DEF_HARDWARE_TABLES } {relative_eta,}rele_0,{rele_1, rele_2,}rele_3, threshold_comparison_type, {from module MOD_DEF_HARDWARE_TABLES } EMEt_cmp,{TOTEt_cmp,} {from module MOD_DEF_HARDWARE_TABLES } KER$_DEBUG_SIGNAL ; {from module $KERNELMSG } { *************************************************************************** } { *************************************************************************** } %INCLUDE 'SITE_DEPENDENT.CST/LIST' %INCLUDE 'L15CT_VME_MAP.TYP/LIST' TYPE { byte mask of l1.5 Cal Trig Crate Terms } L15CT_Term_Mask = PACKED ARRAY [Term_0..Term_7] OF bit ; Term_Select_Address = [LONG] PACKED RECORD CASE INTEGER OF 0 : ( SpTrg : PACKED ARRAY [0..15] OF bit ) ; 1 : ( Low_Byte : byte ; High_Byte : byte ; unused : word ) ; END ; VAR host_name : VARYING_STRING(10) := '' ; L15CT_Params : ARRAY [Crate_0..Crate_1] OF L15CT_VME_Params_Map ; Term_RefSet_Type : ARRAY [Crate_0..Crate_1,Term_0..Term_7] OF threshold_comparison_type ; tag : VARYING_STRING(8) := '15C/HDL%' ; addresses_loaded : BOOLEAN := FALSE ; Hydra_A_DPM : ARRAY [Crate_0..Crate_1] OF ^DPM_Map_for_all_DSP_and_68k ; Hydra_A_Ctrl : ARRAY [Crate_0..Crate_1] OF ^Hydra_II_Map_Ctrl ; Hydra_B_DPM : ARRAY [Crate_0..Crate_1] OF ^DPM_Map_for_all_DSP_and_68k ; Hydra_B_Ctrl : ARRAY [Crate_0..Crate_1] OF ^Hydra_II_Map_Ctrl ; Hydra_C_DPM : ARRAY [Crate_0..Crate_1] OF ^DPM_Map_for_all_DSP_and_68k ; Hydra_C_Ctrl : ARRAY [Crate_0..Crate_1] OF ^Hydra_II_Map_Ctrl ; CPU_68k_DPM : ARRAY [Crate_0..Crate_1] OF ^DPM_Map_for_all_DSP_and_68k ; CPU_68k_Ctrl : ARRAY [Crate_0..Crate_1] OF ^MVME135_68k_Ctrl_Map ; Ironics : ARRAY [Crate_0..Crate_1] OF ^Ironics_Map ; SpTrg_use_L15CT_Terms: ARRAY [Crate_0..Crate_1,0..31] OF L15CT_Term_Mask ; CONST TS_MUX_sel_comp = %X01 ; TS_MUX_sel_input = %X00 ; TS_Write_Enable_not = %X02 ; TS_Write_Enable = %X00 ; TS_Output_Enable_not = %X04 ; TS_Output_Enable = %X00 ; TS_Comp_Clock_High = %X08 ; TS_Comp_Clock_Low = %X00 ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Init_L15CT_Progr ; TYPE big_array = ARRAY [1 .. 8192] OF INTEGER ; VAR p_L15CT_Params : ^big_array ; size_L15CT_Params : INTEGER ; Word_Num : INTEGER ; BEGIN {connect card pointers to VME Mapped space } IF ( addresses_loaded = FALSE ) THEN get_addresses_of_l15ct ; Halt_L15CT_Crate ; { **************************************************************************** } { *** Erase all data structures for L1.5 CT programming *** } { **************************************************************************** } {find base address of Paramter block} p_L15CT_Params::^ANYTYPE := ADDRESS ( L15CT_Params[Crate_0] ) ; {find size in longword of Paramter block} size_L15CT_Params := SIZE ( L15CT_VME_Params_Map ) DIV 4 ; {overwrite it all with FF} FOR Word_Num := 1 TO size_L15CT_Params DO p_L15CT_Params^[Word_Num] := %XFFFFFFFF ; {clear the mask of sptrg versus l1.5 Ct Term} SpTrg_use_L15CT_Terms[Crate_0] := ZERO ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Copy_Params_to_VME ( VAR status : status_type ) ; VAR DPM_Word : INTEGER ; BEGIN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' Copying Params to L1.5 CT Crate ' ) ; Program_Term_Select ; Check_Term_Select ; { **************************************************************************** } { *** First paint FF's over the 32k communication region of all DSPs + 68k *** } { **************************************************************************** } FOR DPM_Word := 0 TO 8191 DO BEGIN Hydra_A_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; Hydra_B_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; Hydra_C_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; CPU_68k_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; END ; { **************************************************************************** } { *** Now copy the Parameters to all Hydra cards and 68k *** } { **************************************************************************** } Hydra_A_DPM[Crate_0]^.Copy_Params := L15CT_Params[Crate_0] ; Hydra_B_DPM[Crate_0]^.Copy_Params := L15CT_Params[Crate_0] ; Hydra_C_DPM[Crate_0]^.Copy_Params := L15CT_Params[Crate_0] ; CPU_68k_DPM[Crate_0]^.Copy_Params := L15CT_Params[Crate_0] ; { **************************************************************************** } { *** Load Steve's Parameters *** } { **************************************************************************** } { { Read_and_Transfer_Executable ( FILE_TYPE := 'L1.5 CT Params', { FILENAME := '46.190::HEPE:[TRIGGER.TRG_C40' { + '.FIRST_RELEASE.EXECUTABLES]' { + 'PARAM_05.BLX', { STATUS := status ) ; } END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Prepare_Params_to_VME ( VAR status : status_type ) ; VAR Term_Num : L15CT_Relative_Term ; SpTrg_Num : INTEGER ; Num_Terms : INTEGER ; BEGIN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' Preparing Params for L1.5 CT Crate ' ) ; { **************************************************************************** } { *** Add information not directly written during the COOR messages *** } { **************************************************************************** } Num_Terms := 0 ; FOR Term_Num := Term_0 TO Term_7 DO BEGIN IF ( L15CT_Params[Crate_0].Local[Term_Num].Header::INTEGER <> %XFFFFFFFF ) THEN BEGIN Num_Terms := Num_Terms + 1 ; IF ( Term_RefSet_Type[Crate_0,Term_Num] = EMEt_cmp ) THEN L15CT_Params[Crate_0].Local[Term_Num].Header.RefSet_Type := %X00 ELSE L15CT_Params[Crate_0].Local[Term_Num].Header.RefSet_Type := %XFF ; FOR SpTrg_Num := 0 TO 31 DO L15CT_Params[Crate_0].Frame[Term_Num].SpTrg_Mapped[SpTrg_Num] := SpTrg_use_L15CT_Terms[Crate_0,SpTrg_Num,Term_Num] ; END ; END ; {Fill the universal parameters} L15CT_Params[Crate_0].Universal := ZERO ; L15CT_Params[Crate_0].Universal.Header.Map_Version_Num := 1 ; L15CT_Params[Crate_0].Universal.Header.Map_Rev_Num := 1 ; L15CT_Params[Crate_0].Universal.Header.Crate_ID := 0 ; { This is how many terms were defined by COOR } L15CT_Params[Crate_0].Universal.Num_Terms := Num_Terms ; { no other universal parameters} L15CT_Params[Crate_0].Universal.Num_Params := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Program_Term_Select ; {following the instructions from} { TRGHARD:[TERM_SELECT_P2]TERM_SELECT_P2_CARD_DESCRIPTION.TXT} VAR SpTrg_Num : INTEGER ; SpTrg_Mask : Term_Select_Address ; address : INTEGER ; Term_Mask : byte ; BEGIN { **** 1. Generate a 64k data set for the card as desired.} { ---------> we will do this on the fly} { **** 2. Set Comp_Clk low, /OE high, /WE high, and MUX_SEL high.} {remember: the port inverts the data written} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable_not + TS_Comp_Clock_Low ) ; FOR address := 0 TO 65535 DO BEGIN SpTrg_Mask::INTEGER := address ; Term_Mask := ZERO ; FOR SpTrg_Num := 0 TO 15 DO BEGIN {OR all the L1.5 CT Term Masks for all sptrg num set in the address } IF ( SpTrg_Mask.SpTrg[SpTrg_Num] = 1 ) THEN Term_Mask::BOOLEAN := Term_Mask::BOOLEAN OR SpTrg_use_L15CT_Terms[Crate_0,SpTrg_Num]::BOOLEAN ; END ; { IF ( Term_Mask <> 0 ) { THEN BEGIN { handle_trc_inf ( TAG := tag, { MESSAGE := ' Progr ' + BIN(Term_Mask,8,8) { + ' @ %X' + BIN(address,16,16) ) ; { END ; } { **** 3. Write the least significant 8 bits of the address to Port 2.} {remember: the port inverts the data written} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Lo].data_byte := 255 - SpTrg_Mask.Low_Byte ; { **** 4. Write the most significant 8 bits to Port 3.} {remember: the port inverts the data written} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Hi].data_byte := 255 - SpTrg_Mask.High_Byte; { **** 5. Write the 8 bit L15 algorithm mask to Port 4.} {remember: the port inverts the data written} Term_Mask := 255 - Term_Mask ; Ironics[Crate_0]^.Term_Select[Port_TS_Data].data_byte := Term_Mask ; { **** 6. Set Comp_Clk high.} {(This latches the Ironics generated address from Ports 2 and 3).} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable_not + TS_Comp_Clock_High ) ; { **** 7. Set Comp_Clk low and /WE low.} {(This writes the L15 algorithm 8 bit mask to the SRAM).} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable + TS_Output_Enable_not + TS_Comp_Clock_Low ) ; { **** 8. Set /WE high.} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable_not + TS_Comp_Clock_Low ) ; END ; { **** 9. Repeat steps 3:8 until finished.} { **** 10. Set the TS-P2PB in "real data" mode.} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_input + TS_Write_Enable_not + TS_Output_Enable + TS_Comp_Clock_Low ) ; {write zeroes to all Ironics ports to make all drivers let go and drift high} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Lo].data_byte := 0 ; Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Hi].data_byte := 0 ; Ironics[Crate_0]^.Term_Select[Port_TS_Data].data_byte := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Check_Term_Select ; {following the instructions from} { TRGHARD:[TERM_SELECT_P2]TERM_SELECT_P2_CARD_DESCRIPTION.TXT} VAR SpTrg_Num : INTEGER ; SpTrg_Mask : Term_Select_Address ; address : INTEGER ; Term_Mask : byte ; data : byte ; BEGIN {first, write zero to the input port} {so that the output driver can let go and drift high} Ironics[Crate_0]^.Term_Select[Port_TS_Data].data_byte := 0 ; { **** 1. Generate a 64k data set for the card as desired.} { ---------> we will do this on the fly} { **** 2. Set Comp_Clk low, /OE low, /WE high, and MUX_SEL high.} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable + TS_Comp_Clock_Low ) ; FOR address := 0 TO 65535 DO BEGIN SpTrg_Mask::INTEGER := address ; Term_Mask := ZERO ; FOR SpTrg_Num := 0 TO 15 DO BEGIN {OR all the L1.5 CT Term Masks for all sptrg num set in the address } IF ( SpTrg_Mask.SpTrg[SpTrg_Num] = 1 ) THEN Term_Mask::BOOLEAN := Term_Mask::BOOLEAN OR SpTrg_use_L15CT_Terms[Crate_0,SpTrg_Num]::BOOLEAN ; END ; { **** 3. Write the least significant 8 bits of the address to Port 2.} {remember: the port inverts the data written} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Lo].data_byte := 255 - SpTrg_Mask.Low_Byte ; { **** 4. Write the most significant 8 bits to Port 3.} {remember: the port inverts the data written} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Hi].data_byte := 255 - SpTrg_Mask.High_Byte; { **** 5. Set Comp_Clk high.} {(This latches the Ironics generated address from Ports 2 and 3).} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable + TS_Comp_Clock_High ) ; { **** 6. Set Comp_Clk low} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_comp + TS_Write_Enable_not + TS_Output_Enable + TS_Comp_Clock_Low ) ; { **** 7. Read 8 bit L15 algorithm mask to Port 4.} {remember: the port only inverts the data on output, not on input} data := Ironics[Crate_0]^.Term_Select[Port_TS_Data].data_byte ; IF ( data <> Term_Mask ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Error Verifying Term Select RAM, ' + CONVERT(STRING,Crate_0) + ' read ' + BIN(data) + ' instead of ' + BIN(Term_Mask,8,8) + ' @ %X' + HEX(address,8,8) ) ; END ; END ; { **** 8. Repeat steps 3:8 until finished.} { **** 9. Set the TS-P2PB in "real data" mode.} Ironics[Crate_0]^.Term_Select[Port_TS_Ctrl].data_byte := 255 - ( TS_MUX_sel_input + TS_Write_Enable_not + TS_Output_Enable + TS_Comp_Clock_Low ) ; {write zeroes to all Ironics ports to make all drivers let go and drift high} Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Lo].data_byte := 0 ; Ironics[Crate_0]^.Term_Select[Port_TS_Addr_Hi].data_byte := 0 ; Ironics[Crate_0]^.Term_Select[Port_TS_Data].data_byte := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Start_L15CT ( VAR status : status_type ) ; CONST set_DSP_Interrupt = %X22 ; Clear_DSP_Interrupt = %X04 ; set_68k_SIG_LP_Interrupt = %XFF ; VAR step_status : status_type ; BEGIN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' Now Starting L1.5 CT Crate ' ) ; { **************************************************************************** } { *** kick Local DSP A1 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP A1 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Set_DSP_Interrupt ; Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP A2 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP A2 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Set_DSP_Interrupt ; Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP A3 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP A3 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Set_DSP_Interrupt ; Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP A4 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP A4 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Set_DSP_Interrupt ; Hydra_A_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP B1 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP B1 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Set_DSP_Interrupt ; Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP B3 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP B3 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Set_DSP_Interrupt ; Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP B4 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP B4 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Set_DSP_Interrupt ; Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP C1 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP C1 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Set_DSP_Interrupt ; Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_1] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP C2 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP C2 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Set_DSP_Interrupt ; Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP C3 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP C3 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Set_DSP_Interrupt ; Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_3] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Local DSP C4 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Local DSP C4 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Set_DSP_Interrupt ; Hydra_C_Ctrl[Crate_0]^.Intr_Ctrl[DSP_4] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick Global DSP B2 *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Tell Global DSP B2 to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Set_DSP_Interrupt ; Hydra_B_Ctrl[Crate_0]^.Intr_Ctrl[DSP_2] := Clear_DSP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} Check_DSP_to_TCC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := GDSP_B2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_DSP_to_EC_Status ( Hydra := Hydra_B_DPM[Crate_0], DSP := GDSP_B2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** kick 68k *** } { **************************************************************************** } handle_trc_inf ( TAG := tag, MESSAGE := ' Tell 68k to check its parameters' ) ; { send Interrupt to ask the DSP to load and check its parameters} { the 68k will clear this level sensitive signal } { we know the job was done from the status code returned } CPU_68k_Ctrl[Crate_0]^.SIG_LP := set_68k_SIG_LP_Interrupt ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for 68k react} Check_68k_Status ( CPU_68k := CPU_68k_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** read Wake Up Words, 1 Local WUW per Hydra + 1 Global WUW on Hydra B *** } { **************************************************************************** } Check_Wake_Up_Word ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_Wake_Up_Word ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_Wake_Up_Word ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; Check_Wake_Up_Word ( Hydra := Hydra_B_DPM[Crate_0], DSP := GDSP_B2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; quit_Start_L15CT: END ; { *************************************************************************** } PROCEDURE Halt_L15CT_Crate ( VAR status :[OPTIONAL] status_type ) ; CONST set_68k_SIG_HP_Interrupt = %XFF ; halt_DSP_and_sel_DP_Mem_boot = %X00000010 ; {halt the DSP } {and specify Dual Port Memory } {as program source } VAR step_status : status_type ; BEGIN { **************************************************************************** } { *** Interrupt 68k to get it "parked" *** } { **************************************************************************** } handle_trc_inf ( TAG := tag, MESSAGE := ' Park 68k to prepare for DSP code downloading ' ) ; { send Interrupt to ask the DSP to get out of the way} { the 68k will clear this level sensitive signal } { we know the job was done from the acknowledgement returned } CPU_68k_Ctrl[Crate_0]^.SIG_HP := set_68k_SIG_HP_Interrupt ; WAIT_ANY ( TIME := -5000000 ) ; {wait 0.5 s for DSP to react} check_68k_acknowledge ( CPU_68k := CPU_68k_DPM[Crate_0], STATUS := step_status ) ; IF PRESENT (status) THEN status := step_status ; { **************************************************************************** } { *** Read the 68k error counters and software flags, before they get erased * } { **************************************************************************** } Read_68k_Errors ( CPU_68k := CPU_68k_DPM[Crate_0] ) ; Read_68k_Flags ( CPU_68k := CPU_68k_DPM[Crate_0] ) ; Read_68k_Counts ( CPU_68k := CPU_68k_DPM[Crate_0] ) ; { **************************************************************************** } { *** Stop/Reset all DSP's and get them ready to receive new code **** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Put all DSPs in Reset, ready for code download ' ) ; Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := halt_DSP_and_sel_DP_Mem_boot ; Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := halt_DSP_and_sel_DP_Mem_boot ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Load_L15CT_Code ( directory : VARYING_STRING(55) ; VAR status : status_type ) ; CONST boot_from_DP_Mem = %X00000030 ; {bring the DSP out of its RESET state } {and begin loading code from the base } {of the Dual Port Memory. } TYPE big_array = ARRAY [1 .. 8192] OF INTEGER ; VAR step_status : status_type ; dir_name : VARYING_STRING(80) ; { (host=8) +(account=17) +(dir=55) } p_L15CT_Params : ^big_array ; size_L15CT_Params : INTEGER ; Word_Num : INTEGER ; DPM_Word : INTEGER ; BEGIN status := ok ; IF ( directory = 'FROM_LOCAL_DISK' ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Loading L1.5 CT EXEs' + ' from Local Disk Directory ' + local_dir_DSP_executables ) ; dir_name := local_dir_DSP_executables ; END ELSE BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Loading L1.5 CT EXEs from ' + directory ) ; {incorporate the node name and user authorization} IF ( host_name = '' ) THEN host_name := get_host_address ; dir_name := host_name + '"TRGUSER TRGGER"::' + directory ; END ; { **************************************************************************** } { *** First paint FF's over the 32k communication region of all DSPs + 68k *** } { **************************************************************************** } FOR DPM_Word := 0 TO 8191 DO BEGIN Hydra_A_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; Hydra_B_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; Hydra_C_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; CPU_68k_DPM[Crate_0]^.Dual_Port_Mem[DPM_Word] := %XFFFFFFFF ; END ; { **************************************************************************** } { *** Load Local DSP A1 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP A1 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_A1.BLX', HYDRA := Hydra_A_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP A2 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP A2 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_A2.BLX', HYDRA := Hydra_A_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP A3 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP A3 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_A3.BLX', HYDRA := Hydra_A_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP A4 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP A4 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_A4.BLX', HYDRA := Hydra_A_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_A_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_A_DPM[Crate_0], DSP := LDSP_A4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP B1 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP B1 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_B1.BLX', HYDRA := Hydra_B_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP B3 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP B3 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_B3.BLX', HYDRA := Hydra_B_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP B4 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP B4 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_B4.BLX', HYDRA := Hydra_B_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_B_DPM[Crate_0], DSP := LDSP_B4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP C1 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP C1 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_C1.BLX', HYDRA := Hydra_C_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_1] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C1, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP C2 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP C2 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_C2.BLX', HYDRA := Hydra_C_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP C3 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP C3 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_C3.BLX', HYDRA := Hydra_C_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_3] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C3, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Local DSP C4 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Loc DSP C4 Exe', DIRNAME := dir_name, FILENAME := 'LOCAL_C4.BLX', HYDRA := Hydra_C_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_C_Ctrl[Crate_0]^.Boot_Ctrl[DSP_4] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_C_DPM[Crate_0], DSP := LDSP_C4, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Load Global DSP B2 *** } { **************************************************************************** } Read_and_Transfer_Executable ( FILE_TYPE := 'Glob DSP Exe', DIRNAME := dir_name, FILENAME := 'GLOBAL.BLX', HYDRA := Hydra_B_DPM[Crate_0], STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; {release DSP so that it boots from Dual Port Memory} Hydra_B_Ctrl[Crate_0]^.Boot_Ctrl[DSP_2] := boot_from_DP_Mem ; WAIT_ANY ( TIME := -1000000 ) ; {wait 0.1 s for DSP to react} check_DSP_booted ( Hydra := Hydra_B_DPM[Crate_0], DSP := GDSP_B2, STATUS := step_status ) ; IF ( step_status <> ok ) THEN status := step_status ; { **************************************************************************** } { *** Erase all data structures for L1.5 CT programming *** } { **************************************************************************** } handle_trc_sys ( TAG := tag, MESSAGE := ' Erasing all old L1.5 CT Programming Info (FF) ' ) ; {find base address of Paramter block} p_L15CT_Params::^ANYTYPE := ADDRESS ( L15CT_Params[Crate_0] ) ; {find size in longword of Paramter block} size_L15CT_Params := SIZE ( L15CT_VME_Params_Map ) DIV 4 ; {overwrite it all with FF} FOR Word_Num := 1 TO size_L15CT_Params DO p_L15CT_Params^[Word_Num] := %XFFFFFFFF ; {clear the mask of sptrg versus l1.5 Ct Term} SpTrg_use_L15CT_Terms[Crate_0] := ZERO ; quit_Load_L15CT_Code: END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Read_and_Transfer_Executable ( File_type : VARYING_STRING(16) ; dirname : VARYING_STRING(80) ; filename : VARYING_STRING(20) ; Hydra :^DPM_Map_for_all_DSP_and_68k ; VAR status : status_type ) ; TYPE nibble = [BIT(4)] 0..15 ; int_by_nibble = PACKED ARRAY [0..7] OF nibble ; VAR record_num : INTEGER ; word_num : INTEGER ; str_buffer : STRING(8) ; int_buffer : int_by_nibble ; nib_num : INTEGER ; int_status : INTEGER ; executable : FILE OF VARYING_STRING(72) ; BEGIN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' Opening ' + File_type + ' : ' + filename ) ; OPEN ( executable, FILE_NAME := dirname + filename, HISTORY := HISTORY$READONLY, BUFFERING := TRUE, BUFFERSIZE := 4096, STATUS := int_status ) ; IF ( ( int_status MOD 8 ) <> 1 ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Error Opening ' + File_type + ' : ' + filename ) ; handle_trc_sta ( TAG := tag, STATUS := int_status ) ; status := IO_failure ; GOTO quit_Transfer_exe ; END ; RESET ( executable ) ; {Set file in read mode and read first record } {skip first record ^B} IF ( EOF ( executable ) = TRUE ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' File is Empty ' + filename ) ; status := IO_failure ; GOTO quit_Transfer_exe ; END ; {get first useful record} record_num := 1 ; GET ( executable ) ; word_num := 0 ; WHILE ( EOF ( executable ) <> TRUE ) DO BEGIN record_num := record_num + 1 ; WHILE ( LENGTH ( executable^ ) >= 11 ) DO BEGIN str_buffer := SUBSTR( executable^, 1, 2 ) + SUBSTR( executable^, 4, 2 ) + SUBSTR( executable^, 7, 2 ) + SUBSTR( executable^, 10, 2 ) ; FOR nib_num := 0 TO 7 DO CASE SUBSTR(str_buffer, 8-nib_num) OF '0' : int_buffer[nib_num] := 0 ; '1' : int_buffer[nib_num] := 1 ; '2' : int_buffer[nib_num] := 2 ; '3' : int_buffer[nib_num] := 3 ; '4' : int_buffer[nib_num] := 4 ; '5' : int_buffer[nib_num] := 5 ; '6' : int_buffer[nib_num] := 6 ; '7' : int_buffer[nib_num] := 7 ; '8' : int_buffer[nib_num] := 8 ; '9' : int_buffer[nib_num] := 9 ; 'A' : int_buffer[nib_num] := 10 ; 'B' : int_buffer[nib_num] := 11 ; 'C' : int_buffer[nib_num] := 12 ; 'D' : int_buffer[nib_num] := 13 ; 'E' : int_buffer[nib_num] := 14 ; 'F' : int_buffer[nib_num] := 15 ; END ; Hydra^.Dual_Port_Mem[word_num] := int_buffer::INTEGER ; word_num := word_num + 1 ; executable^ := SUBSTR( executable^, 13 ) ; END ; GET ( executable ) ; END ; handle_trc_inf ( TAG := tag, MESSAGE := ' File had ' + CONVERT(STRING,word_num) + ' LongWords in ' + CONVERT(STRING,record_num) + ' Records ' ) ; quit_Transfer_exe: CLOSE ( executable ) ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE Test_VME_conX ; VAR addr, data : INTEGER ; err_cnt : INTEGER ; loop_count : INTEGER ; pause_count : INTEGER ; BEGIN handle_trc_err ( TAG := tag, MESSAGE := time_stamp + ' start 10^7 empty loops ' ) ; FOR addr := 1 TO 10000000 DO BEGIN data := addr ; END ; handle_trc_err ( TAG := tag, MESSAGE := time_stamp + ' start 10^7 write loops ' ) ; FOR addr := 1 TO 10000000 DO BEGIN VME_mapped_region^[scratch_A24_page].LongWord[scratch_A24_long_offset] := data ; END ; handle_trc_err ( TAG := tag, MESSAGE := time_stamp + ' start 10^7 read loops ' ) ; FOR addr := 1 TO 10000000 DO BEGIN data := VME_mapped_region^[scratch_A24_page].LongWord[scratch_A24_long_offset] ; END ; handle_trc_err ( TAG := tag, MESSAGE := time_stamp + ' start infinite memory test ' ) ; FOR addr := scratch_A24_long_offset TO scratch_A24_long_offset + longwords_of_A24_scratch - 1 DO BEGIN VME_mapped_region^[scratch_A24_page].LongWord[addr] := addr + addr ; data := VME_mapped_region^[scratch_A24_page].LongWord[addr] ; IF ( data <> addr + addr ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Init A24/D32 Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A24_page].LongWord[addr],8,8) ) ; raise_exception ( KER$_DEBUG_SIGNAL ) ; {get debugger to investigate } END ; END ; FOR addr := scratch_A16_byte_offset TO scratch_A16_byte_offset + bytes_of_A16_scratch - 1 DO BEGIN VME_mapped_region^[scratch_A16_page].Byte[addr] := ( addr + addr ) MOD 256 ; data := VME_mapped_region^[scratch_A16_page].byte[addr] ; IF ( data <> ( (addr+addr) MOD 256 ) ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Init A16/D8 Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A16_page].LongWord[addr],8,8) ) ; raise_exception ( KER$_DEBUG_SIGNAL ) ; {get debugger to investigate } END ; END ; err_cnt := 0 ; loop_count := 0 ; pause_count := 100 ; infinite_loop: loop_count := loop_count + 1 ; IF ( loop_count >= pause_count ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' VME register test, Loop Count ' + CONVERT(STRING,loop_count) + ', Error Count ' + CONVERT(STRING,err_cnt) ) ; { access a non existant VME memory to cause a VME Bus error} VME_mapped_region^[scratch_A16_page].Byte[0] := 0 ; WAIT_ANY ( TIME := -10000000 ) ; {wait 1 s} loop_count := 0 ; END ; FOR addr := scratch_A24_long_offset TO scratch_A24_long_offset + longwords_of_A24_scratch - 1 DO BEGIN data := VME_mapped_region^[scratch_A24_page].LongWord[addr] ; IF ( data <> addr + addr ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Pre-A24/D32-Wrt Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A24_page].LongWord[addr],8,8) ) ; err_cnt := err_cnt + 1 ; handle_trc_err ( TAG := tag, MESSAGE := ' Error Count = ' + CONVERT(STRING, err_cnt ) ) ; END ; VME_mapped_region^[scratch_A24_page].LongWord[addr] := addr + addr ; data := VME_mapped_region^[scratch_A24_page].LongWord[addr] ; IF ( data <> addr + addr ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Post-A24/D32-Wrt Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A24_page].LongWord[addr],8,8) ) ; err_cnt := err_cnt + 1 ; handle_trc_err ( TAG := tag, MESSAGE := ' Error Count = ' + CONVERT(STRING, err_cnt ) ) ; END ; END ; FOR addr := scratch_A16_byte_offset TO scratch_A16_byte_offset + bytes_of_A16_scratch - 1 DO BEGIN data := VME_mapped_region^[scratch_A16_page].Byte[addr] ; IF ( data <> ( (addr+addr) MOD 256 ) ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Pre-A16/D8-Wrt Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A16_page].Byte[addr],8,8) ) ; err_cnt := err_cnt + 1 ; handle_trc_err ( TAG := tag, MESSAGE := ' Error Count = ' + CONVERT(STRING, err_cnt ) ) ; END ; VME_mapped_region^[scratch_A16_page].Byte[addr] := (addr+addr) MOD 256 ; data := VME_mapped_region^[scratch_A16_page].Byte[addr] ; IF ( data <> ( (addr+addr) MOD 256 ) ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' Post-A16/D8-Wrt Err @ %X' + HEX(addr,8,8) + ' = ' + HEX(data,8,8) + ' <> ' + HEX(addr+addr,8,8) + ' re-read ' + HEX(VME_mapped_region^[scratch_A16_page].Byte[addr],8,8) ) ; err_cnt := err_cnt + 1 ; handle_trc_err ( TAG := tag, MESSAGE := ' Error Count = ' + CONVERT(STRING, err_cnt ) ) ; END ; END ; GOTO infinite_loop ; END ; { *************************************************************************** } PROCEDURE get_addresses_of_l15ct ; BEGIN Hydra_A_Ctrl[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_A_Page_Ctrl]) ; Hydra_A_DPM[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_A_Page_DPM]) ; Hydra_B_Ctrl[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_B_Page_Ctrl]) ; Hydra_B_DPM[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_B_Page_DPM]) ; Hydra_C_Ctrl[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_C_Page_Ctrl]) ; Hydra_C_DPM[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Hydra_C_Page_DPM]) ; CPU_68k_DPM[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[CPU_68k_Page_DPM]) ; CPU_68k_Ctrl[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[CPU_68k_Page_Ctrl]) ; Ironics[Crate_0]::^pVBA_Mapped_page := ADDRESS(VME_mapped_region^[Ironics_page]) ; addresses_loaded := TRUE ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE check_DSP_booted ( Hydra :^DPM_Map_for_all_DSP_and_68k ; DSP : DSP_ID ; VAR status :[OPTIONAL] status_type ) ; VAR DSP_Stat : DSP_to_TCC_Status_Block ; expected_flag : INTEGER ; BEGIN IF present(status) THEN status := ok ; CASE DSP OF LDSP_A2 : expected_flag := %XA2000000 ; LDSP_A3 : expected_flag := %XA3000000 ; LDSP_A4 : expected_flag := %XA4000000 ; LDSP_A1 : expected_flag := %XA1000000 ; LDSP_B3 : expected_flag := %XB3000000 ; LDSP_B4 : expected_flag := %XB4000000 ; LDSP_B1 : expected_flag := %XB1000000 ; LDSP_C3 : expected_flag := %XC3000000 ; LDSP_C4 : expected_flag := %XC4000000 ; LDSP_C1 : expected_flag := %XC1000000 ; LDSP_C2 : expected_flag := %XC2000000 ; GDSP_B2 : expected_flag := %XB2000000 ; END ; DSP_Stat := hydra^.DSP_to_TCC_Stat[DSP] ; IF ( DSP_Stat.Longword[0] = expected_flag ) THEN handle_trc_sys ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Boot Status ok' ) ELSE BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Boot Status to TCC is %X' + HEX(DSP_Stat.Longword[0],8,8) + ' instead of %X' + HEX(expected_flag,8,8) ) ; IF present (status) THEN status := error_found ; END ; END ; { *************************************************************************** } PROCEDURE Check_DSP_to_TCC_Status ( Hydra :^DPM_Map_for_all_DSP_and_68k ; DSP : DSP_ID ; VAR status :[OPTIONAL] status_type ) ; VAR DSP_Stat : DSP_to_TCC_Status_Block ; BEGIN DSP_Stat := hydra^.DSP_to_TCC_Stat[DSP] ; {check the whole longword first} IF ( DSP_Stat.Longword[0] = Status_ok ) THEN BEGIN IF present(status) THEN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Status to TCC ok, Cleared' ) ; END ELSE BEGIN IF present (status) THEN status := error_found ; handle_trc_sys ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Error Status to TCC is %X' + HEX(DSP_Stat.Longword[0],8,8) + '...' ) ; IF ( DSP_Stat.Error_Code = Local_Tool_Number_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Local Tool Number, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Tool #' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Number_of_Local_Params_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Number of Local Params, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Local_Param_Range_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Local Param out of Range, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Param #' + CONVERT(STRING, DSP_Stat.Expected) + ', Found %X' + HEX(DSP_Stat.Bad_Param_Int,8,8) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Local_Param_Block_Type_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Local Param block Type, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Local_Term_Number_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Local Term Number, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Reference_Set_Type_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Ref Set Type, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Local_Tool_Memory_Ovf_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Local Tool Mem overflow, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Global_Tool_Number_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Global Tool Number, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Tool #' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Number_of_Global_Params_Error) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Number of Global Params, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Global_Param_Range_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Global Param out of Range, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Param #' + CONVERT(STRING, DSP_Stat.Expected) + ', Found %X' + HEX(DSP_Stat.Bad_Param_Int,8,8) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Global_Param_Block_Type_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Global Param block Type, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Global_Term_Number_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Global Term Number, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) + ', Tool # ' + CONVERT(STRING, DSP_Stat.Tool_Num) ) ELSE IF ( DSP_Stat.Error_Code = Number_of_Frame_Params_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Number of Frame Params, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Frame_Param_Range_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Frame Param out of Range, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Param #' + CONVERT(STRING, DSP_Stat.Expected) + ', Found %X' + HEX(DSP_Stat.Bad_Param_Int,8,8) ) ELSE IF ( DSP_Stat.Error_Code = Frame_Param_Block_Type_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Frame Param block Type, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Frame_Term_Number_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Frame Term Number, Term #' + CONVERT(STRING, DSP_Stat.Term_Num) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Memory_Map_Version_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Memory Map version' + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Number_of_Defined_Terms_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Number of Terms defined' + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = Number_of_Univ_Params_Error ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Bad Number of Universal Params' + ', Expected ' + CONVERT(STRING, DSP_Stat.Expected) + ', Found ' + CONVERT(STRING, DSP_Stat.Found) ) ELSE IF ( DSP_Stat.Error_Code = CRC_Port_Token_Warning ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Comm Port Token not released by CRC' + ', Port ID ' + CONVERT(STRING, DSP_Stat.CommPort_ID) + ' (Warning)' ) ; { this is just a warning, as some of the system } { might be disconnected or not yet implemented } IF present(status) THEN status := ok ; END ELSE IF ( DSP_Stat.Error_Code = CRC_Port_FIFO_Warning ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Comm Port FIFO not empty' + ', Port ID ' + CONVERT(STRING, DSP_Stat.CommPort_ID) + ' from a CRC Channel' ) ELSE IF ( DSP_Stat.Error_Code = LG_Prev_Port_FIFO_Warning ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Comm Port FIFO not empty' + ', Port ID ' + CONVERT(STRING, DSP_Stat.CommPort_ID) + ' from a Local DSP upstream' ) ELSE IF ( DSP_Stat.Error_Code = LG_Next_Port_FIFO_Warning ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Comm Port FIFO not empty' + ', Port ID ' + CONVERT(STRING, DSP_Stat.CommPort_ID) + ' to the next DSP downstream' ) ELSE handle_trc_err ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Unknown error -' + ' review TCC routine Check_DSP_to_TCC_Status' + ' from mod_handle_l15ct' ) ; END ; END ; { *************************************************************************** } PROCEDURE Check_DSP_to_EC_Status ( Hydra :^DPM_Map_for_all_DSP_and_68k ; DSP : DSP_ID ; VAR status :[OPTIONAL] status_type ) ; VAR DSP_Stat : DSP_to_EC_Status_Block ; BEGIN IF present(status) THEN status := ok ; DSP_Stat := hydra^.DSP_to_EC_Stat[DSP] ; {check the whole Status word for special 'D0' state} IF ( DSP_Stat.Status = Waiting_for_Valid_WUW ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Ready, Waiting for Wake Up Word' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; END ELSE BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' DSP ' + CONVERT(STRING, DSP ) + ' Status to 68k is %X' + HEX(DSP_Stat.Longword[0],8,8) + '...' ) ; {first check if the keyword makes sense (e.g. not all FF)} {don't try to decode otherwise} IF ( DSP_Stat.Unused <> 0 ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Illegal bit(s) set ' + 'in Status Word to 68k for DSP ' + CONVERT(STRING, DSP ) ) ELSE BEGIN IF ( DSP_Stat.Got_WUW = 1 ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has found a valid Wake Up Word' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; IF ( DSP_Stat.Got_Data = 1 ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has received its Input Data' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; IF ( DSP_Stat.Done_Code = 1 ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has run its algorithm' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; IF ( DSP <> GDSP_B2) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has found ' + CONVERT(STRING, DSP_Stat.Total_Obj) + ' Objects, TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ELSE handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has evaluated Answer %X' + HEX(DSP_Stat.Term_Ans,2,2) + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; END ; IF ( DSP_Stat.Done_Trsf = 1 ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has transferred its Data' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; IF ( ( DSP = GDSP_B2) AND ( DSP_Stat.No_Trsf = 1 ) ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' has acknowledged no Transfer Necessary' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; IF ( DSP_Stat.Wait_Synch = 1 ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...DSP ' + CONVERT(STRING, DSP ) + ' Waiting for Synch from 68k' + ', TAS Byte is %X' + HEX(DSP_Stat.TAS_Byte,2,2) ) ; END ; END ; END ; { *************************************************************************** } PROCEDURE check_68k_acknowledge ( CPU_68k :^DPM_Map_for_all_DSP_and_68k ; VAR status :[OPTIONAL] status_type ) ; CONST expected_flag = %X68000000 ; VAR CPU_68k_Stat : EC_to_TCC_Status_Block ; BEGIN IF present(status) THEN status := ok ; CPU_68k_Stat := CPU_68k^.EC_to_TCC_Stat ; IF ( CPU_68k_Stat.Longword[0] = expected_flag ) THEN handle_trc_sys ( TAG := tag, MESSAGE := ' 68k parked Status ok (Load_Code Interrupt)' ) ELSE BEGIN handle_trc_err ( TAG := tag, MESSAGE := ' 68k Boot Status is %X' + HEX(CPU_68k_Stat.Longword[0],8,8) + ' instead of %X' + HEX(expected_flag,8,8) ) ; IF present (status) THEN status := error_found ; END ; END ; { *************************************************************************** } PROCEDURE Check_68k_Status ( CPU_68k :^DPM_Map_for_all_DSP_and_68k ; VAR status :[OPTIONAL] status_type ) ; VAR CPU_68k_Stat : EC_to_TCC_Status_Block ; Univ_Header_Received : Header_Word_Universal_Param ; Univ_Header_Expected : Header_Word_Universal_Param ; BEGIN CPU_68k_Stat := CPU_68k^.EC_to_TCC_Stat ; {check the whole longword first} IF ( CPU_68k_Stat.Longword[0] = Status_ok ) THEN BEGIN IF present(status) THEN status := ok ; handle_trc_sys ( TAG := tag, MESSAGE := ' 68k Status to TCC ok, Cleared' ) ; END ELSE BEGIN IF present (status) THEN status := error_found ; handle_trc_sys ( TAG := tag, MESSAGE := ' 68k Error Status is %X' + HEX(CPU_68k_Stat.Longword[0],8,8) + '...' ) ; IF ( CPU_68k_Stat.Error_Code = Univ_Param_Header_error ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := '...Univ Param Block Header Error,' + ' Expect %X' + HEX(CPU_68k_Stat.Expected,8,8) + ', read %X' + HEX(CPU_68k_Stat.Received,8,8) ) ; Univ_Header_Received::INTEGER := CPU_68k_Stat.Received ; Univ_Header_Expected::INTEGER := CPU_68k_Stat.Expected ; IF ( Univ_Header_Received.Map_Rev_Num <> Univ_Header_Expected.Map_Rev_Num ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...(cont) problem in the' + ' Map Revision Number,' + ' Expect %X' + HEX(Univ_Header_Expected.Map_Rev_Num,2,2) + ', read %X' + HEX(Univ_Header_Received.Map_Rev_Num,2,2) ) ; IF ( Univ_Header_Received.Map_Version_Num <> Univ_Header_Expected.Map_Version_Num ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...(cont) problem in the' + ' Map Version Number,' + ' Expect %X' + HEX(Univ_Header_Expected.Map_Version_Num,2,2) + ', read %X' + HEX(Univ_Header_Received.Map_Version_Num,2,2) ) ; IF ( Univ_Header_Received.Crate_ID <> Univ_Header_Expected.Crate_ID ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...(cont) problem in the' + ' Crate ID,' + ' Expect %X' + HEX(Univ_Header_Expected.Crate_ID,2,2) + ', read %X' + HEX(Univ_Header_Received.Crate_ID,2,2) ) ; END ELSE IF ( CPU_68k_Stat.Error_Code = Bad_MFP_Ratio ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Bad Mark and Force Pass Ratio,' + ' Term #' + CONVERT(STRING, CPU_68k_Stat.Term_Num) + ', read ' + CONVERT(STRING, CPU_68k_Stat.MFP_read) ) ELSE IF ( CPU_68k_Stat.Error_Code = DSP_was_not_ready ) THEN BEGIN handle_trc_err ( TAG := tag, MESSAGE := '...68k did not find all DSPs ready' + ' and waiting at step D0' ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' A2=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A2],8,8) + ' A3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A3],8,8) + ' A4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A4],8,8) + ' A1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' ' + ' B3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B3],8,8) + ' B4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B4],8,8) + ' B1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' C2=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C2],8,8) + ' C3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C3],8,8) + ' C4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C4],8,8) + ' C1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Global DSP' + ' B2=%X' + HEX(CPU_68k_Stat.DSP_Status[GDSP_B2],8,8) ) ; END ELSE handle_trc_err ( TAG := tag, MESSAGE := '...Unknown 68k error -' + ' review TCC routine Check_68k_Status' + ' from mod_handle_l15ct' ) ; END ; END ; { *************************************************************************** } PROCEDURE Read_68k_Errors ( CPU_68k :^DPM_Map_for_all_DSP_and_68k ; VAR status :[OPTIONAL] status_type ) ; CONST No_Error_Yet = %XFFFFFFFF ; VAR CPU_68k_Stat : EC_to_TCC_Status_Block ; BEGIN IF present(status) THEN status := ok ; CPU_68k_Stat := CPU_68k^.EC_to_TCC_Stat ; {only go in details about error recovery if there has been any} IF ( CPU_68k_Stat.Last_Condition = No_Error_Yet ) THEN handle_trc_sys ( TAG := tag, MESSAGE := ' 68k never had to Un-Stick the DSPs' ) ELSE BEGIN IF present (status) THEN status := error_found ; handle_trc_err ( TAG := tag, MESSAGE := ' 68k Last Un-Stick Action was for a problem at %X' + HEX(CPU_68k_Stat.Last_Condition) + '...' ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' A2=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A2],8,8) + ' A3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A3],8,8) + ' A4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A4],8,8) + ' A1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_A1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' ' + ' B3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B3],8,8) + ' B4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B4],8,8) + ' B1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_B1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Local DSP' + ' C2=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C2],8,8) + ' C3=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C3],8,8) + ' C4=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C4],8,8) + ' C1=%X' + HEX(CPU_68k_Stat.DSP_Status[LDSP_C1],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Global DSP' + ' B2=%X' + HEX(CPU_68k_Stat.DSP_Status[GDSP_B2],8,8) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...a DSP not at D0 Un-Stick Count = ' + CONVERT(STRING, CPU_68k_Stat.UnStick_D0_Cnt) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...Global not at D3 Un-Stick Count = ' + CONVERT(STRING, CPU_68k_Stat.UnStick_D3_Cnt) ) ; handle_trc_err ( TAG := tag, MESSAGE := '...a DSP not at D15 Un-Stick Count = ' + CONVERT(STRING, CPU_68k_Stat.UnStick_D15_Cnt) ) ; END ; IF ( CPU_68k_Stat.Byt_MisAlign_Cnt = 0 ) THEN handle_trc_sys ( TAG := tag, MESSAGE := ' 68k never saw any Byte Misalignment Problem' + ' in Object Lists' ) ELSE handle_trc_sys ( TAG := tag, MESSAGE := ' 68k saw byte Misalignment Count = ' + CONVERT(STRING,CPU_68k_Stat.Byt_MisAlign_Cnt) ) ; END ; { *************************************************************************** } PROCEDURE Read_68k_Flags ( CPU_68k :^DPM_Map_for_all_DSP_and_68k ) ; CONST Flag_Set = %XF0 ; Flag_Cleared = %X00 ; VAR CPU_68k_Stat : EC_to_TCC_Status_Block ; Flag_State : STRING(7) ; BEGIN CPU_68k_Stat := CPU_68k^.EC_to_TCC_Stat ; handle_trc_sys ( TAG := tag, MESSAGE := ' Reading 68k Software Flags... ' ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.All_DSPS_at_Step_D0 ,2,2) ; IF ( CPU_68k_Stat.All_DSPS_at_Step_D0 = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.All_DSPS_at_Step_D0 = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...All_DSPS_at_Step_D0 Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.MFP_Event ,2,2) ; IF ( CPU_68k_Stat.MFP_Event = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.MFP_Event = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...MFP_Event Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.If_Transfer_Want_MFP_Transfer ,2,2) ; IF ( CPU_68k_Stat.If_Transfer_Want_MFP_Transfer = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.If_Transfer_Want_MFP_Transfer = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...If_Transfer_Want_MFP_Transfer Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.This_Transfer_is_MFP ,2,2) ; IF ( CPU_68k_Stat.This_Transfer_is_MFP = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.This_Transfer_is_MFP = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...This_Transfer_is_MFP Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.Previous_Transfer_Was_MFP ,2,2) ; IF ( CPU_68k_Stat.Previous_Transfer_Was_MFP = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.Previous_Transfer_Was_MFP = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...Previous_Transfer_Was_MFP Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.Fresh_Load_Buf_Availb ,2,2) ; IF ( CPU_68k_Stat.Fresh_Load_Buf_Availb = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.Fresh_Load_Buf_Availb = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...Fresh_Load_Buf_Availb Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.All_Data_In_Load_Buf ,2,2) ; IF ( CPU_68k_Stat.All_Data_In_Load_Buf = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.All_Data_In_Load_Buf = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...All_Data_In_Load_Buf Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.Told_GDSP_to_Transfer ,2,2) ; IF ( CPU_68k_Stat.Told_GDSP_to_Transfer = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.Told_GDSP_to_Transfer = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...Told_GDSP_to_Transfer Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.Which_214_Is_Load_Buf ,2,2) ; IF ( CPU_68k_Stat.Which_214_Is_Load_Buf = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.Which_214_Is_Load_Buf = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...Which_214_Is_Load_Buf Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.State_of_RC_FE_Busy ,2,2) ; IF ( CPU_68k_Stat.State_of_RC_FE_Busy = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.State_of_RC_FE_Busy = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...State_of_RC_FE_Busy Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.SRDY_Has_Been_Sent ,2,2) ; IF ( CPU_68k_Stat.SRDY_Has_Been_Sent = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.SRDY_Has_Been_Sent = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...SRDY_Has_Been_Sent Flag = ' + Flag_State ) ; Flag_State := '%X' + HEX(CPU_68k_Stat.VBD_Is_Ready ,2,2) ; IF ( CPU_68k_Stat.VBD_Is_Ready = Flag_Cleared ) THEN Flag_State := 'Cleared' ; IF ( CPU_68k_Stat.VBD_Is_Ready = Flag_Set ) THEN Flag_State := 'Set' ; handle_trc_sys ( TAG := tag, MESSAGE := '...VBD_Is_Ready Flag = ' + Flag_State ) ; END ; { *************************************************************************** } PROCEDURE Read_68k_Counts ( CPU_68k :^DPM_Map_for_all_DSP_and_68k ) ; VAR CPU_68k_Stat : EC_to_TCC_Status_Block ; BEGIN CPU_68k_Stat := CPU_68k^.EC_to_TCC_Stat ; handle_trc_sys ( TAG := tag, MESSAGE := ' Reading 68k Run Counters... ' ) ; handle_trc_sys ( TAG := tag, MESSAGE := '...Orbit Master Loops Count = ' + CONVERT(STRING, CPU_68k_Stat.Orbit_cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."That''s Me" With Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Big_N_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."That''s Me" NO Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Little_n_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Bystander" With Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Big_I_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Bystander" NO Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Little_i_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Mark&Pass" With Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Big_F_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Mark&Pass" NO Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Little_f_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Un-Stick" With Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Big_E_Cnt ) ) ; handle_trc_sys ( TAG := tag, MESSAGE := '..."Un-Stick" NO Transfer Count = ' + CONVERT(STRING, CPU_68k_Stat.Little_e_Cnt ) ) ; END ; { *************************************************************************** } PROCEDURE Check_Wake_Up_Word ( Hydra :^DPM_Map_for_all_DSP_and_68k ; DSP : DSP_ID ; VAR status :[OPTIONAL] status_type ) ; VAR Wake_Up : Wake_Up_Block ; BEGIN IF present(status) THEN status := ok ; Wake_Up := hydra^.EC_to_DSP_Stat ; { *** take care of Local Wake up word *** } { but only for Local DSP} IF ( DSP <> GDSP_B2 ) THEN BEGIN IF ( Wake_Up.Local_Wkup_Word.Flag_Byte = No_Flag_Set ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Local Wake Up Word Flagged Cleared %X' + HEX(Wake_Up.Local_Wkup_Word,8,8) + ' on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) + ', TAS Byte is %X' + HEX(Wake_Up.Local_Wkup_Word.TAS_Byte,2,2) ) ; END ELSE BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Local Wake Up Word on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) + ' is %X' + HEX(Wake_Up.Local_Wkup_Word,8,8) + '...' ) ; IF ( Wake_Up.Local_Wkup_Word.Reserved <> 0 ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Illegal bit(s) set in Local Wake Up Word' ) ELSE IF ( Wake_Up.Local_Wkup_Word.Flag_Byte = Yes_Mark_Pass ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Local Wake up Word' + ' Mark&Pass Flag Set to YES' ) ELSE IF ( Wake_Up.Local_Wkup_Word.Flag_Byte = Not_Mark_Pass ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Local Wake up Word' + ' Mark&Pass Flag Set to NO' ) ELSE handle_trc_err ( TAG := tag, MESSAGE := '...Local Wake up Word has Illegal Flag Byte' ) ; handle_trc_sys ( TAG := tag, MESSAGE := '...Local Wake Up Word Terms to Evaluate %B' + BIN(Wake_Up.Local_Wkup_Word.Terms_to_Eval) + ', TAS Byte is %X' + HEX(Wake_Up.Local_Wkup_Word.TAS_Byte,2,2) ) ; END ; END ; { *** take care of Global Wake up word *** } { but only for Global DSP} IF ( DSP = GDSP_B2 ) THEN BEGIN IF ( Wake_Up.Global_Wkup_Word.Flag_Byte = No_Flag_Set ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Global Wake Up Word Flagged Cleared %X' + HEX(Wake_Up.Global_Wkup_Word,8,8) + ' on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) + ', TAS Byte is %X' + HEX(Wake_Up.Global_Wkup_Word.TAS_Byte,2,2) ) ; END ELSE BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Global Wake Up Word on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) + ' is %X' + HEX(Wake_Up.Global_Wkup_Word,8,8) + '...' ) ; IF ( Wake_Up.Global_Wkup_Word.Reserved <> 0 ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Illegal bit(s) set in Global Wake Up Word' ) ELSE IF ( Wake_Up.Global_Wkup_Word.Flag_Byte = Yes_Mark_Pass ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Global Wake up Word' + ' Mark&Pass Flag Set to YES' ) ELSE IF ( Wake_Up.Global_Wkup_Word.Flag_Byte = Not_Mark_Pass ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Global Wake up Word' + ' Mark&Pass Flag Set to NO' ) ELSE handle_trc_err ( TAG := tag, MESSAGE := '...Global Wake up Word has Illegal Flag Byte' ) ; handle_trc_sys ( TAG := tag, MESSAGE := '...Global Wake Up Word Terms to Evaluate %B' + BIN(Wake_Up.Global_Wkup_Word.Terms_to_Eval) + ', TAS Byte is %X' + HEX(Wake_Up.Global_Wkup_Word.TAS_Byte,2,2) ) ; END ; END ; { *** take care of Transfer word *** } { but only for Global DSP} IF ( DSP = GDSP_B2 ) THEN BEGIN IF ( Wake_Up.Transfer_Word.Transf_Flag = No_Flag_Set ) THEN BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Transfer Word Flagged Cleared %X' + HEX(Wake_Up.Transfer_Word,8,8) + ' on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) ) ; END ELSE BEGIN handle_trc_sys ( TAG := tag, MESSAGE := ' Transfer Word on Hydra ' + SUBSTR(CONVERT(STRING,DSP), 6, 1) + ' is %X' + HEX(Wake_Up.Transfer_Word,8,8) + '...' ) ; IF ( Wake_Up.Transfer_Word.Reserved <> 0 ) THEN handle_trc_err ( TAG := tag, MESSAGE := '...Illegal bit(s) set in Transfer Word' ) ELSE IF ( Wake_Up.Transfer_Word.Transf_Flag = Not_Transfer ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...Transfer Word Flag Set to NO' ) ELSE IF ( Wake_Up.Transfer_Word.Transf_Flag = Yes_Transfer ) THEN handle_trc_sys ( TAG := tag, MESSAGE := '...Transfer Word Flag Set to YES' ) ELSE handle_trc_err ( TAG := tag, MESSAGE := '...Transfer Word Flag has Illegal Flag Byte' ) ; END ; END ; END ; { *************************************************************************** } [INLINE] FUNCTION time_stamp : STRING(23) ; VAR status : INTEGER ; bin_time : LARGE_INTEGER ; ascii_time : STRING(23) ; BEGIN GET_TIME ( bin_time, STATUS := status ) ; ascii_time := TIME_STRING(bin_time) ; time_stamp := SUBSTR(ascii_time,13) ; END ; { *************************************************************************** } [INLINE] FUNCTION inline_byte_or ( op1 , op2 : byte ) : byte ; VAR bool1, bool2, bool3 : BOOLEAN ; BEGIN bool1::BYTE_DATA := op1::BYTE_DATA ; bool2::BYTE_DATA := op2::BYTE_DATA ; bool3 := bool1 OR bool2 ; inline_byte_or::BYTE_DATA := bool3::BYTE_DATA ; END ; { *************************************************************************** } { *************************************************************************** } FUNCTION Conv_VAX_Float_to_DSP ( Number : REAL ) : INTEGER ; CONST Positive = 0 ; {sign bit encoding value for positive numbers} Negative = 1 ; {sign bit encoding value for negative numbers} TYPE VAX_D_Float_Type = [LONG] PACKED RECORD High_Fract : [POS( 0)] 0..127 ; { 7 bits} Exponent : [POS( 7)] 0..255 ; { 8 bits} Sign : [POS(15)] 0..1 ; { 1 bit } Low_Fract : [POS(16)] word ; {16 bits} END ; DSP_Float_Type = [LONG] PACKED RECORD Low_Fract : [POS( 0)] word ; {16 bits} High_Fract : [POS(16)] 0..127 ; { 7 bits} Sign : [POS(23)] 0..1 ; { 1 bit } Exponent : [POS(24)] 0..255 ; { 8 bits} END ; VAR DSP_Float : DSP_Float_Type ; VAX_Float : VAX_D_Float_Type ; mantissa : DSP_Float_Type ; BEGIN {transfer to more suitable temporary variable} VAX_Float::REAL := Number ; {Transfer the fields by pieces} {transfer the mantissa first} mantissa::INTEGER := 0 ; mantissa.Low_Fract := VAX_FLoat.Low_Fract ; mantissa.High_Fract := VAX_FLoat.High_Fract ; {The VAX stores the mantissa in absolute value} {The DSP stores the mantissa in two's complements when the sign is negative} {The two's complement will trash the upper bits, which are later overwritten} IF ( VAX_FLoat.Sign = Positive ) THEN DSP_FLoat::INTEGER := + mantissa::INTEGER ELSE DSP_FLoat::INTEGER := - mantissa::INTEGER ; {Transfer the sign} DSP_Float.Sign := VAX_FLoat.Sign ; {VAX exponent is an excess 128 binary value, DSP is just twos-complement } {Exponent values of 1 through 255 indicate } {binary exponents (e) of -127 through +127. } DSP_Float.Exponent := VAX_FLoat.Exponent - 128 ; {There is an additional offset in the exponent of one count: } {The VAX architecture stores the number as %B0.1f * 2^e } {(where f is the normalized binary fraction) } {while the C40 stores it as %B1.f * 2^(e-1) } {Zero however is represented as e=-128 in the DSP architectures } IF ( VAX_FLoat::INTEGER <> 0 ) THEN DSP_Float.Exponent := DSP_FLoat.Exponent - 1 ; {Pure negative powers of two need another shift of one count in the exponent} IF ( (VAX_FLoat.Sign = Negative) AND (mantissa::INTEGER = 0) ) THEN DSP_Float.Exponent := DSP_FLoat.Exponent - 1 ; {return value from the more suitable temporary variable} Conv_VAX_Float_to_DSP := DSP_Float::INTEGER ; END ; { *************************************************************************** } END .