{ *************************************************************************** }
MODULE mod_init_cbus_cards ;
{ Created   11-APR-1989 MICHIGAN STATE UNIVERSITY,  TRIGGER CONTROL SOFTWARE }
{ *************************************************************************** }
INCLUDE
  mod_common_global_flags,
  mod_handle_tracing,
  mod_io_allocation_handling,
  mod_handle_mail,
  mod_def_hardware_tables,
  mod_def_physics_tables,
  mod_handle_registers,
  mod_common_hard_io ;                {from the TRICS hardware IO library     }
{ *************************************************************************** }
EXPORT
  init_cbus_cards;  {PROCEDURE initializing the hardware database             }
{ *************************************************************************** }
IMPORT
  status_type, ok, {already_done,} io_failure,
                                      {from module MOD_COMMON_GLOBAL_FLAGS    }

 {state_type,} ON, OFF,               {from module MOD_HANDLE_TRACING         }
 {trace_info, trace_warn,}trace_error,{from module MOD_HANDLE_TRACING         }
  handle_trc_sys,                     {from module MOD_HANDLE_TRACING         }
  handle_trc_err,                     {from module MOD_HANDLE_TRACING         }
  modify_trace_inf,                   {from module MOD_HANDLE_TRACING         }
  modify_trace_wrn,                   {from module MOD_HANDLE_TRACING         }
  modify_trace_err,                   {from module MOD_HANDLE_TRACING         }
  modify_io_tracing,                  {from module MOD_HANDLE_TRACING         }
  modify_db_tracing,                  {from module MOD_HANDLE_TRACING         }
  save_tracing_status,                {from module MOD_HANDLE_TRACING         }
  restore_tracing_status,             {from module MOD_HANDLE_TRACING         }

  sptrg_per_aobackp,                  {from module MOD_HANDLE_TRACING         }
  aoterm_per_aobackp,                 {from module MOD_HANDLE_TRACING         }
  sptrg_per_fstd,                     {from module MOD_HANDLE_TRACING         }
  sptrg_number,                       {from module MOD_HANDLE_TRACING         }
  sptrg_per_dbsc,                     {from module MOD_HANDLE_TRACING         }
  sptrg_per_digm,                     {from module MOD_HANDLE_TRACING         }
  geosec_per_digm,                    {from module MOD_HANDLE_TRACING         }

  send_mail,                          {from module MOD_HANDLE_MAIL            }

 {scaler_per_dbsc,}     exposc,   firedsc,
  relative_sptrg,       relst_0,  relst_1, {relst_2,}  relst_3,
  relative_geo_section, relgs_0, {relgs_1,  relgs_2,}  relgs_3,
                                      {from module MOD_DEF_HARDWARE_TABLES    }

  allocate_trigger,                   {from module MOD_IO_ALLOCATION_HADLLING }
  deallocate_trigger,                 {from module MOD_IO_ALLOCATION_HADLLING }

  mtg_card, dbsc_card,                {from module MOD_DEF_HARDWARE_TABLES    }
 {bbb, mbd,}imlinput,{imlroinput,}andor, fstd, dbsc, sbscdis, sbscaofired,
  sbscstdig, sbscfebz, {tlmfired, imlrofired,}dgmstdig,{tlmbusy, imlrobusy,}
  dgmbzdis, {tlmtrgnum, tlmstdig, tlmfiredstb, tlmfiredout, imlroaux,}mtgdirin,
  mtgholdtx, mtgstdig, mtgbusy, mtgfwtss, mtgtwb, dbsctrgnum, dbscbeamx,
  dbscvtprep, dbscwaitvbd, dbscL0_P1_4, dbscL0_P5_6, dbscaux, dbscforeign,
 {tlmL15_fan,}dgmL15_ans,{imlroL15,}dgmL15_ctrl, mtgL15_vc, mtgL15_mux,
  mtgL15_ctrl, dbscL15, sbscL15_cyc_skp, sbscL15_dead_to, sbscL15_cnf_rej,
 {mbdL15,}                            {from module MOD_DEF_HARDWARE_TABLES    }

  mtgcttss,                           {from module MOD_DEF_HARDWARE_TABLES    }
  tss_fw_write_AB, tss_fw_LED_on, tss_fw_l1_per_bunch_clk,
  tss_fw_incr_stdigt_num, tss_fw_incr_transf_num, tss_fw_st_fired_strobe,
  tss_fw_skip_one_beam_X, tss_fw_skip_two_beam_X, tss_fw_skip_ten_beam_X,
 {tss_L15_short_timeout,              {from module MOD_DEF_HARDWARE_TABLES    }
  tss_Force_High,                     {from module MOD_DEF_HARDWARE_TABLES    }
  tss_Force_Low,                      {from module MOD_DEF_HARDWARE_TABLES    }
  tss_Sel_Rom,                        {from module MOD_DEF_HARDWARE_TABLES    }
  tss_ROM_Gated,                      {from module MOD_DEF_HARDWARE_TABLES    }
  tss_Ext_Bit,                        {from module MOD_DEF_HARDWARE_TABLES    }
  eta_polarity,                       {from module MOD_DEF_HARDWARE_TABLES    }
  magn_eta_per_fe_cell,               {from module MOD_DEF_HARDWARE_TABLES    }
  relative_eta,                       {from module MOD_DEF_HARDWARE_TABLES    }
  rele_0,{rele_1, rele_2,}rele_3,     {from module MOD_DEF_HARDWARE_TABLES    }
  phi_value,                          {from module MOD_DEF_HARDWARE_TABLES    }
  phi_per_fe_half_cell,               {from module MOD_DEF_HARDWARE_TABLES    }
  adc_data_type_per_ctfe_channel,     {from module MOD_DEF_HARDWARE_TABLES    }
  EMEtZ0, HDEtZ0,                     {from module MOD_DEF_HARDWARE_TABLES    }
  threshold_reference_set_type,       {from module MOD_DEF_HARDWARE_TABLES    }
  EMEt_ref,{HDEt_veto,}TOTEt_ref,     {from module MOD_DEF_HARDWARE_TABLES    }
  EMEt_cmp,TOTEt_cmp,                 {from module MOD_DEF_HARDWARE_TABLES    }
  threshold_reference_set_number,     {from module MOD_DEF_HARDWARE_TABLES    }
  ref_0, ref_3, ref_7,                {from module MOD_DEF_HARDWARE_TABLES    }
  cat2_bit_field,                     {from module MOD_DEF_HARDWARE_TABLES    }
  bit_0_5,{bit_6_11,}bit_12_14,       {from module MOD_DEF_HARDWARE_TABLES    }
  comparison_number,                  {from module MOD_DEF_HARDWARE_TABLES    }
  cmp_0,{cmp_1, cmp_2,}cmp_3,         {from module MOD_DEF_HARDWARE_TABLES    }
  eta_per_rack_pair,                  {from module MOD_DEF_HARDWARE_TABLES    }
  Momentum_sign, pos_m, neg_m,        {from module MOD_DEF_HARDWARE_TABLES    }
  cat3_cmp_field, cat3_cor_field,     {from module MOD_DEF_HARDWARE_TABLES    }
  cat3_cmp_0_5, cat3_cmp_18, cat3_cor_0_5, cat3_cor_18_23,
  ctfe_card_high_half,                {from module MOD_DEF_HARDWARE_TABLES    }
  ctfe_ctrl,                          {FROM module MOD_DEF_HARDWARE_TABLES    }
  cat2_EME_t1, cat2_HDE_t1, cat2_PxM_t1, cat2_PyM_t1,
  cat2_EME_t2, cat2_HDE_t2, cat2_PxM_t2, cat2_PyM_t2,
  cat2_EMC_t2, cat2_TOTC_t2,          {FROM module MOD_DEF_HARDWARE_TABLES    }
  cat3_EM_Et_t3, cat3_HD_Et_t3, cat3_Py_t3, cat3_Px_t3,
  cat2_EM_cnt_t3, cat2_TOT_cnt_t3, cat3_EM_L2_t3, cat3_HD_L2_t3,
  cat3_TOT_Et_t4, cat3_TOT_L2_t4,     {FROM module MOD_DEF_HARDWARE_TABLES    }
  jet_list_aoc,                       {FROM module MOD_DEF_HARDWARE_TABLES    }
  LT_list_aoc,                        {FROM module MOD_DEF_HARDWARE_TABLES    }
  fmln_compare,                       {FROM module MOD_DEF_HARDWARE_TABLES    }
{  fmln_compute,                       {FROM module MOD_DEF_HARDWARE_TABLES    }
  trc_err_init_hdb_fw,                {from module MOD_DEF_HARDWARE_TABLES    }
  trc_err_init_hdb_ct,                {from module MOD_DEF_HARDWARE_TABLES    }
  erpb_mtg,                           {from module MOD_DEF_HARDWARE_TABLES    }

  firstetasign,                       {from module MOD_DEF_PHYSCS_TABLE       }
  lastetasign,                        {from module MOD_DEF_PHYSCS_TABLE       }
  firstetamagn,                       {from module MOD_DEF_PHYSCS_TABLE       }
  lastetamagn,                        {from module MOD_DEF_PHYSCS_TABLE       }
  firstphival,                        {from module MOD_DEF_PHYSCS_TABLE       }
  lastphival,                         {from module MOD_DEF_PHYSCS_TABLE       }

  update_register,                    {from module MOD_HANDLE_REGISTER        }
  update_prscratio,                   {from module MOD_HANDLE_REGISTER        }

  cbus_param_list ;                   {from module MOD_COMMON_HARD_IO         }
{ *************************************************************************** }
{ *************************************************************************** }

  %INCLUDE 'SITE_DEPENDENT.CST/LIST'

CONST

  reset_dbsc            =   5 ; {reset double buffered scaler}
  reset_sbsc            =   0 ; {force reset single buffered scaler}

VAR

  ini_status : status_type ; {general purpose status buffer}
  fail_count : INTEGER := 0 ;

{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE init_cbus_cards ( tagext : VARYING_STRING(16) := '' ;
                            inipar :^cbus_param_list := NIL ;
                        VAR status :[OPTIONAL] status_type ) ;

VAR

  st : sptrg_number ;
  st_ao : sptrg_per_aobackp ;
  ao_bp : aoterm_per_aobackp ;
  st_fd : sptrg_per_fstd ;
  st_ds : sptrg_per_dbsc ;
  gs_dg : geosec_per_digm ;
  st_dg : sptrg_per_digm ;
  relst : relative_sptrg ;
  relgs : relative_geo_section ;
  i,j   : INTEGER ;
  local_io_param : BOOLEAN := TRUE ;

  cell_sign_eta : eta_polarity ;
  cell_magn_eta : magn_eta_per_fe_cell ;
  phi           : phi_value ;
  p_ctfe_ctrl   :^ctfe_card_high_half ;
  rele          : relative_eta ;
  ch_typ        : adc_data_type_per_ctfe_channel ;
  th_typ        : threshold_reference_set_type ;
  th_num        : threshold_reference_set_number ;
  cell_phi      : phi_per_fe_half_cell ;
  bit_f         : cat2_bit_field ;
  cmpnum        : comparison_number ;
  eta_tier2     : eta_per_rack_pair ;
  momt_sign     : momentum_sign ;
  cat3_cmp_f    : cat3_cmp_field ;
  cat3_cor_f    : cat3_cor_field ;

BEGIN

  IF PRESENT(status) THEN status := ok ;

{ *** allocate memory for the register initialization parameter list      *** }
  IF ( inipar = NIL )
  THEN BEGIN
    local_io_param := TRUE ;
    NEW ( inipar ) ;
    deallocate_trigger ( TAGEXT := tagext, REPORT := FALSE ) ;
    allocate_trigger ( TAGEXT := tagext, CALLER_ID := inipar, REPORT := FALSE );
  END
  ELSE local_io_param := FALSE ;

  { ************************************************************************* }
  { *** First, Do Framework Cards                                         *** }
  { ************************************************************************* }

  fail_count := 0 ;

  handle_trc_sys ( TAG := 'INI/HDB%' + tagext ,
               MESSAGE := ' Initializing All Framework Registers ' ) ;

  save_tracing_status ;

  modify_trace_inf ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  modify_trace_wrn ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  IF ( trace_error.logfile = ON )
  THEN modify_trace_err ( CONSOLE := OFF,
                          LOGFILE := trc_err_init_hdb_fw, REPORT := FALSE )
  ELSE modify_trace_err ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  modify_db_tracing (  STATE := OFF, REPORT := FALSE ) ;
  modify_io_tracing (  STATE := OFF, REPORT := FALSE ) ;

{ *** master timing generator cards                                       *** }

  {***Direct In Test Trigger MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgdirin), INIPAR := inipar ) ;

  FOR i := 0 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgdirin),
                  REGISTER := ADDRESS(mtgdirin.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_dirin_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;


  {***hold transfer MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgholdtx), INIPAR := inipar ) ;

  FOR i := 0 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgholdtx),
                  REGISTER := ADDRESS(mtgholdtx.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_holdtx_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;


  {***start digitize MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgstdig), INIPAR := inipar ) ;

  FOR i := 0 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgstdig),
                  REGISTER := ADDRESS(mtgstdig.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_stdig_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {***front end busy MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgbusy), INIPAR := inipar ) ;

  update_register ( CARD := ADDRESS(mtgbusy),
                REGISTER := ADDRESS(mtgbusy.channelreg[0]),
                   IOPAR := inipar,
                    DATA := init_busy_mtg_ch,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  {special PAL stretch comint fe busy}
  update_register ( CARD := ADDRESS(mtgbusy),
                REGISTER := ADDRESS(mtgbusy.channelreg[1]),
                   IOPAR := inipar,
                    DATA := 0,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  FOR i := 2 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgbusy),
                  REGISTER := ADDRESS(mtgbusy.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_busy_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {***framework timing and synchronization signals MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgfwtss), INIPAR := inipar ) ;

  FOR i := 0 TO 3
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_tss_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ ch# 5 (fa 4): Write A/B has a limited number of writeable bits}
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_write_AB]),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  FOR i := 5 TO 12
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_tss_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ ch# 14 (fa 13): Increment Start Dgt Number needs to be a special ROM Gated }
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_incr_stdigt_num]),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 15 (fa 14): skip one beam crossing}
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_skip_one_beam_X]),
                   IOPAR := inipar,
                    DATA := 0,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 16 (fa 15): Led ON can follow the PROM}
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_LED_on]),
                     IOPAR := inipar,
                      DATA := init_tss_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 17 (fa 16): skip two beam crossings }
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_skip_two_beam_X]),
                   IOPAR := inipar,
                    DATA := 0,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 18 (fa 17): skip ten beam crossings }
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_skip_ten_beam_X]),
                   IOPAR := inipar,
                    DATA := 0,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 19 (fa 18): L1 per Bunch DBSC clck needs to be ROM gated               }
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_l1_per_bunch_clk]),
                   IOPAR := inipar,
                    DATA := tss_ROM_Gated,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 20 (fa 19): Trigger Number DBSC clk needs to be ROM gated              }
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_incr_transf_num]),
                   IOPAR := inipar,
                    DATA := tss_ROM_Gated,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 21 (fa 20): SpTrg Fired Strobe Shape needs to be ROM Gated             }
  update_register ( CARD := ADDRESS(mtgfwtss),
                REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_st_fired_strobe]),
                   IOPAR := inipar,
                    DATA := tss_ROM_Gated,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  FOR i := 21 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgfwtss),
                  REGISTER := ADDRESS(mtgfwtss.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_tss_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { *** Special IO MTG card *** }

  FOR i := 24 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgtwb),
                  REGISTER := ADDRESS(mtgtwb.channelreg[i]),
                     IOPAR := inipar,
                      DATA := TSS_Force_Low,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ *** IML cards                                                           *** }

  FOR ao_bp := CONVERT( aoterm_per_aobackp, firstaoterm DIV 128 )
            TO CONVERT( aoterm_per_aobackp, lastaoterm  DIV 128 )
  DO BEGIN
    FOR st_ao := CONVERT( sptrg_per_aobackp, firstsptrg DIV 16 )
              TO CONVERT( sptrg_per_aobackp, lastsptrg  DIV 16 )
    DO BEGIN

      FOR i := 0 TO   imlinput[ao_bp,st_ao].regtotal - 1
      DO BEGIN
        update_register ( CARD := ADDRESS(imlinput[ao_bp,st_ao]),
                      REGISTER := ADDRESS(imlinput[ao_bp,st_ao].simureg[i]),
                         IOPAR := inipar,
                          DATA := init_iml,
                        STATUS := ini_status ) ;
        inline_check_io_failure ;
      END ;
    END ;
  END ;

{ *** ANDOR cards                                                         *** }

  FOR ao_bp := CONVERT( aoterm_per_aobackp, firstaoterm DIV 128 )
            TO CONVERT( aoterm_per_aobackp, lastaoterm  DIV 128 )
  DO BEGIN
    FOR st := CONVERT( sptrg_number, firstsptrg )
           TO CONVERT( sptrg_number, lastsptrg )
    DO BEGIN

      FOR i := 0 TO andor[ao_bp,st].regtotal - 1
      DO BEGIN
        update_register ( CARD := ADDRESS(andor[ao_bp,st]),
                      REGISTER := ADDRESS(andor[ao_bp,st].netreg[i]),
                         IOPAR := inipar,
                          DATA := init_andor,
                        STATUS := ini_status ) ;
        inline_check_io_failure ;
      END ;

    END ;
  END ;


{ *** FSTD cards                                                         *** }

  FOR st_fd := CONVERT( sptrg_per_fstd, firstsptrg DIV 4 )
            TO CONVERT( sptrg_per_fstd, lastsptrg  DIV 4 )
  DO FOR relst := relst_0 TO relst_3
  DO BEGIN
    update_register ( CARD := ADDRESS(fstd[st_fd]),
                  REGISTER := ADDRESS(fstd[st_fd].enabreg[relst]),
                     IOPAR := inipar,
                      DATA := init_fstd_veto,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_prscratio ( CARD := ADDRESS(fstd[st_fd]),
                   REGISTER := ADDRESS(fstd[st_fd].psctrlreg[relst]),
                      IOPAR := inipar,
                      RATIO := init_prsc_ratio,
                     STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;

{ *** DBSC cards                                                          *** }

  {*** DBSC in FSTD cells }
  FOR st_ds := CONVERT( sptrg_per_dbsc, firstsptrg DIV 2 )
            TO CONVERT( sptrg_per_dbsc, lastsptrg  DIV 2 )
  DO reset_dbsc_card ( CARD := ADDRESS(dbsc[st_ds]), INIPAR := inipar ) ;

  {*** DBSC Trigger Number  }
  reset_dbsc_card ( CARD := ADDRESS(dbsctrgnum::dbsc_card), INIPAR := inipar ) ;

  { *** DBSC Beam Crossing Number }
  reset_dbsc_card ( CARD := ADDRESS(dbscbeamx::dbsc_card), INIPAR := inipar ) ;

  { *** DBSC VME Transfer Program Prepare Data }
  reset_dbsc_card ( CARD := ADDRESS(dbscvtprep::dbsc_card), INIPAR := inipar ) ;

  { *** DBSC VME Transfer Program Wait for VBD Buffer }
  reset_dbsc_card ( CARD := ADDRESS(dbscwaitvbd::dbsc_card), INIPAR := inipar ) ;

  { *** DBSC Cards in Bottom Backplane of M114 }
  reset_dbsc_card ( CARD := ADDRESS(dbscL0_P1_4::dbsc_card), INIPAR := inipar ) ;
  reset_dbsc_card ( CARD := ADDRESS(dbscL0_P5_6::dbsc_card), INIPAR := inipar ) ;
  reset_dbsc_card ( CARD := ADDRESS(dbscaux::dbsc_card), INIPAR := inipar ) ;
  FOR i := 1 TO 11
  DO reset_dbsc_card ( CARD := ADDRESS(dbscforeign[i]::dbsc_card),
                     INIPAR := inipar ) ;

{ *** SBSC cards                                                          *** }

  FOR st_fd := CONVERT( sptrg_per_fstd, firstsptrg DIV 4 )
            TO CONVERT( sptrg_per_fstd, lastsptrg  DIV 4 )
  DO FOR i := 0 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(sbscdis[st_fd]),
                  REGISTER := ADDRESS(sbscdis[st_fd].ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  FOR i := 0 TO 7
  DO BEGIN

    update_register ( CARD := ADDRESS(sbscaofired),
                  REGISTER := ADDRESS(sbscaofired.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(sbscstdig),
                  REGISTER := ADDRESS(sbscstdig.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(sbscfebz),
                  REGISTER := ADDRESS(sbscfebz.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;

{ *** DIGIMEM cards                                                       *** }

  FOR gs_dg := CONVERT( geosec_per_digm, firstgeosec DIV 4 )
            TO CONVERT( geosec_per_digm, lastgeosec  DIV 4 )
  DO FOR relgs := relgs_0 TO relgs_3
  DO FOR i := 0 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(dgmstdig[gs_dg]),
                  REGISTER := ADDRESS(dgmstdig[gs_dg].netreg[relgs,i]),
                     IOPAR := inipar,
                      DATA := init_dgm_stdig,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  FOR st_dg := CONVERT( sptrg_per_digm, firstsptrg DIV 4 )
            TO CONVERT( sptrg_per_digm, lastsptrg  DIV 4 )
  DO FOR relst := relst_0 TO relst_3
  DO FOR i := 0 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(dgmbzdis[st_dg]),
                  REGISTER := ADDRESS(dgmbzdis[st_dg].netreg[relst,i]),
                     IOPAR := inipar,
                      DATA := init_dgm_bzdis,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { ************************************************************************* }
  { *** Second, Do L1.5 Framework Cards                                   *** }
  { ************************************************************************* }

  FOR st_dg := CONVERT( sptrg_per_digm, firstL15sptrg DIV 4 )
            TO CONVERT( sptrg_per_digm, lastL15sptrg  DIV 4 )
  DO FOR relst := relst_0 TO relst_3
  DO FOR i := 0 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(dgmL15_ans[st_dg]),
                  REGISTER := ADDRESS(dgmL15_ans[st_dg].netreg[relst,i]),
                     IOPAR := inipar,
                      DATA := init_dgm_L15_terms,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { *** l1.5 control digimem }
  FOR i := 0 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(dgmL15_ctrl),
                  REGISTER := ADDRESS(dgmL15_ctrl.spare[i]),
                     IOPAR := inipar,
                      DATA := init_dgm_L15_spare,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
    update_register ( CARD := ADDRESS(dgmL15_ctrl),
                  REGISTER := ADDRESS(dgmL15_ctrl.L15_confirmed[i]),
                     IOPAR := inipar,
                      DATA := init_dgm_L15_confirm,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
    update_register ( CARD := ADDRESS(dgmL15_ctrl),
                  REGISTER := ADDRESS(dgmL15_ctrl.L15_fired[i]),
                     IOPAR := inipar,
                      DATA := init_dgm_L15_fired,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
    update_register ( CARD := ADDRESS(dgmL15_ctrl),
                  REGISTER := ADDRESS(dgmL15_ctrl.PL1_fired[i]),
                     IOPAR := inipar,
                      DATA := init_dgm_L15_pureL1,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { enable Level 1.5 timeout }
  update_register ( CARD := ADDRESS(dgmL15_ctrl),
                REGISTER := ADDRESS(dgmL15_ctrl.L15_confirmed[7]),
                   IOPAR := inipar,
                    DATA := init_dgm_L15_timeout,
                  STATUS := ini_status ) ;


  { *** l1.5 veto/confirm mtg }
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgL15_vc), INIPAR := inipar ) ;

  FOR i := 0 TO 15
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_vc),
                  REGISTER := ADDRESS(mtgL15_vc.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_l15_confirm,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;
  FOR i := 16 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_vc),
                  REGISTER := ADDRESS(mtgL15_vc.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_veto,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { *** l1.5 term multiplex mtg }
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgL15_mux), INIPAR := inipar ) ;

  FOR i := 0 TO 18
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_mux),
                  REGISTER := ADDRESS(mtgL15_mux.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_receive,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { *** l1.5 control mtg }
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgL15_ctrl), INIPAR := inipar ) ;

  FOR i := 0 TO 4
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_ctrl),
                  REGISTER := ADDRESS(mtgL15_ctrl.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_ctrl,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {channel #6 not initialized}

  FOR i := 6 TO 23
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_ctrl),
                  REGISTER := ADDRESS(mtgL15_ctrl.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_ctrl,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {channel #25 not initialized}

  FOR i := 25 TO 27
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_ctrl),
                  REGISTER := ADDRESS(mtgL15_ctrl.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_ctrl,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {channel #29 & #30 not initialized}

  FOR i := 30 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgL15_ctrl),
                  REGISTER := ADDRESS(mtgL15_ctrl.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_MTG_L15_ctrl,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  { *** global l1.5 DBSC }
  reset_dbsc_card ( CARD := ADDRESS(dbscL15::dbsc_card),
                  INIPAR := inipar ) ;

  FOR i := 0 TO 7
  DO BEGIN

  { *** l1.5 cycle/skip SBSC L1.5 }
    update_register ( CARD := ADDRESS(sbscL15_cyc_skp),
                  REGISTER := ADDRESS(sbscL15_cyc_skp.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  { *** l1.5 dead crossing / tiemout SBSC }
    update_register ( CARD := ADDRESS(sbscL15_dead_to),
                  REGISTER := ADDRESS(sbscL15_dead_to.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  { *** l1.5 reject / confirm SBSC }
    update_register ( CARD := ADDRESS(sbscL15_cnf_rej),
                  REGISTER := ADDRESS(sbscL15_cnf_rej.ctrlreg[i]),
                     IOPAR := inipar,
                      DATA := reset_sbsc,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;


  { done }
  restore_tracing_status ( REPORT := FALSE ) ;

  IF ( fail_count  <> 0 )
  THEN BEGIN
    send_mail ( ADDRESS := mail_alert_1 + mail_alert_2 + mail_alert_3,
                SUBJECT := CONVERT(STRING,fail_count) 
                         + ' Errors Initializing Framework Registers' ) ;
    handle_trc_err ( TAG := 'INI/HDB%' + tagext ,
                 MESSAGE := ' Framework Register Init Failure Count Is '
                          + CONVERT(STRING,fail_count)  ) ;
    IF PRESENT(status) THEN status := io_failure ;
  END ;

  { ************************************************************************* }
  { *** Third, Do L1 Calorimeter Trigger Cards                            *** }
  { ************************************************************************* }

  fail_count := 0 ;

  handle_trc_sys ( TAG := 'INI/HDB%' + tagext ,
               MESSAGE := ' Initializing All Calorimeter Trigger Registers ' );

  save_tracing_status ;

  modify_trace_inf ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  modify_trace_wrn ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  IF ( trace_error.logfile = ON )
  THEN modify_trace_err ( CONSOLE := OFF,
                          LOGFILE := trc_err_init_hdb_ct, REPORT := FALSE )
  ELSE modify_trace_err ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;
  modify_db_tracing (  STATE := OFF, REPORT := FALSE ) ;
  modify_io_tracing (  STATE := OFF, REPORT := FALSE ) ;

  {***timing and synchronization signals MTG}
  init_mtg_ctrl_registers ( CARD := ADDRESS(mtgcttss), INIPAR := inipar ) ;

  FOR i := 0 TO 31
  DO BEGIN
    update_register ( CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[i]),
                     IOPAR := inipar,
                      DATA := init_tss_mtg_ch,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  {Tier # 1}
{ initialize data base for the ctfe cards                               }

  FOR cell_sign_eta := firstetasign TO lastetasign
  DO BEGIN

    FOR cell_magn_eta := CONVERT( magn_eta_per_fe_cell,
                                 (ORD(firstetamagn)-1) DIV 4 )
                      TO CONVERT( magn_eta_per_fe_cell,
                                 (ORD(lastetamagn)-1) DIV 4 )
    DO BEGIN

      FOR phi := firstphival TO lastphival
      DO BEGIN

        p_ctfe_ctrl := ADDRESS ( ctfe_ctrl[cell_sign_eta,cell_magn_eta,phi] ) ;

        update_register   ( CARD := p_ctfe_ctrl,
                        REGISTER := ADDRESS(p_ctfe_ctrl^.brdctrl),
                           IOPAR := inipar,
                            DATA := 129, {ADC data, normal clock, load simu}
                          STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register   ( CARD := p_ctfe_ctrl,
                        REGISTER := ADDRESS(p_ctfe_ctrl^.loadsimreg),
                           IOPAR := inipar,
                            DATA := 0, {clear simu register}
                          STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register   ( CARD := p_ctfe_ctrl,
                        REGISTER := ADDRESS(p_ctfe_ctrl^.chanctrl),
                           IOPAR := inipar,
                            DATA := 255,    {all channels updated }
                          STATUS := ini_status ) ;
        inline_check_io_failure ;

        FOR rele := rele_0 TO rele_3
        DO BEGIN

          FOR ch_typ := EMEtZ0 TO HDEtZ0
          DO BEGIN

             update_register( CARD := p_ctfe_ctrl,
                          REGISTER := ADDRESS(p_ctfe_ctrl^.pedreg[rele,ch_typ]),
                             IOPAR := inipar,
                              DATA := 0, {all pedestal register zeored}
                            STATUS := ini_status ) ;
             inline_check_io_failure ;

          END ;{ch_typ}

          FOR th_typ := EMEt_ref TO TOTEt_ref
          DO FOR th_num := ref_0 TO ref_3
          DO BEGIN

            update_register   ( CARD := p_ctfe_ctrl,
                            REGISTER := ADDRESS(p_ctfe_ctrl^.thrreg[rele,th_typ,th_num]),
                               IOPAR := inipar,
                                DATA := 255, {all thresholds set to maximum}
                              STATUS := ini_status ) ;
            inline_check_io_failure ;

          END ;{th_num&th_typ}
        END; {rele}

      END ;{phi}

    END ;{cell_magn_eta}

  END ;{cell_sign_eta}

{ initialize data base for the tier #1 cat2 cards                             }

  FOR cell_sign_eta := firstetasign TO lastetasign
  DO BEGIN

    FOR cell_magn_eta := CONVERT( magn_eta_per_fe_cell,
                                 (ORD(firstetamagn)-1) DIV 4 )
                      TO CONVERT( magn_eta_per_fe_cell,
                                 (ORD(lastetamagn)-1)  DIV 4 )
    DO BEGIN

      FOR cell_phi := CONVERT( phi_per_fe_half_cell,
                              (ORD(firstphival)-1) DIV 8 )
                   TO CONVERT( phi_per_fe_half_cell,
                              (ORD(lastphival)-1)  DIV 8 )
      DO BEGIN

        FOR bit_f := bit_0_5 TO bit_12_14
        DO BEGIN

          update_register ( CARD := ADDRESS(cat2_EME_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                        REGISTER := ADDRESS(cat2_EME_t1[cell_sign_eta,cell_magn_eta,cell_phi].corrreg[bit_f]),
                           IOPAR := inipar,
                            DATA := 0, {all correction registers zeroed}
                          STATUS := ini_status ) ;
          inline_check_io_failure ;

          update_register ( CARD := ADDRESS(cat2_HDE_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                        REGISTER := ADDRESS(cat2_HDE_t1[cell_sign_eta,cell_magn_eta,cell_phi].corrreg[bit_f]),
                           IOPAR := inipar,
                            DATA := 0, {all correction registers zeroed}
                          STATUS := ini_status ) ;
          inline_check_io_failure ;

          update_register ( CARD := ADDRESS(cat2_PxM_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                        REGISTER := ADDRESS(cat2_PxM_t1[cell_sign_eta,cell_magn_eta,cell_phi].corrreg[bit_f]),
                           IOPAR := inipar,
                            DATA := 0, {all correction registers zeroed}
                          STATUS := ini_status ) ;
          inline_check_io_failure ;

          update_register ( CARD := ADDRESS(cat2_PyM_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                        REGISTER := ADDRESS(cat2_PyM_t1[cell_sign_eta,cell_magn_eta,cell_phi].corrreg[bit_f]),
                           IOPAR := inipar,
                            DATA := 0, {all correction registers zeroed}
                          STATUS := ini_status ) ;
          inline_check_io_failure ;

          FOR cmpnum := cmp_0 TO cmp_3
          DO BEGIN

            update_register ( CARD := ADDRESS(cat2_EME_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                          REGISTER := ADDRESS(cat2_EME_t1[cell_sign_eta,cell_magn_eta,cell_phi].compreg[cmpnum,bit_f]),
                             IOPAR := inipar,
                              DATA := 0, {all comparator registers zeroed}
                            STATUS := ini_status ) ;
            inline_check_io_failure ;

            update_register ( CARD := ADDRESS(cat2_HDE_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                          REGISTER := ADDRESS(cat2_HDE_t1[cell_sign_eta,cell_magn_eta,cell_phi].compreg[cmpnum,bit_f]),
                             IOPAR := inipar,
                              DATA := 0, {all comparator registers zeroed}
                            STATUS := ini_status ) ;
            inline_check_io_failure ;

            update_register ( CARD := ADDRESS(cat2_PxM_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                          REGISTER := ADDRESS(cat2_PxM_t1[cell_sign_eta,cell_magn_eta,cell_phi].compreg[cmpnum,bit_f]),
                             IOPAR := inipar,
                              DATA := 0, {all comparator registers zeroed}
                            STATUS := ini_status ) ;
            inline_check_io_failure ;

            update_register ( CARD := ADDRESS(cat2_PyM_t1[cell_sign_eta,cell_magn_eta,cell_phi]),
                          REGISTER := ADDRESS(cat2_PyM_t1[cell_sign_eta,cell_magn_eta,cell_phi].compreg[cmpnum,bit_f]),
                             IOPAR := inipar,
                              DATA := 0, {all comparator registers zeroed}
                            STATUS := ini_status ) ;
            inline_check_io_failure ;

          END ; {cmpnum}
        END ; {bit_f}

      END ; {cell_phi}
    END ; {cell_magn_eta}
  END ; {cell_sign_eta}


  {Tier # 2}

  FOR cell_magn_eta := CONVERT( magn_eta_per_fe_cell,
                               (ORD(firstetamagn)-1) DIV 4 )
                    TO CONVERT( magn_eta_per_fe_cell,
                               (ORD(lastetamagn)-1) DIV 4 )
  DO BEGIN

    FOR bit_f := bit_0_5 TO bit_12_14
    DO BEGIN
      update_register ( CARD := ADDRESS(cat2_EME_t2[cell_magn_eta]),
                    REGISTER := ADDRESS(cat2_EME_t2[cell_magn_eta].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat2_HDE_t2[cell_magn_eta]),
                    REGISTER := ADDRESS(cat2_HDE_t2[cell_magn_eta].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR bit_f := bit_0_5 TO bit_12_14
      DO BEGIN
        update_register ( CARD := ADDRESS(cat2_EME_t2[cell_magn_eta]),
                      REGISTER := ADDRESS(cat2_EME_t2[cell_magn_eta].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register ( CARD := ADDRESS(cat2_HDE_t2[cell_magn_eta]),
                      REGISTER := ADDRESS(cat2_HDE_t2[cell_magn_eta].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;
      END ;

    END ; {cmpnum}
  END ; {cell_magn_eta}

  FOR th_num := ref_0 TO ref_3
  DO FOR cell_magn_eta := CONVERT( magn_eta_per_fe_cell,
                               (ORD(firstetamagn)-1) DIV 4 )
                       TO CONVERT( magn_eta_per_fe_cell,
                               (ORD(lastetamagn)-1) DIV 4 )
  DO BEGIN

    FOR bit_f := bit_0_5 TO bit_12_14
    DO BEGIN
      update_register ( CARD := ADDRESS(cat2_EMC_t2[th_num,cell_magn_eta]),
                    REGISTER := ADDRESS(cat2_EMC_t2[th_num,cell_magn_eta].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat2_TOTC_t2[th_num,cell_magn_eta]),
                    REGISTER := ADDRESS(cat2_TOTC_t2[th_num,cell_magn_eta].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR bit_f := bit_0_5 TO bit_12_14
      DO BEGIN
        update_register ( CARD := ADDRESS(cat2_EMC_t2[th_num,cell_magn_eta]),
                      REGISTER := ADDRESS(cat2_EMC_t2[th_num,cell_magn_eta].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register ( CARD := ADDRESS(cat2_TOTC_t2[th_num,cell_magn_eta]),
                      REGISTER := ADDRESS(cat2_TOTC_t2[th_num,cell_magn_eta].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}
  END ; {th_num & cell_magn_eta}

  FOR momt_sign := pos_m TO neg_m
  DO FOR eta_tier2 := CONVERT( eta_per_rack_pair,
                               (ORD(firstetamagn)-1) DIV 8 )
                   TO CONVERT( eta_per_rack_pair,
                               (ORD(lastetamagn)-1) DIV 8 )
  DO BEGIN

    FOR bit_f := bit_0_5 TO bit_12_14
    DO BEGIN
      update_register ( CARD := ADDRESS(cat2_PxM_t2[momt_sign,eta_tier2]),
                    REGISTER := ADDRESS(cat2_PxM_t2[momt_sign,eta_tier2].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat2_PyM_t2[momt_sign,eta_tier2]),
                    REGISTER := ADDRESS(cat2_PyM_t2[momt_sign,eta_tier2].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR bit_f := bit_0_5 TO bit_12_14
      DO BEGIN
        update_register ( CARD := ADDRESS(cat2_PxM_t2[momt_sign,eta_tier2]),
                      REGISTER := ADDRESS(cat2_PxM_t2[momt_sign,eta_tier2].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register ( CARD := ADDRESS(cat2_PyM_t2[momt_sign,eta_tier2]),
                      REGISTER := ADDRESS(cat2_PyM_t2[momt_sign,eta_tier2].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}
  END ; {momt_sign & eta_tier2}

{Tier # 3}

  FOR cmpnum := cmp_0 TO cmp_3
  DO BEGIN

    FOR cat3_cmp_f := cat3_cmp_0_5 TO cat3_cmp_18
    DO BEGIN

      update_register ( CARD := ADDRESS(cat3_EM_L2_t3),
                    REGISTER := ADDRESS(cat3_EM_L2_t3.compreg[cmpnum,cat3_cmp_f]),
                       IOPAR := inipar,
                        DATA := 0, {all comparator registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat3_HD_L2_t3),
                    REGISTER := ADDRESS(cat3_HD_L2_t3.compreg[cmpnum,cat3_cmp_f]),
                       IOPAR := inipar,
                        DATA := 0, {all comparator registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat3_Px_t3),
                    REGISTER := ADDRESS(cat3_Px_t3.compreg[cmpnum,cat3_cmp_f]),
                       IOPAR := inipar,
                        DATA := 0, {all comparator registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat3_Py_t3),
                    REGISTER := ADDRESS(cat3_Py_t3.compreg[cmpnum,cat3_cmp_f]),
                       IOPAR := inipar,
                        DATA := 0, {all comparator registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

  END ; {cmpnum}

  FOR cat3_cor_f := cat3_cor_0_5 TO cat3_cor_18_23
  DO BEGIN

    update_register ( CARD := ADDRESS(cat3_EM_L2_t3),
                  REGISTER := ADDRESS(cat3_EM_L2_t3.corrreg[cat3_cor_f]),
                     IOPAR := inipar,
                      DATA := 0, {all correction registers zeroed}
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(cat3_HD_L2_t3),
                  REGISTER := ADDRESS(cat3_HD_L2_t3.corrreg[cat3_cor_f]),
                     IOPAR := inipar,
                      DATA := 0, {all correction registers zeroed}
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(cat3_Px_t3),
                  REGISTER := ADDRESS(cat3_Px_t3.corrreg[cat3_cor_f]),
                     IOPAR := inipar,
                      DATA := 0, {all correction registers zeroed}
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(cat3_Py_t3),
                  REGISTER := ADDRESS(cat3_Py_t3.corrreg[cat3_cor_f]),
                     IOPAR := inipar,
                      DATA := 0, {all correction registers zeroed}
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;


  FOR j := first_emet_sum_cmp DIV 4  TO last_emet_sum_cmp DIV 4
  DO BEGIN

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR cat3_cmp_f := cat3_cmp_0_5 TO cat3_cmp_18
      DO BEGIN

        update_register ( CARD := ADDRESS(cat3_EM_Et_t3[j]),
                      REGISTER := ADDRESS(cat3_EM_Et_t3[j].compreg[cmpnum,cat3_cmp_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}

    FOR cat3_cor_f := cat3_cor_0_5 TO cat3_cor_18_23
    DO BEGIN

      update_register ( CARD := ADDRESS(cat3_EM_Et_t3[j]),
                    REGISTER := ADDRESS(cat3_EM_Et_t3[j].corrreg[cat3_cor_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

  END ;

  FOR j := first_hdet_sum_cmp DIV 4  TO last_hdet_sum_cmp DIV 4
  DO BEGIN

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR cat3_cmp_f := cat3_cmp_0_5 TO cat3_cmp_18
      DO BEGIN

        update_register ( CARD := ADDRESS(cat3_HD_Et_t3[j]),
                      REGISTER := ADDRESS(cat3_HD_Et_t3[j].compreg[cmpnum,cat3_cmp_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}

    FOR cat3_cor_f := cat3_cor_0_5 TO cat3_cor_18_23
    DO BEGIN

      update_register ( CARD := ADDRESS(cat3_HD_Et_t3[j]),
                    REGISTER := ADDRESS(cat3_HD_Et_t3[j].corrreg[cat3_cor_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

  END ;

  FOR th_num := ref_0 TO ref_3
  DO BEGIN

    FOR bit_f := bit_0_5 TO bit_12_14
    DO BEGIN

      update_register ( CARD := ADDRESS(cat2_EM_cnt_t3[th_num]),
                    REGISTER := ADDRESS(cat2_EM_cnt_t3[th_num].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

      update_register ( CARD := ADDRESS(cat2_TOT_cnt_t3[th_num]),
                    REGISTER := ADDRESS(cat2_TOT_cnt_t3[th_num].corrreg[bit_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR bit_f := bit_0_5 TO bit_12_14
      DO BEGIN

        update_register ( CARD := ADDRESS(cat2_EM_cnt_t3[th_num]),
                      REGISTER := ADDRESS(cat2_EM_cnt_t3[th_num].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

        update_register ( CARD := ADDRESS(cat2_TOT_cnt_t3[th_num]),
                      REGISTER := ADDRESS(cat2_TOT_cnt_t3[th_num].compreg[cmpnum,bit_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}
  END ; {th_num }


  {Tier # 4}

  FOR j := first_totet_sum_cmp DIV 4 TO last_totet_sum_cmp DIV 4
  DO BEGIN

    FOR cmpnum := cmp_0 TO cmp_3
    DO BEGIN

      FOR cat3_cmp_f := cat3_cmp_0_5 TO cat3_cmp_18
      DO BEGIN

        update_register ( CARD := ADDRESS(cat3_TOT_Et_t4[j]),
                      REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compreg[cmpnum,cat3_cmp_f]),
                         IOPAR := inipar,
                          DATA := 0, {all comparator registers zeroed}
                        STATUS := ini_status ) ;
        inline_check_io_failure ;

      END ;

    END ; {cmpnum}

    FOR cat3_cor_f := cat3_cor_0_5 TO cat3_cor_18_23
    DO BEGIN

      update_register ( CARD := ADDRESS(cat3_TOT_Et_t4[j]),
                    REGISTER := ADDRESS(cat3_TOT_Et_t4[j].corrreg[cat3_cor_f]),
                       IOPAR := inipar,
                        DATA := 0, {all correction registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

  END ;

  FOR cmpnum := cmp_0 TO cmp_3
  DO BEGIN

    FOR cat3_cmp_f := cat3_cmp_0_5 TO cat3_cmp_18
    DO BEGIN

      update_register ( CARD := ADDRESS(cat3_TOT_L2_t4),
                    REGISTER := ADDRESS(cat3_TOT_L2_t4.compreg[cmpnum,cat3_cmp_f]),
                       IOPAR := inipar,
                        DATA := 0, {all comparator registers zeroed}
                      STATUS := ini_status ) ;
      inline_check_io_failure ;

    END ;

  END ; {cmpnum}

  FOR cat3_cor_f := cat3_cor_0_5 TO cat3_cor_18_23
  DO BEGIN

    update_register ( CARD := ADDRESS(cat3_TOT_L2_t4),
                  REGISTER := ADDRESS(cat3_TOT_L2_t4.corrreg[cat3_cor_f]),
                     IOPAR := inipar,
                      DATA := 0, {all correction registers zeroed}
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;

{ *** jet list argument andor card }
  FOR th_num := ref_0 TO ref_3
  DO FOR i := 0 TO 3
  DO BEGIN
    update_register ( CARD := ADDRESS(jet_list_aoc),
                  REGISTER := ADDRESS(jet_list_aoc.maskreg[EMEt_cmp,th_num,i]),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

    update_register ( CARD := ADDRESS(jet_list_aoc),
                  REGISTER := ADDRESS(jet_list_aoc.maskreg[TOTEt_cmp,th_num,i]),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

  FOR th_num := ref_0 TO ref_7
  DO FOR i := 0 TO 3
  DO BEGIN
    update_register ( CARD := ADDRESS(LT_list_aoc),
                  REGISTER := ADDRESS(LT_list_aoc.maskreg[th_num,i]),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ *** FMLN cards }
  update_register ( TAGEXT := tagext,
                      CARD := ADDRESS(fmln_compare),
                  REGISTER := ADDRESS(fmln_compare.wr_protect),
                     IOPAR := inipar,
                      DATA := 255,
                    STATUS := ini_status ) ;
  inline_check_io_failure ;
  update_register ( TAGEXT := tagext,
                      CARD := ADDRESS(fmln_compare),
                  REGISTER := ADDRESS(fmln_compare.ovf_ovrule),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
  inline_check_io_failure ;
  update_register ( TAGEXT := tagext,
                      CARD := ADDRESS(fmln_compare),
                  REGISTER := ADDRESS(fmln_compare.controlreg),
                     IOPAR := inipar,
                      DATA := 0,
                    STATUS := ini_status ) ;
  inline_check_io_failure ;

{  update_register ( TAGEXT := tagext,
{                      CARD := ADDRESS(fmln_compute),
{                  REGISTER := ADDRESS(fmln_compute.wr_protect),
{                     IOPAR := inipar,
{                      DATA := 255,
{                    STATUS := ini_status ) ;
{  inline_check_io_failure ;
{  update_register ( TAGEXT := tagext,
{                      CARD := ADDRESS(fmln_compute),
{                  REGISTER := ADDRESS(fmln_compute.ovf_ovrule),
{                     IOPAR := inipar,
{                      DATA := 0,
{                    STATUS := ini_status ) ;
{  inline_check_io_failure ;
{  update_register ( TAGEXT := tagext,
{                      CARD := ADDRESS(fmln_compute),
{                  REGISTER := ADDRESS(fmln_compute.controlreg),
{                     IOPAR := inipar,
{                      DATA := 0,
{                    STATUS := ini_status ) ;
{  inline_check_io_failure ;

  { ************************************************************************* }
  { *** Fourth, Do L1.5 Calorimeter Trigger Cards                         *** }
  { ************************************************************************* }

  init_mtg_ctrl_registers ( CARD := ADDRESS(erpb_mtg), INIPAR := inipar ) ;
  
{ ch# 1 (fa 0): Master of the ERPB_Capture_Clock signal.     }
{ ch# 2 (fa 1): Master of the ERPB_Select_TotEt/EMEt signal. }
  FOR i := 0 TO 1
  DO BEGIN
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i]),
                     IOPAR := inipar,
                      DATA := tss_Sel_Rom,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ ch# 3 (fa 2): Master of the ERPB_Store_Enable_Bar signal.  }
{ ch# 4 (fa 3): Master of the ERPB_Latch_Enable_Bar signal.  }
  FOR i := 2 TO 3
  DO BEGIN
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i]),
                     IOPAR := inipar,
                      DATA := tss_Ext_Bit,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ ch# 5 (fa 4): Master of the EERPB_Transmit_Trigger signal. }
  update_register ( CARD := ADDRESS(erpb_mtg),
                REGISTER := ADDRESS(erpb_mtg.channelreg[4]),
                   IOPAR := inipar,
                    DATA := tss_ROM_Gated,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 6 (fa 5): Master -- spare                              }
  update_register ( CARD := ADDRESS(erpb_mtg),
                REGISTER := ADDRESS(erpb_mtg.channelreg[5]),
                   IOPAR := inipar,
                    DATA := tss_Force_Low,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

{ ch# 7 (fa 6): 2nd capture "Something Happened", hold for 1 BX. }
{ ch# 8 (fa 7): 1st capture "Something Happened", hold for 1 BX. }
  FOR i := 6 TO 7
  DO BEGIN
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i]),
                     IOPAR := inipar,
                      DATA := tss_Ext_Bit,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;
  END ;

{ ch#  9 (fa  8): Drive ERPB_Capture_Clock signal     to |eta|  1:8   }
{ ch# 10 (fa  9): Drive ERPB_Select_TotEt/EMEt signal to |eta|  1:8   }
{ ch# 11 (fa 10): Drive ERPB_Store_Enable_Bar signal  to |eta|  1:8   }
{ ch# 12 (fa 11): Drive ERPB_Latch_Enable_Bar signal  to |eta|  1:8   }
{ ch# 13 (fa 12): Drive ERPB_Transmit_Trigger signal  to |eta|  1:8   }
  FOR i := 8 TO 12
  DO BEGIN
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i]),
                     IOPAR := inipar,
                      DATA := tss_Ext_Bit,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 17..21 (fa  16..20): Same thing for driving        |eta|  9:16  }
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i+8]),
                     IOPAR := inipar,
                      DATA := tss_Ext_Bit,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 25..29 (fa  24..28): Same thing for driving        |eta| 17:20  }
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i+16]),
                     IOPAR := inipar,
                      DATA := tss_Ext_Bit,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;

{ ch# 14 (fa 13): Load the Logic Cell Array signal 1  to |eta|  1:8   }
{ ch# 15 (fa 14): Load the Logic Cell Array signal 2  to |eta|  1:8   }
{ ch# 16 (fa 15): Load the Logic Cell Array signal 3  to |eta|  1:8   }
  FOR i := 13 TO 15
  DO BEGIN
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i]),
                     IOPAR := inipar,
                      DATA := tss_Force_High,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 22..24 (fa  21..23): Same thing for driving        |eta|  9:16  }
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i+8]),
                     IOPAR := inipar,
                      DATA := tss_Force_High,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

{ ch# 30..32 (fa  29..31): Same thing for driving        |eta| 17:20  }
    update_register ( CARD := ADDRESS(erpb_mtg),
                  REGISTER := ADDRESS(erpb_mtg.channelreg[i+16]),
                     IOPAR := inipar,
                      DATA := tss_Force_High,
                    STATUS := ini_status ) ;
    inline_check_io_failure ;

  END ;

  { ************************************************************************* }
  { *** Done                                                              *** }
  { ************************************************************************* }

{ *** release the memory from the register initialization io parameters   *** }
  IF ( local_io_param = TRUE )
  THEN BEGIN
    DISPOSE ( inipar ) ;
    deallocate_trigger ( TAGEXT := tagext, REPORT := FALSE ) ;
  END ;

  restore_tracing_status ( REPORT := FALSE ) ;

  IF ( fail_count  <> 0 )
  THEN BEGIN
    send_mail ( ADDRESS := mail_alert_1 + mail_alert_2 + mail_alert_3,
                SUBJECT := CONVERT(STRING,fail_count) 
                         + ' Errors Initializing CalTrig Registers' ) ;
    handle_trc_err ( TAG := 'INI/HDB%' + tagext ,
                 MESSAGE := ' Cal Trigger Register Init Failure Count Is '
                          + CONVERT(STRING,fail_count)  ) ;
    IF PRESENT(status) THEN status := io_failure ;
  END ;

END ;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE reset_dbsc_card ( card :^dbsc_card ;
                          inipar :^cbus_param_list ) ;
BEGIN

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.resetreg[relst_0,exposc]),
                   IOPAR := inipar,
                    DATA := reset_dbsc,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.resetreg[relst_0,firedsc]),
                   IOPAR := inipar,
                    DATA := reset_dbsc,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.resetreg[relst_1,exposc]),
                   IOPAR := inipar,
                    DATA := reset_dbsc,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.resetreg[relst_1,firedsc]),
                   IOPAR := inipar,
                    DATA := reset_dbsc,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;


END ;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE init_mtg_ctrl_registers ( card :^mtg_card ;
                                  inipar :^cbus_param_list ) ;
BEGIN
  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.start_lsb),
                   IOPAR := inipar,
                    DATA := init_all_mtg_strt_lsb,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.start_msb),
                   IOPAR := inipar,
                    DATA := init_all_mtg_strt_msb,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.stop_lsb),
                   IOPAR := inipar,
                    DATA := init_all_mtg_stop_lsb,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.stop_msb),
                   IOPAR := inipar,
                    DATA := init_all_mtg_stop_msb,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;

  update_register ( CARD := card,
                REGISTER := ADDRESS(card^.controlreg),
                   IOPAR := inipar,
                    DATA := init_all_mtg_ctrl_reg,
                  STATUS := ini_status ) ;
  inline_check_io_failure ;
END ;
{ *************************************************************************** }
{ *************************************************************************** }
[INLINE] PROCEDURE inline_check_io_failure ;
BEGIN
  IF ( ini_status = io_failure ) THEN fail_count := fail_count + 1 ;
END ;
{ *************************************************************************** }
{ *************************************************************************** }
END .