{ **************************************************************************** }
MODULE mod_tst_init ;
{  Created  27-NOV-1989   MICHIGAN STATE UNIVERSITY, TRIGGER CONTROL SOFTWARE }
{ *************************************************************************** }
INCLUDE
  mod_common_global_flags,
  mod_common_soft_conn,
  mod_handle_tracing,
  mod_io_allocation_handling,
  mod_def_hardware_tables,
  mod_handle_registers,
  mod_handle_l15ct,
  mod_init_cbus_cards,
  mod_init_sptrg,
  mod_init_geosec,
  mod_init_globals,
  mod_init_trgtwr,
  mod_init_thresholds,
  mod_init_auxi,
  mod_tcs_io_comint_handling,         {from the TRICS hardware IO library     }
  mod_tcs_io_drv11j_handling,         {from the TRICS hardware IO library     }
  mod_tst_common ;
{ *************************************************************************** }
EXPORT
  power_up_init,
  init_mtg_for_caltrg,  {PROCEDURE setup timing signals for caltrg cell       }
  load_all_ctfe_in_cell;{PROCEDURE initialize all ctfe in a f-end cell        }
{ *************************************************************************** }
IMPORT
  L1_obey_L15,                        {from module MOD_COMMON_GLOBAL_FLAGS    }
  status_type,                        {from module MOD_COMMON_GLOBAL_FLAGS    }
 {ON,}OFF,

  disp_not_busy,                      {from module MOD_COMMON_SOFT_CONN       }

  save_tracing_status,                {from module MOD_HANDLE_TRACING         }
  restore_tracing_status,             {from module MOD_HANDLE_TRACING         }
  handle_trc_sys,                     {from module MOD_HANDLE_TRACING         }
  modify_trace_err,                   {from module MOD_HANDLE_TRACING         }

  deallocate_trigger,                 {from module MOD_IO_ALLOCATION_HADLLING }

  mtgfwtss,                           {from module MOD_DEF_HARDWARE_TABLES    }
  mtgcttss,                           {from module MOD_DEF_HARDWARE_TABLES    }
  tss_force_high, tss_force_low, tss_sel_rom,
  tss_fw_read_ab, tss_fw_write_ab, tss_fw_latch_shift, 
  tss_ct_read_ab, tss_ct_write_ab, tss_ct_latch_shift,
  tss_ct_x_clock, tss_ct_2x_clock, tss_ct_t1_ENR_latch, tss_ct_t1_MOM_latch,
  tss_ct_CHTCR_latch, tss_ct_ADC_Clock,
  tss_ct_imlro_cnt_latch, tss_ct_imlro_1st_latch, tss_ct_imlro_2nd_latch,
  eta_polarity,                       {from module MOD_DEF_HARDWARE_TABLES    }
  phi_value,                          {from module MOD_DEF_HARDWARE_TABLES    }
  relative_eta,                       {from module MOD_DEF_HARDWARE_TABLES    }
    rele_0,{rele_1, rele_2,}rele_3,   {from module MOD_DEF_HARDWARE_TABLES    }
  magn_eta_per_fe_cell,               {from module MOD_DEF_HARDWARE_TABLES    }
  phi_per_fe_half_cell,               {from module MOD_DEF_HARDWARE_TABLES    }
  ctfe_card_high_half,                {from module MOD_DEF_HARDWARE_TABLES    }
  threshold_reference_set_type,       {from module MOD_DEF_HARDWARE_TABLES    }
  EMEt_ref,{DEt_veto,}TOTEt_ref,     {from module MOD_DEF_HARDWARE_TABLES    }
  threshold_reference_set_number,     {from module MOD_DEF_HARDWARE_TABLES    }
  ref_0,{ref_1, ref_2,}ref_3,         {from module MOD_DEF_HARDWARE_TABLES    }

  ctfe_ctrl,                          {from module MOD_DEF_HARDWARE_TABLES    }

  update_register,                    {from module MOD_HANDLE_REGISTER        }

  Init_L15CT_Progr,                   {from module MOD_HANDLE_L15CT           }

  init_cbus_cards,                    {from module MOD_INIT_CBUS_CARDS        }

  init_all_geosec,                    {from module MOD_INIT_GEOSEC            }

  init_all_sptrg,                     {from module MOD_INIT_SPTRG             }

  init_all_trgtwr,                    {from module MOD_INIT_TRGTWR            }
  init_all_LgTile,                    {from module MOD_INIT_TRGTWR            }

  load_tree_corrections,              {from module MOD_INIT_THRESHOLDS        }
  load_momentum_lookup,               {from module MOD_INIT_THRESHOLDS        }
  init_all_thresholds,                {from module MOD_INIT_THRESHOLDS        }

  init_auxi,                          {from module MOD_INIT_AUXI              }

  init_global_scalers,                {from module MOD_INIT_GLOBALS           }

  reading_from_pipe,                  {from module MOD_TST_COMMON             }
  testtag,                            {from module MOD_TST_COMMON             }
  iotest,                             {from module MOD_TST_COMMON             }
  Check_FW_AndOr,                     {from module MOD_TST_COMMON             }

  proced_tcs_reset_comint,            {from module MOD_TCS_IO_COMINT_HANDLING }
  proced_tcs_pause,                   {from module MOD_TCS_IO_COMINT_HANDLING }
  proced_tcs_disable_db_builder,      {from module MOD_TCS_IO_COMINT_HANDLING }
  proced_tcs_release_dbbuilder ;      {from module MOD_TCS_IO_COMINT_HANDLING }
{ *************************************************************************** }
{ *************************************************************************** }
TYPE

  bit  = [BIT(1)] 0..1     ;
  byte = [BYTE]   0..255   ;

{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE power_up_init ;
VAR

  status : status_type ;
  tagext : VARYING_STRING(8) := 'TSTini%' ;

BEGIN

  handle_trc_sys ( TAG := 'TST/INI%',
               MESSAGE := ' Initializing Trigger' ) ;

  proced_tcs_pause ( status ) ;

  proced_tcs_disable_db_builder ;
  proced_tcs_reset_comint ;

  L1_Obey_l15 := FALSE ;

  Init_L15CT_Progr ;

  init_cbus_cards ( STATUS := status, TAGEXT := testtag, INIPAR := iotest ) ;

  init_all_sptrg  ( STATUS := status, TAGEXT := testtag, INIPAR := iotest ) ;

  init_all_geosec ( STATUS := status, TAGEXT := testtag, INIPAR := iotest ) ;

  init_all_trgtwr ( STATUS := status, TAGEXT := tagext, INIPAR := iotest  ) ;

  init_all_LgTile ( STATUS := status, TAGEXT := tagext, INIPAR := iotest  ) ;

  init_all_thresholds ( STATUS := status, TAGEXT := tagext, INIPAR := iotest  ) ;

  load_momentum_lookup ( STATUS := status, TAGEXT := tagext, INIPAR := iotest  ) ;

  load_tree_corrections ( STATUS := status, TAGEXT := tagext, INIPAR := iotest  ) ;

  init_global_scalers ( STATUS := status, TAGEXT := testtag, INIPAR := iotest );

  deallocate_trigger ( TAGEXT := testtag ) ;

  { but first grab the dispatcher-not-busy semaphore             }
  { to prevent mutual data corruption with dispatcher            }
  WAIT_ANY (disp_not_busy) ;
  init_auxi ( STATUS := status, TAGEXT := testtag ) ;
  SIGNAL (disp_not_busy) ;

  synch_double_buffer ( STATUS := status, TAGEXT := testtag ) ;

  proced_tcs_release_dbbuilder ;

END ;
{ *************************************************************************** }
PROCEDURE synch_double_buffer ( tagext : VARYING_STRING(16) := '' ;
                            VAR status :[OPTIONAL] status_type ) ;
EXTERNAL ;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE init_mtg_for_caltrg ;
BEGIN

  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.start_lsb),
                     IOPAR := iotest,
                      DATA := 100 ) ; {preset address at begin of 1st crossing prom pattern}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.start_msb),
                     IOPAR := iotest,
                      DATA := 0 ) ; {preset address at begin prom pattern}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.stop_lsb),
                     IOPAR := iotest,
                      DATA := 192) ; {stop address at end of 1st crossing in prom pattern}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.stop_msb),
                     IOPAR := iotest,
                      DATA := 0 ) ; {stop address at end of prom pattern}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.controlreg),
                     IOPAR := iotest,
                      DATA := 36 ) ; {release clock}

  IF ( Check_FW_AndOr = TRUE ) 
  THEN BEGIN

    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.start_lsb),
                       IOPAR := iotest,
                        DATA := 100); {preset address at begin of prom pattern}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.start_msb),
                       IOPAR := iotest,
                        DATA := 0 ) ; {preset address at begin prom pattern}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.stop_lsb),
                       IOPAR := iotest,
                        DATA := 192) ; {stop address at end of prom pattern}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.stop_msb),
                       IOPAR := iotest,
                        DATA := 0 ) ; {stop address at end of prom pattern}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.controlreg),
                       IOPAR := iotest,
                        DATA := 36 ) ; {release clock}
  END ;

  reading_from_pipe := 'A' ;

  update_register ( TAGEXT := testtag,
                       CARD := ADDRESS(mtgcttss),
                   REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_Read_AB]),
                      IOPAR := iotest,
                       DATA := tss_force_high ) ; {read pipe A}


  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_Write_AB]),
                     IOPAR := iotest,
                      DATA := tss_force_low ) ; {write pipe B}

  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_Latch_Shift]),
                     IOPAR := iotest,
                      DATA := 6 ) ; {29525 latch/shift running}
                                    {special L15MTG06}

  IF ( Check_FW_AndOr = TRUE ) 
  THEN BEGIN

    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_Read_AB]),
                       IOPAR := iotest,
                        DATA := tss_force_high ) ; {read pipe A}
                                                   {MTGBit7, here same as Bit2}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_Write_AB]),
                       IOPAR := iotest,
                        DATA := 3 ) ; {write pipe B}
                                      {Special MTGBit9D}
    update_register ( TAGEXT := testtag,
                        CARD := ADDRESS(mtgfwtss),
                    REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_Latch_Shift]),
                       IOPAR := iotest,
                        DATA := 6 ) ; {29520 latch/shift running}
                                      {special L15MTG05}
  END ;

  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_ADC_Clock]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {ADC clock running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_X_Clock]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {"X" clock running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_2X_Clock]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {"2X" clock running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_T1_ENR_Latch]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ;{CAT2 energy tier #1 latch running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_T1_MOM_Latch]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ;{CAT2 moment tier #1 latch running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_CHTCR_Latch]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {CHTCR tier #1 latch running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_IMLRO_Cnt_Latch]),
                     IOPAR := iotest,
                      DATA := 6 ) ; {global quant IMLRO latch running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_IMLRO_1st_Latch]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {global quant IMLRO latch running}
  update_register ( TAGEXT := testtag,
                      CARD := ADDRESS(mtgcttss),
                  REGISTER := ADDRESS(mtgcttss.channelreg[tss_ct_IMLRO_2nd_Latch]),
                     IOPAR := iotest,
                      DATA := tss_sel_rom ) ; {global quant IMLRO latch running}

END ;
{ **************************************************************************** }
{ **************************************************************************** }
PROCEDURE load_all_ctfe_in_cell ( cell_sign_eta : eta_polarity ;
                                  cell_magn_eta : magn_eta_per_fe_cell ;
                             half_cell_quad_phi : phi_per_fe_half_cell ;
                                common_adc_simu : byte := 0 ;
                               common_threshold : byte := 255 ) ;

VAR

  status      : status_type ;
  phi         : phi_value ;
  low_phi     : phi_value ;
  hig_phi     : phi_value ;
  p_ctfe_ctrl :^ctfe_card_high_half ;
  rele        : relative_eta ;
  rf_typ      : threshold_reference_set_type ;
  rf_num      : threshold_reference_set_number ;

BEGIN

  save_tracing_status ;
  modify_trace_err ( CONSOLE := OFF, LOGFILE := OFF, REPORT := FALSE ) ;

  low_phi := CONVERT(phi_value, ( 8 * ORD(half_cell_quad_phi) + 1 ) ) ;
  hig_phi := CONVERT(phi_value, ( 8 * ORD(half_cell_quad_phi) + 8 ) ) ;

  FOR phi := low_phi TO hig_phi
  DO BEGIN

    p_ctfe_ctrl := ADDRESS ( ctfe_ctrl[cell_sign_eta,cell_magn_eta,phi] ) ;

    update_register ( TAGEXT := testtag,
                        CARD := p_ctfe_ctrl,
                    REGISTER := ADDRESS(p_ctfe_ctrl^.brdctrl),
                       IOPAR := iotest,
                        DATA := 128, {simu data, normal clock, load simu mode}
                      STATUS := status ) ;

    update_register ( TAGEXT := testtag,
                        CARD := p_ctfe_ctrl,
                    REGISTER := ADDRESS(p_ctfe_ctrl^.loadsimreg),
                       IOPAR := iotest,
                        DATA := common_adc_simu ) ;

    update_register ( TAGEXT := testtag,
                        CARD := p_ctfe_ctrl,
                    REGISTER := ADDRESS(p_ctfe_ctrl^.chanctrl),
                       IOPAR := iotest,
                        DATA := 255 ) ; {all channels updated @TSS i.e. cleared }

    update_register ( TAGEXT := testtag,
                        CARD := p_ctfe_ctrl,
                    REGISTER := ADDRESS(p_ctfe_ctrl^.chanctrl),
                       IOPAR := iotest,
                        DATA := 0 ) ; {no channel updated}


    FOR rele := rele_0 TO rele_3
    DO FOR rf_typ := EMEt_ref TO TOTEt_ref
    DO FOR rf_num := ref_0 TO ref_3
    DO BEGIN

      update_register ( TAGEXT := testtag,
                          CARD := p_ctfe_ctrl,
                      REGISTER := ADDRESS(p_ctfe_ctrl^.thrreg[rele,rf_typ,rf_num]),
                         IOPAR := iotest,
                          DATA := common_threshold ) ; {all thresholds set to maximum}

    END ;{rf_num,rf_typ&rele}

end_of_card:

  END ;{phi}

  restore_tracing_status ( REPORT := FALSE ) ;

END ;
{ **************************************************************************** }
{ **************************************************************************** }
END.